Doc lsu (#2359)

core/load_unit.sv

@@ -31,53 +31,53 @@ module load_unit
     input logic clk_i,
     // Asynchronous reset active low - SUBSYSTEM
     input logic rst_ni,
-    // TO_BE_COMPLETED - TO_BE_COMPLETED
+    // Flush signal - CONTROLLER
     input logic flush_i,
-    // Load unit input port - TO_BE_COMPLETED
+    // Load request is valid - LSU_BYPASS
     input logic valid_i,
-    // TO_BE_COMPLETED - TO_BE_COMPLETED
+    // Load request input - LSU_BYPASS
     input lsu_ctrl_t lsu_ctrl_i,
-    // TO_BE_COMPLETED - TO_BE_COMPLETED
+    // Pop the load request from the LSU bypass FIFO - LSU_BYPASS
     output logic pop_ld_o,
-    // Load unit result is valid - TO_BE_COMPLETED
+    // Load unit result is valid - ISSUE_STAGE
     output logic valid_o,
-    // Load transaction ID - TO_BE_COMPLETED
+    // Load transaction ID - ISSUE_STAGE
     output logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_o,
-    // Load result - TO_BE_COMPLETED
+    // Load result - ISSUE_STAGE
     output logic [CVA6Cfg.XLEN-1:0] result_o,
-    // Load exception - TO_BE_COMPLETED
+    // Load exception - ISSUE_STAGE
     output exception_t ex_o,
-    // Request address translation - TO_BE_COMPLETED
+    // Request address translation - MMU
     output logic translation_req_o,
-    // Virtual address - TO_BE_COMPLETED
+    // Virtual address - MMU
     output logic [CVA6Cfg.VLEN-1:0] vaddr_o,
-    // Transformed trap instruction out - TO_BE_COMPLETED
+    // Transformed trap instruction out - MMU
     output logic [31:0] tinst_o,
-    // Instruction is a hyp load store instruction - TO_BE_COMPLETED
+    // Instruction is a hyp load store instruction - MMU
     output logic hs_ld_st_inst_o,
-    // Hyp load store with execute permissions - TO_BE_COMPLETED
+    // Hyp load store with execute permissions - MMU
     output logic hlvx_inst_o,
-    // Physical address - TO_BE_COMPLETED
+    // Physical address - MMU
     input logic [CVA6Cfg.PLEN-1:0] paddr_i,
-    // Excepted which appears before load - TO_BE_COMPLETED
+    // Excepted which appears before load - MMU
     input exception_t ex_i,
-    // Data TLB hit - lsu
+    // Data TLB hit - MMU
     input logic dtlb_hit_i,
-    // TO_BE_COMPLETED - TO_BE_COMPLETED
+    // Physical page number from the DTLB - MMU
     input logic [CVA6Cfg.PPNW-1:0] dtlb_ppn_i,
-    // TO_BE_COMPLETED - TO_BE_COMPLETED
+    // Page offset for address checking - STORE_UNIT
     output logic [11:0] page_offset_o,
-    // TO_BE_COMPLETED - TO_BE_COMPLETED
+    // Indicates if the page offset matches a store unit entry - STORE_UNIT
     input logic page_offset_matches_i,
-    // Store buffer is empty - TO_BE_COMPLETED
+    // Store buffer is empty - STORE_UNIT
     input logic store_buffer_empty_i,
-    // TO_BE_COMPLETED - TO_BE_COMPLETED
+    // Transaction ID of the committing instruction - COMMIT_STAGE
     input logic [CVA6Cfg.TRANS_ID_BITS-1:0] commit_tran_id_i,
     // Data cache request out - CACHES
     input dcache_req_o_t req_port_i,
     // Data cache request in - CACHES
     output dcache_req_i_t req_port_o,
-    // TO_BE_COMPLETED - TO_BE_COMPLETED
+    // Presence of non-idempotent operations in the D$ write buffer - CACHES
     input logic dcache_wbuffer_not_ni_i
 );
   enum logic [3:0] {

docs/04_cv32a65x/design/source/cv32a6_execute.rst

@@ -139,16 +139,27 @@ Furthermore, the store_unit module provides information to the load_unit to know
 load_unit
 ---------
 
-The load_unit module manages the data load operations.
+The load unit module manages the data load operations.
 
 Before issuing a load, the load unit needs to check the store buffer for potential aliasing.
-It inserts stalls until it can satisfy the current request. This means:
+It stalls until it can satisfy the current request. This means:
 
 * Two loads to the same address are allowed.
 * Two stores to the same address are allowed.
-* A store followed by a load to the same address can only be satisfied if the store has already been committed (marked as committed in the store buffer).
+* A store after a load to the same address is allowed.
+* A load after a store to the same address can only be processed if the store has already been sent to the cache i.e there is no fowarding.
 
-.. TO_BE_COMPLETED, But once the store is committed, do we do forwarding without waiting for the store to actually be finished? Or do we authorize the outcome of the load, which will be carried out in memory/cache?
+After the check of the store buffer, a read request is sent to the D$ with the index field of the address (1).
+The load unit stalls until the D$ acknowledges this request (2).
+In the next cycle, the tag field of the address is sent to the D$ (3).
+If the load request address is non-idempotent, it stalls until the write buffer of the D$ is empty of non-idempotent requests and the store buffer is empty.
+It also stalls until the incoming load instruction is the next instruction to be committed.
+When the D$ allows the read of the data, the data is sent to the load unit and the load instruction can be committed (4).
+
+.. figure:: ../images/schema_fsm_load_control.png
+   :align: center
+
+   Load unit's interactions
 
 .. include:: port_load_unit.rst
 
@@ -157,7 +168,7 @@ It inserts stalls until it can satisfy the current request. This means:
 lsu_bypass
 ----------
 
-TO BE COMPLETED
+The LSU bypass is a FIFO which keeps instructions from the issue stage when the store unit or the load unit are not available immediately.
 
 .. include:: port_lsu_bypass.rst
 

docs/04_cv32a65x/design/source/port_load_unit.rst

@@ -32,98 +32,98 @@
 
    * - ``flush_i``
      - in
-     - TO_BE_COMPLETED
-     - TO_BE_COMPLETED
+     - Flush signal
+     - CONTROLLER
      - logic
 
    * - ``valid_i``
      - in
-     - Load unit input port
-     - TO_BE_COMPLETED
+     - Load request is valid
+     - LSU_BYPASS
      - logic
 
    * - ``lsu_ctrl_i``
      - in
-     - TO_BE_COMPLETED
-     - TO_BE_COMPLETED
+     - Load request input
+     - LSU_BYPASS
      - lsu_ctrl_t
 
    * - ``pop_ld_o``
      - out
-     - TO_BE_COMPLETED
-     - TO_BE_COMPLETED
+     - Pop the load request from the LSU bypass FIFO
+     - LSU_BYPASS
      - logic
 
    * - ``valid_o``
      - out
      - Load unit result is valid
-     - TO_BE_COMPLETED
+     - ISSUE_STAGE
      - logic
 
    * - ``trans_id_o``
      - out
      - Load transaction ID
-     - TO_BE_COMPLETED
+     - ISSUE_STAGE
      - logic[CVA6Cfg.TRANS_ID_BITS-1:0]
 
    * - ``result_o``
      - out
      - Load result
-     - TO_BE_COMPLETED
+     - ISSUE_STAGE
      - logic[CVA6Cfg.XLEN-1:0]
 
    * - ``ex_o``
      - out
      - Load exception
-     - TO_BE_COMPLETED
+     - ISSUE_STAGE
      - exception_t
 
    * - ``translation_req_o``
      - out
      - Request address translation
-     - TO_BE_COMPLETED
+     - MMU
      - logic
 
    * - ``vaddr_o``
      - out
      - Virtual address
-     - TO_BE_COMPLETED
+     - MMU
      - logic[CVA6Cfg.VLEN-1:0]
 
    * - ``paddr_i``
      - in
      - Physical address
-     - TO_BE_COMPLETED
+     - MMU
      - logic[CVA6Cfg.PLEN-1:0]
 
    * - ``ex_i``
      - in
      - Excepted which appears before load
-     - TO_BE_COMPLETED
+     - MMU
      - exception_t
 
    * - ``page_offset_o``
      - out
-     - TO_BE_COMPLETED
-     - TO_BE_COMPLETED
+     - Page offset for address checking
+     - STORE_UNIT
      - logic[11:0]
 
    * - ``page_offset_matches_i``
      - in
-     - TO_BE_COMPLETED
-     - TO_BE_COMPLETED
+     - Indicates if the page offset matches a store unit entry
+     - STORE_UNIT
      - logic
 
    * - ``store_buffer_empty_i``
      - in
      - Store buffer is empty
-     - TO_BE_COMPLETED
+     - STORE_UNIT
      - logic
 
    * - ``commit_tran_id_i``
      - in
-     - TO_BE_COMPLETED
-     - TO_BE_COMPLETED
+     - Transaction ID of the committing instruction
+     - COMMIT_STAGE
      - logic[CVA6Cfg.TRANS_ID_BITS-1:0]
 
    * - ``req_port_i``
@@ -140,8 +140,8 @@
 
    * - ``dcache_wbuffer_not_ni_i``
      - in
-     - TO_BE_COMPLETED
-     - TO_BE_COMPLETED
+     - Presence of non-idempotent operations in the D$ write buffer
+     - CACHES
      - logic
 
 Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below