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https://github.com/openhwgroup/cva6.git
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[RVFI] Optimize CSRs (#1999)
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MarioOpenHWGroup
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parent
e1ee77e02d
commit
71ef48804a
5 changed files with 50 additions and 59 deletions
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@ -276,16 +276,13 @@ module cva6_rvfi
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`define CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME, CSR_SOURCE_NAME) \
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bit [CVA6Cfg.XLEN-1:0] ``CSR_NAME``_d; \
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always_ff @(posedge clk_i) begin \
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``CSR_NAME``_d <= {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}; \
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rvfi_csr_o.``CSR_NAME``.rdata = CSR_ENABLE_COND ? {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME} : 0; \
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end \
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always_comb begin \
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rvfi_csr_o.``CSR_NAME = CSR_ENABLE_COND ? \
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'{ rdata: ``CSR_NAME``_d , \
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wdata: { {{CVA6Cfg.XLEN-$bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME} }, \
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rmask: '1, wmask: '1} \
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: '0; \
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rvfi_csr_o.``CSR_NAME``.wdata = CSR_ENABLE_COND ? { {{CVA6Cfg.XLEN-$bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME} } : 0; \
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rvfi_csr_o.``CSR_NAME``.rmask = CSR_ENABLE_COND ? 1 : 0; \
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rvfi_csr_o.``CSR_NAME``.wmask = CSR_ENABLE_COND ? (rvfi_csr_o.``CSR_NAME``.rdata != {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}) : 0; \
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end
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`define COMMA ,
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@ -380,29 +377,7 @@ module cva6_rvfi
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genvar i;
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generate
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for (i = 0; i < 16; i++) begin
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always_ff @(posedge clk_i) begin
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pmpaddr_q[i] = (csr.pmpcfg_q[i].addr_mode[1] == 1'b1) ?
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{{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]}
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: {{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}} , csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1] , 1'b0 };
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end
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always_comb begin
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rvfi_csr_o.pmpaddr[i] = '{
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rdata: {'0, pmpaddr_q[i]},
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wdata:
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csr.pmpcfg_q[i].addr_mode[1]
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== 1'b1 ?
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{{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]}
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: {
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{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}
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,
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csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1]
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,
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1'b0
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},
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rmask: '1,
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wmask: '1
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};
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end
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`CONNECT_RVFI_FULL(1'b1, pmpaddr[i], csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0])
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end
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endgenerate
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;
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@ -46,12 +46,17 @@ module spike #(
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st_core_cntrl_cfg st;
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initial begin
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string core_name = "cva6";
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st = cva6pkg_to_core_cntrl_cfg(st);
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st.boot_addr_valid = 1'b1;
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st.boot_addr = 64'h0x10000;
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if ($test$plusargs("core_name")) begin
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$value$plusargs("core_name=%s", core_name);
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end
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rvfi_initialize(st);
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rvfi_initialize_spike("cva6", st);
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rvfi_initialize_spike(core_name, st);
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end
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@ -101,24 +106,30 @@ module spike #(
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s_core.csr_wdata[CSR_INDEX] = rvfi_csr_i.``CSR_NAME``.wdata;\
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s_core.csr_wmask[CSR_INDEX] = rvfi_csr_i.``CSR_NAME``.wmask;
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`GET_RVFI_CSR (CSR_MSTATUS , mstatus , 0)
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`GET_RVFI_CSR (CSR_MCAUSE , mcause , 1)
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`GET_RVFI_CSR (CSR_MEPC , mepc , 2)
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`GET_RVFI_CSR (CSR_MTVEC , mtvec , 3)
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`GET_RVFI_CSR (CSR_MISA , misa , 4)
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`GET_RVFI_CSR (CSR_MTVAL , mtval , 5)
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`GET_RVFI_CSR (CSR_MIDELEG , mideleg , 6)
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`GET_RVFI_CSR (CSR_MEDELEG , medeleg , 7)
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`GET_RVFI_CSR (CSR_SATP , satp , 8)
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`GET_RVFI_CSR (CSR_MIE , mie , 9)
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`GET_RVFI_CSR (CSR_STVEC , stvec , 10)
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`GET_RVFI_CSR (CSR_SSCRATCH , sscratch , 11)
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`GET_RVFI_CSR (CSR_SEPC , sepc , 12)
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`GET_RVFI_CSR (CSR_MSCRATCH , mscratch , 13)
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`GET_RVFI_CSR (CSR_STVAL , stval , 14)
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`GET_RVFI_CSR (CSR_SCAUSE , scause , 15)
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`GET_RVFI_CSR (CSR_PMPADDR0 , pmpaddr[0] , 16)
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`GET_RVFI_CSR (CSR_PMPCFG0 , pmpcfg0 , 17)
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`GET_RVFI_CSR (CSR_MSTATUS , mstatus , 0)
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`GET_RVFI_CSR (CSR_MCAUSE , mcause , 1)
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`GET_RVFI_CSR (CSR_MEPC , mepc , 2)
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`GET_RVFI_CSR (CSR_MTVEC , mtvec , 3)
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`GET_RVFI_CSR (CSR_MISA , misa , 4)
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`GET_RVFI_CSR (CSR_MTVAL , mtval , 5)
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`GET_RVFI_CSR (CSR_MIDELEG , mideleg , 6)
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`GET_RVFI_CSR (CSR_MEDELEG , medeleg , 7)
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`GET_RVFI_CSR (CSR_SATP , satp , 8)
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`GET_RVFI_CSR (CSR_MIE , mie , 9)
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`GET_RVFI_CSR (CSR_STVEC , stvec , 10)
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`GET_RVFI_CSR (CSR_SSCRATCH , sscratch , 11)
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`GET_RVFI_CSR (CSR_SEPC , sepc , 12)
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`GET_RVFI_CSR (CSR_MSCRATCH , mscratch , 13)
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`GET_RVFI_CSR (CSR_STVAL , stval , 14)
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`GET_RVFI_CSR (CSR_SCAUSE , scause , 15)
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`GET_RVFI_CSR (CSR_PMPCFG0 , pmpcfg0 , 16)
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`GET_RVFI_CSR (CSR_PMPCFG1 , pmpcfg1 , 17)
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`GET_RVFI_CSR (CSR_PMPCFG2 , pmpcfg2 , 18)
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`GET_RVFI_CSR (CSR_PMPCFG3 , pmpcfg3 , 19)
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for (int i = 0; i < 16; i++) begin
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`GET_RVFI_CSR (CSR_PMPADDR0 + i , pmpaddr[i] , 20 + i)
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end
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`GET_RVFI_CSR (CSR_MINSTRET , instret , 37)
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rvfi_spike_step(s_core, s_reference_model);
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rvfi_compare(s_core, s_reference_model);
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@ -31,11 +31,9 @@ if ! [ -n "$DV_SIMULATORS" ]; then
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fi
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if ! [ -n "$UVM_VERBOSITY" ]; then
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UVM_VERBOSITY=UVM_NONE
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export UVM_VERBOSITY=UVM_NONE
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fi
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export DV_OPTS="$DV_OPTS --issrun_opts=\"+UVM_VERBOSITY=$UVM_VERBOSITY\""
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make clean
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make -C verif/sim clean_all
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@ -33,10 +33,10 @@ if ! [ -n "$DV_SIMULATORS" ]; then
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fi
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if ! [ -n "$UVM_VERBOSITY" ]; then
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UVM_VERBOSITY=UVM_NONE
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export UVM_VERBOSITY=UVM_NONE
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fi
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export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
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export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1"
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cd verif/sim/
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python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
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@ -144,7 +144,7 @@ vcs-testharness:
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veri-testharness:
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make -C $(path_var) verilate verilator="verilator --no-timing" target=$(target) defines=$(subst +define+,,$(isscomp_opts))
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$(path_var)/work-ver/Variane_testharness $(if $(TRACE_COMPACT), -f verilator.fst) $(if $(TRACE_FAST), -v verilator.vcd) $(elf) $(issrun_opts) \
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+elf_file=$(elf) +tohost_addr=$(shell $$RISCV/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1)
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$(COMMON_PLUS_ARGS)
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# If present, move default waveform files to log directory.
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# Keep track of target in waveform file name.
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[ ! -f verilator.fst ] || mv verilator.fst `dirname $(log)`/`basename $(log) .log`.fst
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@ -206,15 +206,22 @@ COMMON_COMP_UVM_FLAGS = \
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+incdir+$(CVA6_REPO_DIR)/verif/env/uvme +incdir+$(CVA6_REPO_DIR)/verif/tb/uvmt \
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$(if $(spike-tandem), +define+SPIKE_TANDEM=1)
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COMMON_RUN_UVM_FLAGS = \
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-sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv \
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-sv_lib $(SPIKE_INSTALL_DIR)/lib/libfesvr \
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-sv_lib $(SPIKE_INSTALL_DIR)/lib/libdisasm \
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COMMON_PLUS_ARGS = \
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++$(elf) \
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+elf_file=$(elf) \
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+tohost_addr=$(shell $$RISCV/bin/$(CV_SW_PREFIX)nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
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+signature=$(elf).signature_output +UVM_TESTNAME=uvmt_cva6_firmware_test_c
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ifneq ($(UVM_VERBOSITY),)
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COMMON_PLUS_ARGS += +UVM_VERBOSITY=$(UVM_VERBOSITY)
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endif
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COMMON_RUN_UVM_FLAGS = \
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-sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv \
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-sv_lib $(SPIKE_INSTALL_DIR)/lib/libfesvr \
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-sv_lib $(SPIKE_INSTALL_DIR)/lib/libdisasm \
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$(COMMON_PLUS_ARGS)
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ALL_UVM_FLAGS = -lca -sverilog +incdir+$(VCS_HOME)/etc/uvm/src \
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$(VCS_HOME)/etc/uvm/src/uvm_pkg.sv -ntb_opts uvm-1.2 -timescale=1ns/1ps \
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-assert svaext -race=all -ignore unique_checks -full64 -q +incdir+$(VCS_HOME)/etc/uvm/src \
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