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SV32-DV-Plan Execution (#1376)
This commit is contained in:
Ammar Khan
GitHub
parent
d455c122ed
commit
72143ef0a9
43 changed files with 7587 additions and 0 deletions
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@ -208,6 +208,19 @@ csr_test:
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script: source verif/regress/dv-riscv-csr-access-test.sh
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after_script: *simu_after_script
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mmu_sv32_tests:
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extends:
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- .regress_test
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variables:
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DASHBOARD_JOB_TITLE: "mmu_sv32_tests $DV_TARGET"
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DASHBOARD_JOB_DESCRIPTION: "MMU SV32 regression suite"
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DASHBOARD_SORT_INDEX: 0
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DASHBOARD_JOB_CATEGORY: "Test suites"
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DV_SIMULATORS: "veri-testharness,spike"
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DV_TARGET: cv32a60x
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script: source verif/regress/dv-riscv-mmu-sv32-test.sh
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after_script: *simu_after_script
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hwconfig:
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extends:
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- .regress_test
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31
verif/regress/dv-riscv-mmu-sv32-test.sh
Normal file
31
verif/regress/dv-riscv-mmu-sv32-test.sh
Normal file
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@ -0,0 +1,31 @@
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# Copyright 2021 Thales DIS design services SAS
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#
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# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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# You may obtain a copy of the License at https://solderpad.org/licenses/
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#
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# Original Author: Jean-Roch COULON - Thales
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# where are the tools
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if ! [ -n "$RISCV" ]; then
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echo "Error: RISCV variable undefined"
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return
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fi
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# install the required tools
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source verif/regress/install-cva6.sh
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source verif/regress/install-riscv-dv.sh
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source verif/regress/install-riscv-arch-test.sh
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if ! [ -n "$DV_TARGET" ]; then
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DV_TARGET=cv32a60x
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fi
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if ! [ -n "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=veri-testharness,spike
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fi
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cd verif/sim
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python3 cva6.py --testlist=../tests/testlist_riscv-mmu-sv32-arch-test-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
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cd -
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106
verif/tests/custom/sv32/macros.h
Normal file
106
verif/tests/custom/sv32/macros.h
Normal file
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@ -0,0 +1,106 @@
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#include "../env/encoding.h"
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#define _start rvtest_entry_point
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#define SMODE_ECALL ecall
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#define UMODE_ECALL ecall
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#define LEVEL0 0x00
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#define LEVEL1 0x01
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#define SUPERPAGE_SHIFT 22
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#define PTE(PA, PR) ;\
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srli PA, PA, RISCV_PGSHIFT ;\
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slli PA, PA, PTE_PPN_SHIFT ;\
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or PA, PA, PR ;
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#define PTE_SETUP_RV32(PA, PR, TMP, VA, PGTB_ADDR,LEVEL) ;\
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PTE(PA, PR) ;\
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.if (LEVEL==1) ;\
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la TMP, PGTB_ADDR ;\
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srli VA, VA, SUPERPAGE_SHIFT ;\
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.endif ;\
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.if (LEVEL==0) ;\
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la TMP, PGTB_ADDR ;\
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slli VA, VA, PTE_PPN_SHIFT ;\
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srli VA, VA, SUPERPAGE_SHIFT ;\
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.endif ;\
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slli VA, VA, 2 ;\
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add TMP, TMP, VA ;\
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sw PA, 0(TMP) ;
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#define SATP_SETUP_SV32(PGTB_ADDR) ;\
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la t6, PGTB_ADDR ;\
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li t5, SATP32_MODE ;\
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srli t6, t6, RISCV_PGSHIFT ;\
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or t6, t6, t5 ;\
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csrw satp, t6 ;\
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sfence.vma ;
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#define CHANGE_T0_S_MODE(MEPC_ADDR) ;\
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li t0, MSTATUS_MPP ;\
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csrc mstatus, t0 ;\
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li t1, MSTATUS_MPP & ( MSTATUS_MPP >> 1) ;\
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csrs mstatus, t1 ;\
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csrw mepc, MEPC_ADDR ;\
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mret ;
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#define CHANGE_T0_U_MODE(MEPC_ADDR) ;\
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li t0, MSTATUS_MPP ;\
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csrc mstatus, t0 ;\
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csrw mepc, MEPC_ADDR ;\
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mret ;
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#define RVTEST_EXIT_LOGIC ;\
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exit: ;\
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add t1, zero, x1 ;\
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slli t1, t1, 1 ;\
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addi t1, t1, 1 ;\
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la t0, tohost ;\
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sw t1, 0(t0) ;\
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j exit ;
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#define COREV_VERIF_EXIT_LOGIC ;\
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exit: ;\
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slli x1, x1, 1 ;\
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addi x1, x1, 1 ;\
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mv x30, s1 ;\
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sw x1, tohost, x30 ;\
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self_loop: j self_loop ;
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#define ALL_MEM_PMP ;\
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li t2, -1 ;\
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csrw pmpaddr0, t2 ;\
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li t2, 0x0F ;\
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csrw pmpcfg0, t2 ;\
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sfence.vma ;
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#define TEST_PROLOG(ADDR,CAUSE) ;\
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la t1, rvtest_check ;\
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la t2, ADDR ;\
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li t3, CAUSE ;\
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li t4, 1 ;\
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sw t4, 0(t1) ;\
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sw t2, 4(t1) ;\
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sw t3, 8(t1) ;\
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la a1,rvtest_data ;
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.macro INCREMENT_MEPC label_suffix ;\
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csrr t1, mepc ;\
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lw t5, 0(t1) ;\
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li t2, 3 ;\
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and t5, t5, t2 ;\
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bne t2, t5, not_32_bit_Instr_\label_suffix ;\
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addi t1, t1, 4 ;\
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j write_mepc_\label_suffix ;\
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not_32_bit_Instr_\label_suffix: ;\
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addi t1, t1, 2 ;\
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write_mepc_\label_suffix: ;\
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csrw mepc, t1 ;\
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.endm ;
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#define TEST_STATUS ;\
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la a1, rvtest_check ;\
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lw t1, 0(a1) ;\
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bne t1, x0, test_fail ;
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197
verif/tests/custom/sv32/vm_access_bit_level_0.S
Normal file
197
verif/tests/custom/sv32/vm_access_bit_level_0.S
Normal file
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@ -0,0 +1,197 @@
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#=======================================================================
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# RWX Access of Level0 PTE in User and Supervisor mode when access
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# bit is low
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#-----------------------------------------------------------------------
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# Test Description:
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#
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# If implementation does not sets the pte.A on accessing the PTE,
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# and PTE has pte.A=0, then accessing it would raise page fault
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# exception of the corresponding access type.
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#
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# - Set pte.r=1 & pte.a=0 and test the read acces.
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# - Set pte.w=1 & pte.a=0 and test the write access.
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# - Set pte.x=1 & pte.a=0 and test the execute access.
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#
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#=======================================================================
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#include "macros.h"
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#define _MMODE_ "M"
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#define _SUMODE_ "SU"
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#ifdef smode
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#define SET_PTE_U 0
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#else
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#define SET_PTE_U PTE_U
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#endif
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.text
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.global _start
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.option norvc
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_start:
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ALL_MEM_PMP # PMP permission to all the mem
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la t1,trap_handler # loads the address of trap handler
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csrw mtvec,t1 # sets the mtvec to trap handler
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PTE_LEVEL0:
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# ----------------LEVEL 0 PTE Setup for load and store test---------------------
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la a1,pgtb_l0 # loads the address of label pgtb_l0
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la a0, _start # VA = PA - Identity Map
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ori a2, x0, ( PTE_V ) # sets the permission bits
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PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
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la a1,vm_en # loads the address of label vm_en
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mv a0, a1 # VA = PA - Identity Map
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ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
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PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
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la a1,rvtest_data # loads the address of label rvtest_data
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mv a0, a1 # VA = PA - Identity Map
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ori a2, x0, ( PTE_D | SET_PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
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PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
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la a1,rvtest_check # loads the address of label rvtest_data
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mv a0, a1 # VA = PA - Identity Map
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ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R | PTE_V) # sets the permission bits
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PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
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# ----------------Set the SATP and change the mode---------------------
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SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
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la a1,vm_en # loads the address of vm_en
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#ifdef smode
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CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
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#else
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CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
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#endif
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# ----------------Virtualization Enabeled---------------------
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vm_en:
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# -------------------Load Test Prolog-------------------------
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TEST_PROLOG(check_load, CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
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check_load: # test the load access
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lw t1,0(a1)
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TEST_STATUS # checks the status of the test
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nop
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# -------------------Store Test Prolog------------------------
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TEST_PROLOG(check_store, CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
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check_store: # test the store access
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sw t1,0(a1)
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nop
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TEST_STATUS # checks the status of the test
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#ifdef smode
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SMODE_ECALL # SMODE ecall
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#else
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UMODE_ECALL # UMODE ecall
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#endif
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# -------------------Execute Test Prolog-----------------------
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TEST_PROLOG(check_execute, CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
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PTE_LEVEL0_EXECUTE:
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# -------------LEVEL 1 PTE Setup for execute test------------------------
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# Setup a new PTE to test execute
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la a1,check_execute # loads the address of label vm_en
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mv a0, a1 # VA = PA - Identity Map
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ori a2, x0, ( PTE_D | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
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PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
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# ----------------Set the SATP and change the mode---------------------
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SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
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la a1,check_execute # loads the address of check_execute
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#ifdef smode
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CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
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#else
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CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
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#endif
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check_execute: # test the execute access
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li t1, 0x45 # page fault should raise
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TEST_STATUS
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j test_pass
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trap_handler:
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csrr t0, mcause # read the value of mcause
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la t1, rvtest_check # load the address of trvtest_check
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lw t2, 0(t1) # if cause expected then load 1 else 0
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lw t3, 4(t1) # load the expected value of mepc
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lw t4, 8(t1) # load the expected value of mcause
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li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
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beq t0,t1,continue_in_m_mode # checks if ecall is occured
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li t1, CAUSE_USER_ECALL # load the value of user ecall
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beq t0,t1,continue_in_m_mode # checks for ecall is occured
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beqz t2, test_fail # Jumps to exit if cause is not expected
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csrr t5,mepc # read the value of mepc
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bne t3,t5, test_fail # check the value of mepc with it's expected value
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bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
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li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
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beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
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continue_execution:
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INCREMENT_MEPC _SUMODE_ # update the value of mepc
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j trap_epilogs
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continue_in_m_mode:
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INCREMENT_MEPC _MMODE_ # update the value of mepc
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li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
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csrs mstatus,t1 # update the value mstatus MPP
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trap_epilogs:
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la t1, rvtest_check # load the addr of rvtest_check
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li t2, 0
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sw t2, 0(t1) # Clear the expected cause
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sw t2, 4(t1) # Clear the exception PC
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sw t2, 8(t1) # Clear cause execution number
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mret
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test_pass:
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li x1, 0 # Write 0 in x1 if test pass
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j exit # Jump to exit
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test_fail:
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li x1, 1 # Write 1 in x1 if test failed
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COREV_VERIF_EXIT_LOGIC # Exit logic
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.data
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rvtest_check:
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.word 0xdeadbeef # 1 for cause expected 0 for no cause
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.word 0xbeefdead # write the value of mepc here (where cause is expected)
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.word 0xcafecafe # write the value of expect cause
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.align 12
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rvtest_data:
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.word 0xbeefcafe
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.word 0xdeadcafe
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.word 0x00000000
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.word 0x00000000
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.align 12
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pgtb_l1:
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.zero 4096
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pgtb_l0:
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.zero 4096
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.align 4; .global tohost; tohost: .dword 0;
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.align 4; .global fromhost; fromhost: .dword 0;
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194
verif/tests/custom/sv32/vm_access_bit_level_1.S
Normal file
194
verif/tests/custom/sv32/vm_access_bit_level_1.S
Normal file
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@ -0,0 +1,194 @@
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#=======================================================================
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# RWX Access of Level1 PTE in User and Supervisor mode when access
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# bit is low
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#-----------------------------------------------------------------------
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# Test Description:
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#
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# If implementation does not sets the pte.A on accessing the PTE,
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# and PTE has pte.A=0, then accessing it would raise page fault
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# exception of the corresponding access type.
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#
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# - Set pte.r=1 & pte.a=0 and test the read acces.
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# - Set pte.w=1 & pte.a=0 and test the write access.
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# - Set pte.x=1 & pte.a=0 and test the execute access.
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#
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#=======================================================================
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#include "macros.h"
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#define _MMODE_ "M"
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#define _SUMODE_ "SU"
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#ifdef smode
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#define SET_PTE_U 0
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#else
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#define SET_PTE_U PTE_U
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#endif
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.text
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.global _start
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.option norvc
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_start:
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ALL_MEM_PMP # PMP permission to all the mem
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la t1,trap_handler # loads the address of trap handler
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csrw mtvec,t1 # sets the mtvec to trap handler
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PTE_LEVEL1:
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# ----------------LEVEL 1 PTE Setup for load and store test---------------------
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la a1,vm_en # loads the address of label vm_en
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mv a0, a1 # VA = PA - Identity Map
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ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
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PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
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la a1,rvtest_data # loads the address of label rvtest_data
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mv a0, a1 # VA = PA - Identity Map
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ori a2, x0, ( PTE_D | SET_PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
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PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
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la a1,rvtest_check # loads the address of label rvtest_data
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mv a0, a1 # VA = PA - Identity Map
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ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R | PTE_V) # sets the permission bits
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PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
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# ----------------Set the SATP and change the mode---------------------
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SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
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la a1,vm_en # loads the address of vm_en
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#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled---------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# -------------------Load Test Prolog-------------------------
|
||||
|
||||
TEST_PROLOG(check_load, CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
check_load: # test the load access
|
||||
|
||||
lw t1,0(a1)
|
||||
TEST_STATUS # checks the status of the test
|
||||
nop
|
||||
|
||||
# -------------------Store Test Prolog------------------------
|
||||
|
||||
TEST_PROLOG(check_store, CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
check_store: # test the store access
|
||||
sw t1,0(a1)
|
||||
nop
|
||||
TEST_STATUS # checks the status of the test
|
||||
#ifdef smode
|
||||
SMODE_ECALL # SMODE ecall
|
||||
#else
|
||||
UMODE_ECALL # UMODE ecall
|
||||
#endif
|
||||
|
||||
# -------------------Execute Test Prolog-----------------------
|
||||
|
||||
TEST_PROLOG(check_execute, CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
PTE_LEVEL1_EXECUTE:
|
||||
|
||||
# -------------LEVEL 1 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_execute # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,check_execute # loads the address of check_execute
|
||||
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
|
||||
check_execute: # test the execute access
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
csrr t5,mepc # read the value of mepc
|
||||
|
||||
bne t3,t5, test_fail # check the value of mepc with it's expected value
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # Exit logic
|
||||
|
||||
.data
|
||||
.align 24
|
||||
rvtest_check:
|
||||
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
198
verif/tests/custom/sv32/vm_bare_mode_level_0.S
Normal file
198
verif/tests/custom/sv32/vm_bare_mode_level_0.S
Normal file
|
|
@ -0,0 +1,198 @@
|
|||
#=======================================================================
|
||||
# SATP mode = Bare for Level 1 PTE
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE does not have the SATP setuped then, accessing it
|
||||
# would raise a ILLEGAL_INSTRUCTION fault exception.
|
||||
# When satp.mode=Bare and PTE has (r,w,x) PMP permissions, this test
|
||||
# covers the following scenarios in both supervisor and user privilege
|
||||
# modes for level 1 PTE.
|
||||
#
|
||||
# Set SATP = Bare and rest bits to zeros and test the access to PTE.
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
.set va, 0x82000000
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test------------
|
||||
|
||||
la a1,pgtb_l0 # loads the address of label pgtb_l0
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l0, LEVEL0 ) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 (a1, a2, t1, a0, pgtb_l0, LEVEL0 ) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP to Bare_Mode and change the mode----------
|
||||
|
||||
csrw satp, x0 # Write satp with all zeros (bare mode)
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
|
||||
sw t1,0(a1) # test the store access
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
|
||||
#ifdef smode
|
||||
SMODE_ECALL # changes mode M to S and set the MEPC
|
||||
#else
|
||||
UMODE_ECALL # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
# ----------------------Access test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(va,CAUSE_ILLEGAL_INSTRUCTION) # load the addr and expected cause
|
||||
|
||||
# -------------LEVEL 1 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_access # loads the address of label vm_en
|
||||
la a0, va # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP to Bare_Mode and change the mode---------------------
|
||||
|
||||
csrw satp, x0 # Write satp with all zeros (bare mode)
|
||||
la a1 , va # loads the virual address of check_access
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
|
||||
check_access: # check access to PTE first with va then with physical address
|
||||
|
||||
li t1, 0x45
|
||||
TEST_STATUS # checks the status of the test
|
||||
j test_pass # Jump to exit
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_ILLEGAL_INSTRUCTION # load the value of illegal instruction fault
|
||||
beq t0,t5,Back_to_check_access # if illegal instruction fault jump to check access in M mod
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
Back_to_check_access:
|
||||
|
||||
la t3,check_access # loads the address of check_access
|
||||
csrw mepc,t3 # update the value of mepc with check_access address
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
j trap_epilogs
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # Exit logic
|
||||
|
||||
.data
|
||||
.align 24 # Superpage align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
193
verif/tests/custom/sv32/vm_bare_mode_level_1.S
Normal file
193
verif/tests/custom/sv32/vm_bare_mode_level_1.S
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
#=======================================================================
|
||||
# SATP mode = Bare for Level 1 PTE
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE does not have the SATP setuped then, accessing it
|
||||
# would raise a ILLEGAL_INSTRUCTION fault exception.
|
||||
# When satp.mode=Bare and PTE has (r,w,x) PMP permissions, this test
|
||||
# covers the following scenarios in both supervisor and user privilege
|
||||
# modes for level 1 PTE.
|
||||
#
|
||||
# Set SATP = Bare and rest bits to zeros and test the access to PTE.
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
.set va, 0x82000000
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test------------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP to Bare_Mode and change the mode----------
|
||||
|
||||
csrw satp, x0 # Write satp with all zeros (bare mode)
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
|
||||
sw t1,0(a1) # test the store access
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
|
||||
#ifdef smode
|
||||
SMODE_ECALL # changes mode M to S and set the MEPC
|
||||
#else
|
||||
UMODE_ECALL # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
# ----------------------Access test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(va,CAUSE_ILLEGAL_INSTRUCTION) # load the addr and expected cause
|
||||
|
||||
# -------------LEVEL 1 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_access # loads the address of label vm_en
|
||||
la a0, va # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP to Bare_Mode and change the mode---------------------
|
||||
|
||||
csrw satp, x0 # Write satp with all zeros (bare mode)
|
||||
la a1 , va # loads the virual address of check_access
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
|
||||
check_access: # check access to PTE first with va then with physical address
|
||||
|
||||
li t1, 0x45
|
||||
TEST_STATUS # checks the status of the test
|
||||
j test_pass # Jump to exit
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_ILLEGAL_INSTRUCTION # load the value of illegal instruction fault
|
||||
beq t0,t5,Back_to_check_access # if illegal instruction fault jump to check access in M mod
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
Back_to_check_access:
|
||||
|
||||
la t3,check_access # loads the address of check_access
|
||||
csrw mepc,t3 # update the value of mepc with check_access address
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
j trap_epilogs
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # Exit logic
|
||||
|
||||
.data
|
||||
.align 24 # Superpage align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
156
verif/tests/custom/sv32/vm_dirty_bit_level_0.S
Normal file
156
verif/tests/custom/sv32/vm_dirty_bit_level_0.S
Normal file
|
|
@ -0,0 +1,156 @@
|
|||
#=======================================================================
|
||||
# Write Access of Level0 PTE in User and Supervisor mode when dirty
|
||||
# bit is low
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
# If implementation does not sets the pte.D when PTE is written,
|
||||
# then attempting to store on that PTE would
|
||||
# raise Store/AMO page fault exception, this test
|
||||
# covers the following scenarios in both supervisor and user privilege
|
||||
# modes for level0 PTE.
|
||||
# Level 0
|
||||
# - Set PTE.D = 0 and test the write access in Supervisor Mode
|
||||
# - Set PTE.D = 0 and test the write access in User Mode
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL1 PTE Setup to point to LEVEL0 PTE----------------
|
||||
la a1,pgtb_l0 # loads the address of label pgtb_l0
|
||||
mv a0, a1 # generrates the VA for label vm_en
|
||||
ori a2, x0, ( PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------LEVEL 0 PTE Setup for load and store test--------------
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_V | PTE_A | SET_PTE_U | PTE_W | PTE_R ) # sets the permission bits -- No dirty bit
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode-----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------------Store test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_store,CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
|
||||
sw t1,0(a1) # test the store access
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
j exit # Jump to exit
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_STORE_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
.align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
152
verif/tests/custom/sv32/vm_dirty_bit_level_1.S
Normal file
152
verif/tests/custom/sv32/vm_dirty_bit_level_1.S
Normal file
|
|
@ -0,0 +1,152 @@
|
|||
#=======================================================================
|
||||
# Write Access of Level1 PTE in User and Supervisor mode when dirty
|
||||
# bit is low
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
# If implementation does not sets the pte.D when PTE is written,
|
||||
# then attempting to store on that PTE would
|
||||
# raise Store/AMO page fault exception, this test
|
||||
# covers the following scenarios in both supervisor and user privilege
|
||||
# modes for level1 PTE.
|
||||
# Level 1
|
||||
# - Set PTE.D = 0 and test the write access in Supervisor Mode
|
||||
# - Set PTE.D = 0 and test the write access in User Mode
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test------------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_V | PTE_A | SET_PTE_U | PTE_W | PTE_R ) # sets the permission bits --No dirty bit
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------------Store test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_store,CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
sw t1,0(a1) # test the store access
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
j exit # Jump to exit
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_STORE_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
.align 24 # Superpage align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
202
verif/tests/custom/sv32/vm_invalid_pte_level_0.S
Normal file
202
verif/tests/custom/sv32/vm_invalid_pte_level_0.S
Normal file
|
|
@ -0,0 +1,202 @@
|
|||
#=======================================================================
|
||||
# RWX Access of Level0 PTE in User and Supervisor mode when valid
|
||||
# bit is low
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE does not have the Valid (pte.V=0) permission, accessing it
|
||||
# would raise a page fault exception of the corresponding access type.
|
||||
# When satp.mode=sv32 and PTE has (r,w,x) PMP permissions, this test
|
||||
# covers the following scenarios in both supervisor and user privilege
|
||||
# modes for level1 PTE.
|
||||
#
|
||||
# - Set PTE.V = 0 and test the read access.
|
||||
# - Set PTE.V = 0 and test the write access.
|
||||
# - Set PTE.V = 0 and test the execute access.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL1 PTE Setup to point to LEVEL0 PTE----------------
|
||||
la a1,pgtb_l0 # loads the address of label pgtb_l0
|
||||
mv a0, a1 # generrates the VA for label vm_en
|
||||
ori a2, x0, ( PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------LEVEL 0 PTE Setup for load and store test--------------
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode-----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------Load test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_load,CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
TEST_STATUS # checks the status of the test
|
||||
# ----------------Store test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_store,CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
|
||||
sw t1,0(a1) # test the store access
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
#ifdef smode
|
||||
SMODE_ECALL # changes mode M to S and set the MEPC
|
||||
#else
|
||||
UMODE_ECALL # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
# ----------------------Execute test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_execute,CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
# -------------LEVEL 0 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_execute # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,check_execute # loads the address of check_execute
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
|
||||
|
||||
check_execute:
|
||||
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
.align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
197
verif/tests/custom/sv32/vm_invalid_pte_level_1.S
Normal file
197
verif/tests/custom/sv32/vm_invalid_pte_level_1.S
Normal file
|
|
@ -0,0 +1,197 @@
|
|||
#=======================================================================
|
||||
# RWX Access of Level1 PTE in User and Supervisor mode when valid
|
||||
# bit is low
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE does not have the Valid (pte.V=0) permission, accessing it
|
||||
# would raise a page fault exception of the corresponding access type.
|
||||
# When satp.mode=sv32 and PTE has (r,w,x) PMP permissions, this test
|
||||
# covers the following scenarios in both supervisor and user privilege
|
||||
# modes for level1 PTE.
|
||||
#
|
||||
# - Set PTE.V = 0 and test the read access.
|
||||
# - Set PTE.V = 0 and test the execute access.
|
||||
# - Set PTE.V = 0 and test the write access.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test------------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------Load test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_load,CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
TEST_STATUS # checks the status of the test
|
||||
# ----------------Store test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_store,CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
|
||||
sw t1,0(a1) # test the store access
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
#ifdef smode
|
||||
SMODE_ECALL # changes mode M to S and set the MEPC
|
||||
#else
|
||||
UMODE_ECALL # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
# ----------------------Execute test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_execute,CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
# -------------LEVEL 1 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_execute # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,check_execute # loads the address of check_execute
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
|
||||
check_execute:
|
||||
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
.align 24 # Superpage align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
202
verif/tests/custom/sv32/vm_misaligned_superpage.S
Normal file
202
verif/tests/custom/sv32/vm_misaligned_superpage.S
Normal file
|
|
@ -0,0 +1,202 @@
|
|||
#=======================================================================
|
||||
# Misaligned Superpage for level 1 PTE for supevisor and user mode
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE at level1 is leaf PTE (superpage) and its pte.ppn[0]!=0, then
|
||||
# it is a misaligned superpage and accessing that PTE would raise page
|
||||
# fault exception of the corresponding access type.
|
||||
#
|
||||
# When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has
|
||||
# non-reserved RWX encodings, (pte.r | pte.x)=1, and pte.v=1, then test
|
||||
# the following in supervisor and user privilege mode for level1 PTE.
|
||||
#
|
||||
# - set pte.ppn[0]!=0 and test for read, write and execute access.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test------------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0,( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R| PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------Load test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_load,CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
# ----------------Store test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_store,CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
|
||||
sw t1,0(a1) # test the store access
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
#ifdef smode
|
||||
SMODE_ECALL # changes mode M to S and set the MEPC
|
||||
#else
|
||||
UMODE_ECALL # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
|
||||
# ----------------------Execute test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_execute,CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
# -------------LEVEL 1 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_execute # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,check_execute # loads the address of check_execute
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
|
||||
.align 12 # to make the address misliagned for execute access i.e ppn[0]!=0
|
||||
check_execute:
|
||||
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # Exit logic
|
||||
|
||||
.data
|
||||
.align 24 # Superpage align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22 # makes the ppn[0]!=0
|
||||
.word 0xdeadbeef # random word at the address where ppn[0]!=0
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
|
||||
176
verif/tests/custom/sv32/vm_mstatus_tvm_level_0.S
Normal file
176
verif/tests/custom/sv32/vm_mstatus_tvm_level_0.S
Normal file
|
|
@ -0,0 +1,176 @@
|
|||
#=======================================================================
|
||||
# RW Access of satp and sfence.vma in User and Supervisor mode when
|
||||
# mstatus.tvm = 1
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
# If mstatus.TVM=1, read and write access to the satp and sfence.vma will
|
||||
# raise illegal instruction exception in S-mode. This test
|
||||
# covers the following scenarios in both supervisor
|
||||
# modes for level0 PTE.
|
||||
# Level 0
|
||||
# - mstatus.tvm = 1 and test the RW access of satp and sfence in
|
||||
# in supervisor mode.
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL1 PTE Setup to point to LEVEL0 PTE----------------
|
||||
la a1,pgtb_l0 # loads the address of label pgtb_l0
|
||||
mv a0, a1 # generrates the VA for label pgtb_l0
|
||||
ori a2, x0, ( PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------LEVEL 0 PTE Setup for load and store test--------------
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_V | PTE_A | SET_PTE_U | PTE_D | PTE_W | PTE_R ) # sets the permission bits -- only W permission
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode-----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
li t4, MSTATUS_TVM
|
||||
csrs mstatus, t4 # TVM bit set on mstatus
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------------Load test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_load, CAUSE_ILLEGAL_INSTRUCTION) # load the addr and expected cause
|
||||
|
||||
check_load:
|
||||
|
||||
csrr t1, satp # tests the load access
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
# ----------------------store - satp test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_store,CAUSE_ILLEGAL_INSTRUCTION) # load the addr and expected cause
|
||||
|
||||
check_store:
|
||||
csrw satp, t1 # test the store access
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
# ----------------------store - sfence test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_store_sfence,CAUSE_ILLEGAL_INSTRUCTION) # load the addr and expected cause
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store_sfence:
|
||||
sfence.vma # test the store access
|
||||
TEST_STATUS # checks the status of the test
|
||||
SMODE_ECALL # SMODE ecall
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
j exit # Jump to exit
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
.align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
165
verif/tests/custom/sv32/vm_mstatus_tvm_level_1.S
Normal file
165
verif/tests/custom/sv32/vm_mstatus_tvm_level_1.S
Normal file
|
|
@ -0,0 +1,165 @@
|
|||
#=======================================================================
|
||||
# RW Access of satp and sfence.vma in User and Supervisor mode when
|
||||
# mstatus.tvm = 1
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
# If mstatus.TVM=1, read and write access to the satp and sfence.vma will
|
||||
# raise illegal instruction exception in S-mode. This test
|
||||
# covers the following scenarios in supervisor mode for level1 PTE.
|
||||
# Level 1
|
||||
# - mstatus.tvm = 1 and test the RW access of satp and sfence in
|
||||
# in supervisor mode.
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test------------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_V | PTE_A | SET_PTE_U | PTE_D | PTE_W | PTE_R ) # sets the permission bits -- only W permission
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
li t4, MSTATUS_TVM
|
||||
csrs mstatus, t4 # TVM bit set on mstatus
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------------Load test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_load, CAUSE_ILLEGAL_INSTRUCTION) # load the addr and expected cause
|
||||
|
||||
check_load:
|
||||
|
||||
csrr t1, satp # tests the load access
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
# ----------------------store - satp test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_store,CAUSE_ILLEGAL_INSTRUCTION) # load the addr and expected cause
|
||||
|
||||
check_store:
|
||||
csrw satp, t1 # test the store access
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
# ----------------------store - sfence test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_store_sfence,CAUSE_ILLEGAL_INSTRUCTION) # load the addr and expected cause
|
||||
|
||||
check_store_sfence:
|
||||
sfence.vma # test the store access
|
||||
TEST_STATUS # checks the status of the test
|
||||
SMODE_ECALL
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
j exit # Jump to exit
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
.align 24 # Superpage align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
159
verif/tests/custom/sv32/vm_mxr_clear_level_0.S
Normal file
159
verif/tests/custom/sv32/vm_mxr_clear_level_0.S
Normal file
|
|
@ -0,0 +1,159 @@
|
|||
#=======================================================================
|
||||
# Load Access of Level1 PTE in User and Supervisor mode when
|
||||
# mstatus.MXR is unset
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE has only execute permission (pte.x = 1) and s/mstatus.MXR=0,
|
||||
# then read access on that PTE should raise load page fault exception.
|
||||
#
|
||||
# - Set pte.r=0 & pte.w=0 & pte.x=1 & s/mstatus.MXR=0 and test the
|
||||
# read acces.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the mem
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
PTE_LEVEL0:
|
||||
|
||||
# ----------------LEVEL 0 PTE Setup for load test---------------------
|
||||
|
||||
la a1,pgtb_l0 # loads the address of label pgtb_l0
|
||||
la a0, _start # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R | PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
li a1, MSTATUS_MXR
|
||||
csrc mstatus, a1 # Clear mstatus.MXR
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled---------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# -------------------Load Test Prolog-------------------------
|
||||
|
||||
TEST_PROLOG(check_load, CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
check_load: # test the load access
|
||||
|
||||
lw t1,0(a1)
|
||||
TEST_STATUS # checks the status of the test
|
||||
nop
|
||||
|
||||
#ifdef smode
|
||||
SMODE_ECALL # SMODE ecall
|
||||
#else
|
||||
UMODE_ECALL # UMODE ecall
|
||||
#endif
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
csrr t5,mepc # read the value of mepc
|
||||
|
||||
bne t3,t5, test_fail # check the value of mepc with it's expected value
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # Exit logic
|
||||
|
||||
.data
|
||||
rvtest_check:
|
||||
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0xcafecafe
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
154
verif/tests/custom/sv32/vm_mxr_clear_level_1.S
Normal file
154
verif/tests/custom/sv32/vm_mxr_clear_level_1.S
Normal file
|
|
@ -0,0 +1,154 @@
|
|||
#=======================================================================
|
||||
# Load Access of Level1 PTE in User and Supervisor mode when
|
||||
# mstatus.MXR is unset
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE has only execute permission (pte.x = 1) and s/mstatus.MXR=0,
|
||||
# then read access on that PTE should raise load page fault exception.
|
||||
#
|
||||
# - Set pte.r=0 & pte.w=0 & pte.x=1 & s/mstatus.MXR=0 and test the
|
||||
# read acces.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the mem
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
PTE_LEVEL1:
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load test---------------------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_W | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_W | PTE_R | PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
li a1, MSTATUS_MXR
|
||||
csrc mstatus, a1 # Clear mstatus.MXR
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled---------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# -------------------Load Test Prolog-------------------------
|
||||
|
||||
TEST_PROLOG(check_load, CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
check_load: # test the load access
|
||||
|
||||
lw t1,0(a1)
|
||||
TEST_STATUS # checks the status of the test
|
||||
nop
|
||||
|
||||
#ifdef smode
|
||||
SMODE_ECALL # SMODE ecall
|
||||
#else
|
||||
UMODE_ECALL # UMODE ecall
|
||||
#endif
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
csrr t5,mepc # read the value of mepc
|
||||
|
||||
bne t3,t5, test_fail # check the value of mepc with it's expected value
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # Exit logic
|
||||
|
||||
.data
|
||||
.align 24
|
||||
rvtest_check:
|
||||
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0xcafecafe
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
154
verif/tests/custom/sv32/vm_mxr_set_level_0.S
Normal file
154
verif/tests/custom/sv32/vm_mxr_set_level_0.S
Normal file
|
|
@ -0,0 +1,154 @@
|
|||
#=======================================================================
|
||||
# Read Access of PTE at level0 in User and Supervisor mode when
|
||||
# mstatus.mxr = 1 and only PTE.X = 1
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
# If PTE has only execute permission (pte.x = 1) and s/mstatus.MXR=1,
|
||||
# then read access on that PTE should be successful without having
|
||||
# explicit read permission (pte.r=0). This test
|
||||
# covers the following scenarios in both supervisor and user privilege
|
||||
# modes for level0 PTE.
|
||||
# Level 0
|
||||
# - mstatus.mxr = 1 and only PTE.X = 1 with the READ access
|
||||
# in the supervisor and user mode
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL1 PTE Setup to point to LEVEL0 PTE----------------
|
||||
la a1,pgtb_l0 # loads the address of label pbtb_l0
|
||||
mv a0, a1 # generrates the VA for label pbtb_l0
|
||||
ori a2, x0, ( PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------LEVEL 0 PTE Setup for load and store test--------------
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
sw a1, 0(a1) # store the random number
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits -- only X permission
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode-----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
li t4, MSTATUS_MXR
|
||||
csrs mstatus, t4 # MXR bit set on mstatus
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
|
||||
#ifdef smode
|
||||
SMODE_ECALL # SMODE ecall
|
||||
#else
|
||||
UMODE_ECALL # UMODE ecall
|
||||
#endif
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
j exit # Jump to exit
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
.align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
149
verif/tests/custom/sv32/vm_mxr_set_level_1.S
Normal file
149
verif/tests/custom/sv32/vm_mxr_set_level_1.S
Normal file
|
|
@ -0,0 +1,149 @@
|
|||
#=======================================================================
|
||||
# Read Access of PTE at level1 in User and Supervisor mode when
|
||||
# mstatus.mxr = 1 and only PTE.X = 1
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
# If PTE has only execute permission (pte.x = 1) and s/mstatus.MXR=1,
|
||||
# then read access on that PTE should be successful without having
|
||||
# explicit read permission (pte.r=0). This test
|
||||
# covers the following scenarios in both supervisor and user privilege
|
||||
# modes for level0 PTE.
|
||||
# Level 0
|
||||
# - mstatus.mxr = 1 and only PTE.X = 1 with the READ access
|
||||
# in the supervisor and user mode
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test------------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
sw a1, 0(a1) # store the random number
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits -- only X permission
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
li t4, MSTATUS_MXR
|
||||
csrs mstatus, t4 # MXR bit set on mstatus
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
la a1, rvtest_data # loads the address of label rvtest_data # stores the value of t1
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
|
||||
#ifdef smode
|
||||
SMODE_ECALL # SMODE ecall
|
||||
#else
|
||||
UMODE_ECALL # UMODE ecall
|
||||
#endif
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
j exit # Jump to exit
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
.align 24 # Superpage align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
199
verif/tests/custom/sv32/vm_nonleaf_pte.S
Normal file
199
verif/tests/custom/sv32/vm_nonleaf_pte.S
Normal file
|
|
@ -0,0 +1,199 @@
|
|||
#=======================================================================
|
||||
# RWX Access of Level0 PTE in User and Supervisor mode when
|
||||
# Non-Leaf PTE persmissions at Level 0
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
# If PTE at level0 has non-leaf RWX permissions (pte.x=0 & pte.r=0 & pte.w=0),
|
||||
# then accessing it would raise page fault exception of the corresponding
|
||||
# access type. This test
|
||||
# covers the following scenarios in both supervisor and user privilege
|
||||
# modes for level0 PTE.
|
||||
# Level 0
|
||||
# Set PTE.R = 0 and PTE.W = 0 and PTE.X = 0 test the RWX access in SMode
|
||||
# Set PTE.R = 0 and PTE.W = 0 and PTE.X = 0 test the RWX access in UMode
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL1 PTE Setup to point to LEVEL0 PTE----------------
|
||||
la a1,pgtb_l0 # loads the address of label pgbt_l0
|
||||
mv a0, a1 # generrates the VA for label pgtb_l0
|
||||
ori a2, x0, ( PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------LEVEL 0 PTE Setup for load and store test--------------
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_V | PTE_A | SET_PTE_U | PTE_D ) # sets the permission bits -- No RWX permission
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode-----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------Load test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_load,CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
TEST_STATUS # checks the status of the test
|
||||
# ----------------Store test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_store,CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
sw t1,0(a1) # test the store access
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
#ifdef smode
|
||||
SMODE_ECALL # changes mode M to S and set the MEPC
|
||||
#else
|
||||
UMODE_ECALL # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
# ----------------------Execute test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_execute,CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
# -------------LEVEL 0 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_execute # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_V | PTE_A | SET_PTE_U | PTE_D ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,check_execute # loads the address of check_execute
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
|
||||
|
||||
check_execute:
|
||||
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
j exit # Jump to exit
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
.align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
238
verif/tests/custom/sv32/vm_pmp_check_level_0.S
Normal file
238
verif/tests/custom/sv32/vm_pmp_check_level_0.S
Normal file
|
|
@ -0,0 +1,238 @@
|
|||
#=======================================================================
|
||||
# PMP permissions on Physical Address in User and supervisor mode
|
||||
# at level 0 PTE
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE has valid and non-reserved RWX permissions, but the translated
|
||||
# Physical address (pte.ppn of leaf PTE + offset) does not have (r,w,x)
|
||||
# PMP permissions, then accessing the translated Physical address would
|
||||
# raise access fault exception.
|
||||
#
|
||||
# - Remove read PMP permission of translated Physical Address in pmpcfg
|
||||
# and test the read acces.
|
||||
# - Remvoe write PMP permission of translated Physical Address in pmpcfg
|
||||
# and test the write access.
|
||||
# - Remove execute PMP permission of translated Physical Address in
|
||||
# pmpcfg and test the execute access.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#define NAPOT_RANGE_4KB 0x1FF # Set 4kB range with NAPOT
|
||||
#define NAPOT_RANGE_32B 0x3 # Set 32B range with NAPOT
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
|
||||
# -------------------------------- PMP Configurations --------------------------------
|
||||
|
||||
la t2, vm_en # Loads the address of vm_en
|
||||
srli t2, t2, PMP_SHIFT # Right shift the PA by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_4KB # Selects the range of 4kB
|
||||
csrw pmpaddr0, t2 # Region 1 for the pmp permissions
|
||||
sfence.vma
|
||||
|
||||
la t2, pgtb_l1 # loads the base address of LEVEL1 4kbpage table
|
||||
srli t2, t2, PMP_SHIFT # Right shift the address of LEVEL 1 page table by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_4KB # Selects the range of 4kB
|
||||
csrw pmpaddr1, t2 # Region 2 for the pmp permission
|
||||
sfence.vma
|
||||
|
||||
la t2, pgtb_l0 # loads the base address of LEVEL0 4kbpage table
|
||||
srli t2, t2, PMP_SHIFT # Right shift the address of LEVEL 0 page table by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_4KB # Selects the range of 4kB
|
||||
csrw pmpaddr4, t2 # Region 3 for the pmp permission
|
||||
sfence.vma
|
||||
|
||||
la t2, rvtest_check # loads the base address of rvtest_data label
|
||||
srli t2, t2, PMP_SHIFT # Right shift the address of rvtest_data label by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_32B # Selects the range of 32B
|
||||
csrw pmpaddr2, t2 # Region 4 for the pmp permission
|
||||
sfence.vma
|
||||
|
||||
la t2, rvtest_data # loads the base address of rvtest_data label
|
||||
srli t2, t2, PMP_SHIFT # Right shift the address of rvtest_data label by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_32B # Selects the range of 32B
|
||||
csrw pmpaddr3, t2 # Region 5 for the pmp permission
|
||||
sfence.vma
|
||||
|
||||
# Region 1, 2, 3, 4: NAPOT with RWX PMP Permissions
|
||||
li t2, ((PMP_NAPOT | PMP_X) << 24) | ((PMP_NAPOT | PMP_X | PMP_W | PMP_R) << 16) | ((PMP_NAPOT | PMP_X | PMP_W | PMP_R) << 8) | (PMP_NAPOT | PMP_X | PMP_W | PMP_R)
|
||||
csrw pmpcfg0, t2 # Write PMP Regions Configration
|
||||
li t2, (PMP_NAPOT | PMP_X | PMP_W | PMP_R) # Region5: NAPOT with RWX PMP Permissions
|
||||
csrw pmpcfg1, t2 # Write PMP Regions Configration
|
||||
sfence.vma
|
||||
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
PTE_LEVEL0:
|
||||
|
||||
# ----------------LEVEL 0 PTE Setup for load and store test---------------------
|
||||
|
||||
la a1,pgtb_l0 # loads the address of label pgtb_l0
|
||||
la a0, _start # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_W | PTE_R | PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled---------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# -------------------Load Test Prolog------------------------
|
||||
|
||||
TEST_PROLOG(check_load, CAUSE_LOAD_ACCESS) # load the addr and expected cause
|
||||
|
||||
check_load: # test the load access
|
||||
|
||||
lw t1,0(a1)
|
||||
TEST_STATUS # checks the status of the test
|
||||
nop
|
||||
|
||||
# -------------------Store Test Prolog------------------------
|
||||
|
||||
TEST_PROLOG(check_store, CAUSE_STORE_ACCESS) # load the addr and expected cause
|
||||
|
||||
check_store: # test the store access
|
||||
sw t1,0(a1)
|
||||
nop
|
||||
TEST_STATUS # checks the status of the test
|
||||
#ifdef smode
|
||||
SMODE_ECALL # SMODE ecall
|
||||
#else
|
||||
UMODE_ECALL # UMODE ecall
|
||||
#endif
|
||||
|
||||
# -------------------Execute Test Prolog------------------------
|
||||
|
||||
TEST_PROLOG(check_execute, CAUSE_FETCH_ACCESS) # load the addr and expected cause
|
||||
|
||||
li t2, (PMP_NAPOT | PMP_X | PMP_W | PMP_R)
|
||||
csrc pmpcfg0, t2 # Clear PMP Region 1 Configration
|
||||
li t2, (PMP_NAPOT | PMP_W | PMP_R)
|
||||
csrs pmpcfg0, t2 # Set PMP Region 1 Configration
|
||||
sfence.vma
|
||||
|
||||
la a1, check_execute
|
||||
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
|
||||
check_execute: # test the execute access
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
csrr t5,mepc # read the value of mepc
|
||||
|
||||
bne t3,t5, test_fail # check the value of mepc with it's expected value
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_ACCESS # load the value of fetch access fault
|
||||
beq t0, t5, continue_in_m_mode # if fetch access fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # Exit logic
|
||||
|
||||
.data
|
||||
rvtest_check:
|
||||
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
227
verif/tests/custom/sv32/vm_pmp_check_level_1.S
Normal file
227
verif/tests/custom/sv32/vm_pmp_check_level_1.S
Normal file
|
|
@ -0,0 +1,227 @@
|
|||
#=======================================================================
|
||||
# PMP permissions on Physical Address in User and supervisor mode
|
||||
# at level 1 PTE
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE has valid and non-reserved RWX permissions, but the translated
|
||||
# Physical address (pte.ppn of leaf PTE + offset) does not have (r,w,x)
|
||||
# PMP permissions, then accessing the translated Physical address would
|
||||
# raise access fault exception.
|
||||
#
|
||||
# - Remove read PMP permission of translated Physical Address in pmpcfg
|
||||
# and test the read acces.
|
||||
# - Remvoe write PMP permission of translated Physical Address in pmpcfg
|
||||
# and test the write access.
|
||||
# - Remove execute PMP permission of translated Physical Address in
|
||||
# pmpcfg and test the execute access.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
#define NAPOT_RANGE_4KB 0x1FF # Set 4kB range with NAPOT
|
||||
#define NAPOT_RANGE_32B 0x3 # Set 32B range with NAPOT
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
|
||||
# -------------------------------- PMP Configurations --------------------------------
|
||||
|
||||
la t2, vm_en # Loads the address of vm_en
|
||||
srli t2, t2, PMP_SHIFT # Right shift the PA by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_4KB # Selects the range of 4kB
|
||||
csrw pmpaddr0, t2 # Region 1 for the pmp permissions
|
||||
sfence.vma
|
||||
|
||||
la t2, pgtb_l1 # loads the base address of level1 4kbpage table
|
||||
srli t2, t2, PMP_SHIFT # Right shift the address of level 1 page table by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_4KB # Selects the range of 8kB
|
||||
csrw pmpaddr1, t2 # Region 2 for the pmp permission
|
||||
sfence.vma
|
||||
|
||||
la t2, rvtest_check # loads the base address of rvtest_check label
|
||||
srli t2, t2, PMP_SHIFT # Right shift the address of rvtest_data label by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_32B # Selects the range of 32B
|
||||
csrw pmpaddr2, t2 # Region 3 for the pmp permission
|
||||
sfence.vma
|
||||
|
||||
la t2, rvtest_data # loads the base address of rvtest_data label
|
||||
srli t2, t2, PMP_SHIFT # Right shift the address of rvtest_data label by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_32B # Selects the range of 32B
|
||||
csrw pmpaddr3, t2 # Region 4 for the pmp permission
|
||||
sfence.vma
|
||||
|
||||
# Region 1, 2, 3: NAPOT with RWX PMP Permissions
|
||||
# Region 4: : NAPOT with X PMP Permission only
|
||||
li t2, ((PMP_NAPOT | PMP_X) << 24) | ((PMP_NAPOT | PMP_X | PMP_W | PMP_R) << 16) | ((PMP_NAPOT | PMP_X | PMP_W | PMP_R) << 8) | (PMP_NAPOT | PMP_X | PMP_W | PMP_R)
|
||||
csrw pmpcfg0, t2 # Write PMP Regions Configration
|
||||
sfence.vma
|
||||
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
PTE_LEVEL1:
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test---------------------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_W | PTE_R | PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled---------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# -------------------Load Test Prolog------------------------
|
||||
|
||||
TEST_PROLOG(check_load, CAUSE_LOAD_ACCESS) # load the addr and expected cause
|
||||
|
||||
check_load: # test the load access
|
||||
|
||||
lw t1,0(a1)
|
||||
TEST_STATUS # checks the status of the test
|
||||
nop
|
||||
|
||||
# -------------------Store Test Prolog------------------------
|
||||
|
||||
TEST_PROLOG(check_store, CAUSE_STORE_ACCESS) # load the addr and expected cause
|
||||
|
||||
check_store: # test the store access
|
||||
sw t1,0(a1)
|
||||
nop
|
||||
TEST_STATUS # checks the status of the test
|
||||
#ifdef smode
|
||||
SMODE_ECALL # SMODE ecall
|
||||
#else
|
||||
UMODE_ECALL # UMODE ecall
|
||||
#endif
|
||||
|
||||
# -------------------Execute Test Prolog------------------------
|
||||
|
||||
TEST_PROLOG(check_execute, CAUSE_FETCH_ACCESS) # load the addr and expected cause
|
||||
|
||||
li t2, (PMP_NAPOT | PMP_X | PMP_W | PMP_R)
|
||||
csrc pmpcfg0, t2 # Clear PMP Region 1 Configration
|
||||
li t2, (PMP_NAPOT | PMP_W | PMP_R)
|
||||
csrs pmpcfg0, t2 # Set PMP Region 1 Configration
|
||||
sfence.vma
|
||||
|
||||
la a1, check_execute
|
||||
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
|
||||
check_execute: # test the execute access
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
csrr t5,mepc # read the value of mepc
|
||||
|
||||
bne t3,t5, test_fail # check the value of mepc with it's expected value
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_ACCESS # load the value of fetch access fault
|
||||
beq t0, t5, continue_in_m_mode # if fetch access fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # Exit logic
|
||||
|
||||
.data
|
||||
.align 24
|
||||
rvtest_check:
|
||||
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
265
verif/tests/custom/sv32/vm_pte_pmp_check_level_0.S
Normal file
265
verif/tests/custom/sv32/vm_pte_pmp_check_level_0.S
Normal file
|
|
@ -0,0 +1,265 @@
|
|||
#=======================================================================
|
||||
# RWX Access of PTE with no PMP of PTE Permissions Test on Level 0 PTE
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE does not have (r,w,x) PMP permissions, then accessing it would
|
||||
# raise access fault exception of the corresponding access type.
|
||||
# When satp.mode=sv32 and PMP have no (r,w,x) PMP permissions, then this test
|
||||
# covers the following scenarios in both supervisor and user privilege
|
||||
# modes for level 0 PTE.
|
||||
#
|
||||
# - Set PMP.R = 0 for PTE and test the read access.
|
||||
# - Set PMP.X = 0 for PTE and test the execute access.
|
||||
# - Set PMP.W = 0 for PTE the write access.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#define NAPOT_RANGE_4KB 0x1FF # Set 4kB range with NAPOT
|
||||
#define NAPOT_RANGE_32B 0x3 # Set 32B range with NAPOT
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
|
||||
# -------------------------------- PMP Configurations --------------------------------
|
||||
|
||||
la t2, vm_en # Loads the address of vm_en
|
||||
srli t2, t2, PMP_SHIFT # Right shift the PA by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_4KB # Selects the range of 4kB
|
||||
csrw pmpaddr0, t2 # Region 1 for the pmp permissions
|
||||
sfence.vma
|
||||
|
||||
la t2, pgtb_l1 # loads the base address of level1 4kbpage table
|
||||
la t5, vm_en
|
||||
srli t5, t5, 20
|
||||
add t2, t2, t5
|
||||
srli t2, t2, PMP_SHIFT # Right shift the address of level 1 page table by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_32B # Selects the range of 8kB
|
||||
csrw pmpaddr1, t2 # Region 2 for the pmp permission
|
||||
sfence.vma
|
||||
|
||||
la t2, rvtest_check # loads the base address of rvtest_check label
|
||||
srli t2, t2, PMP_SHIFT # Right shift the address of rvtest_data label by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_32B # Selects the range of 32B
|
||||
csrw pmpaddr2, t2 # Region 3 for the pmp permission
|
||||
sfence.vma
|
||||
|
||||
la t2, pgtb_l0 # loads the base address of pgtb_l0
|
||||
srli t2, t2, PMP_SHIFT # Right shift the address of pgtb_l0 by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_32B # Selects the range of 32B
|
||||
csrw pmpaddr3, t2 # Region 4 for the pmp permission
|
||||
sfence.vma
|
||||
|
||||
la t2, tohost # loads the base address of tohost label
|
||||
srli t2, t2, PMP_SHIFT # Right shift the address of tohost label by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_32B # Selects the range of 32B
|
||||
csrw pmpaddr4, t2 # Region 5 for the pmp permission
|
||||
sfence.vma
|
||||
|
||||
# Region 1, 2, 3: NAPOT with RWX PMP Permissions
|
||||
# Region 4: : NAPOT with no PMP Permission only
|
||||
li t2, ((PMP_NAPOT) << 24) | ((PMP_NAPOT | PMP_X | PMP_W | PMP_R) << 16) | ((PMP_NAPOT | PMP_X | PMP_W | PMP_R) << 8) | (PMP_NAPOT | PMP_X | PMP_W | PMP_R)
|
||||
csrw pmpcfg0, t2 # Write PMP Regions Configration
|
||||
sfence.vma
|
||||
li t2, (PMP_NAPOT | PMP_X | PMP_W | PMP_R)
|
||||
csrw pmpcfg1, t2 # Write PMP Regions Configration
|
||||
sfence.vma
|
||||
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test---------------------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_W | PTE_R | PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------LEVEL 0 PTE Setup for load and store test---------------------
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level1
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled---------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------Load test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_load, CAUSE_LOAD_ACCESS) # load the addr and expected cause
|
||||
la a1, pgtb_l0 # load base address of PGTB Level 1 for load access test
|
||||
|
||||
check_load: # test the load access
|
||||
|
||||
lw t1,0(a1)
|
||||
TEST_STATUS
|
||||
|
||||
# ----------------Store test prolog--------------------------------------
|
||||
|
||||
|
||||
TEST_PROLOG(check_store, CAUSE_STORE_ACCESS) # load the addr and expected cause
|
||||
la a1, pgtb_l0 # load base address of PGBTB Level 1 for store access test
|
||||
|
||||
check_store: # test the store access
|
||||
sw t1,0(a1)
|
||||
TEST_STATUS
|
||||
|
||||
#ifdef smode
|
||||
SMODE_ECALL # SMODE ecall
|
||||
#else
|
||||
UMODE_ECALL # UMODE ecall
|
||||
#endif
|
||||
|
||||
# ----------------------Setting PMP Permissions for Region 2------------------------------
|
||||
la a1,pgtb_l0 # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la t2, pgtb_l0 # loads the base address of level1 4kbpage table
|
||||
srli t2, t2, PMP_SHIFT # Right shift the address of level 1 page table by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_4KB # Selects the range of 4kB
|
||||
csrw pmpaddr3, t2 # Region 2 for the pmp permission
|
||||
sfence.vma
|
||||
|
||||
li t2, ((PMP_NAPOT | PMP_X | PMP_W | PMP_R) << 24)
|
||||
csrc pmpcfg0, t2 # Clear PMP Regions Configration
|
||||
li t2, ((PMP_NAPOT | PMP_W | PMP_R) << 24)
|
||||
csrs pmpcfg0, t2 # Write PMP Regions Configration
|
||||
sfence.vma
|
||||
|
||||
la a1, check_execute
|
||||
# ----------------change the mode---------------------
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
|
||||
check_execute: # test the execute access
|
||||
li t1, 0x45
|
||||
#ifdef smode
|
||||
SMODE_ECALL # SMODE ecall
|
||||
#else
|
||||
UMODE_ECALL # UMODE ecall
|
||||
#endif
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
j exit # Jump to exit
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to test_fail if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to test_fail if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # Exit logic
|
||||
|
||||
.data
|
||||
.align 24
|
||||
rvtest_check:
|
||||
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
251
verif/tests/custom/sv32/vm_pte_pmp_check_level_1.S
Normal file
251
verif/tests/custom/sv32/vm_pte_pmp_check_level_1.S
Normal file
|
|
@ -0,0 +1,251 @@
|
|||
#=======================================================================
|
||||
# RWX Access of PTE with no PMP of PTE Permissions Test on Level 1 PTE
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE does not have (r,w,x) PMP permissions, then accessing it would
|
||||
# raise access fault exception of the corresponding access type.
|
||||
# When satp.mode=sv32 and PMP have no (r,w,x) PMP permissions, then this test
|
||||
# covers the following scenarios in both supervisor and user privilege
|
||||
# modes for level 1 PTE.
|
||||
#
|
||||
# - Set PMP.R = 0 for PTE and test the read access.
|
||||
# - Set PMP.X = 0 for PTE and test the execute access.
|
||||
# - Set PMP.W = 0 for PTE the write access.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#define NAPOT_RANGE_4KB 0x1FF # Set 4kB range with NAPOT
|
||||
#define NAPOT_RANGE_32B 0x3 # Set 32B range with NAPOT
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
|
||||
# -------------------------------- PMP Configurations --------------------------------
|
||||
|
||||
la t2, vm_en # Loads the address of vm_en
|
||||
srli t2, t2, PMP_SHIFT # Right shift the PA by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_4KB # Selects the range of 4kB
|
||||
csrw pmpaddr0, t2 # Region 1 for the pmp permissions
|
||||
sfence.vma
|
||||
|
||||
la t2, pgtb_l1 # loads the base address of level1 4kbpage table
|
||||
la t5, vm_en
|
||||
srli t5, t5, 20
|
||||
add t2, t2, t5
|
||||
srli t2, t2, PMP_SHIFT # Right shift the address of level 1 page table by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_32B # Selects the range of 32kB
|
||||
csrw pmpaddr1, t2 # Region 2 for the pmp permission
|
||||
sfence.vma
|
||||
|
||||
la t2, rvtest_check # loads the base address of rvtest_check label
|
||||
srli t2, t2, PMP_SHIFT # Right shift the address of rvtest_data label by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_32B # Selects the range of 32B
|
||||
csrw pmpaddr2, t2 # Region 3 for the pmp permission
|
||||
sfence.vma
|
||||
|
||||
la t2, pgtb_l1 # loads the base address of pgtb_l1
|
||||
srli t2, t2, PMP_SHIFT # Right shift the address of pgtb_l1 by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_32B # Selects the range of 32B
|
||||
csrw pmpaddr3, t2 # Region 4 for the pmp permission
|
||||
sfence.vma
|
||||
|
||||
la t2, tohost # loads the base address of tohost label
|
||||
srli t2, t2, PMP_SHIFT # Right shift the address of tohost label by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_32B # Selects the range of 32B
|
||||
csrw pmpaddr4, t2 # Region 5 for the pmp permission
|
||||
sfence.vma
|
||||
|
||||
# Region 1, 2, 3: NAPOT with RWX PMP Permissions
|
||||
# Region 4: : NAPOT with no PMP Permission only
|
||||
li t2, ((PMP_NAPOT) << 24) | ((PMP_NAPOT | PMP_X | PMP_W | PMP_R) << 16) | ((PMP_NAPOT | PMP_X | PMP_W | PMP_R) << 8) | (PMP_NAPOT | PMP_X | PMP_W | PMP_R)
|
||||
csrw pmpcfg0, t2 # Write PMP Regions Configration
|
||||
sfence.vma
|
||||
li t2, (PMP_NAPOT | PMP_X | PMP_W | PMP_R)
|
||||
csrw pmpcfg1, t2 # Write PMP Regions Configration
|
||||
sfence.vma
|
||||
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test---------------------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_W | PTE_R | PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled---------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------Load test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_load, CAUSE_LOAD_ACCESS) # load the addr and expected cause
|
||||
la a1, pgtb_l1 # load base address of PGTB Level 1 for load access test
|
||||
|
||||
check_load: # test the load access
|
||||
|
||||
lw t1,0(a1)
|
||||
TEST_STATUS
|
||||
|
||||
# ----------------Store test prolog--------------------------------------
|
||||
|
||||
|
||||
TEST_PROLOG(check_store, CAUSE_STORE_ACCESS) # load the addr and expected cause
|
||||
la a1, pgtb_l1 # load base address of PGBTB Level 1 for store access test
|
||||
|
||||
check_store: # test the store access
|
||||
sw t1,0(a1)
|
||||
TEST_STATUS
|
||||
|
||||
#ifdef smode
|
||||
SMODE_ECALL # SMODE ecall
|
||||
#else
|
||||
UMODE_ECALL # UMODE ecall
|
||||
#endif
|
||||
|
||||
# ----------------------Setting PMP Permissions for Region 2------------------------------
|
||||
|
||||
|
||||
la t2, pgtb_l1 # loads the base address of level1 4kbpage table
|
||||
srli t2, t2, PMP_SHIFT # Right shift the address of level 1 page table by PMP_Shift(2)
|
||||
ori t2, t2, NAPOT_RANGE_4KB # Selects the range of 4kB
|
||||
csrw pmpaddr1, t2 # Region 2 for the pmp permission
|
||||
sfence.vma
|
||||
|
||||
li t2, ((PMP_NAPOT | PMP_X | PMP_W | PMP_R) << 8)
|
||||
csrc pmpcfg0, t2 # Clear PMP Regions Configration
|
||||
li t2, ((PMP_NAPOT | PMP_W | PMP_R) << 8)
|
||||
csrs pmpcfg0, t2 # Write PMP Regions Configration
|
||||
sfence.vma
|
||||
|
||||
la a1, check_execute
|
||||
# ----------------change the mode---------------------
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
|
||||
check_execute: # test the execute access
|
||||
li t1, 0x45
|
||||
#ifdef smode
|
||||
SMODE_ECALL # SMODE ecall
|
||||
#else
|
||||
UMODE_ECALL # UMODE ecall
|
||||
#endif
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
j exit # Jump to exit
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to test_fail if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to test_fail if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # Exit logic
|
||||
|
||||
.data
|
||||
.align 24
|
||||
rvtest_check:
|
||||
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
146
verif/tests/custom/sv32/vm_pte_u_bit_set_01.S
Normal file
146
verif/tests/custom/sv32/vm_pte_u_bit_set_01.S
Normal file
|
|
@ -0,0 +1,146 @@
|
|||
#=======================================================================
|
||||
# U Bit Permission set for Level 1 PTE
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE belongs to user mode i.e. its U permission bit is set (pte.u = 1),
|
||||
# then accessing that PTE in user mode should be successful if the
|
||||
# (r,w,x) permission of PTE is granted.
|
||||
# When satp.mode=sv32 and PTE has (r,w,x) PMP permissions, this test
|
||||
# covers the following scenarios in user privilege modes for level 1 PTE.
|
||||
#
|
||||
# Set PTE.U = 1 & PTE.R = 1 and test the read access.
|
||||
# Set PTE.U = 1 & PTE.W = 1 and test the write access.
|
||||
# Set PTE.U = 1 & PTE.X = 1 and test the execute access.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test------------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_W | PTE_R | PTE_V | PTE_U ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_W | PTE_R | PTE_V | PTE_U ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
la a1, rvtest_data # load addr of rvtest_data
|
||||
|
||||
check_store:
|
||||
|
||||
sw t1,0(a1) # test the store access
|
||||
nop
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
nop
|
||||
|
||||
check_execute:
|
||||
|
||||
li t1, 0x45 # page fault should raise
|
||||
UMODE_ECALL
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
.align 24 # Superpage align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
177
verif/tests/custom/sv32/vm_pte_u_bit_set_02.S
Normal file
177
verif/tests/custom/sv32/vm_pte_u_bit_set_02.S
Normal file
|
|
@ -0,0 +1,177 @@
|
|||
#=======================================================================
|
||||
# U Bit Permission set for Level 1 PTE
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE belongs to user mode i.e. its U permission bit is set (pte.u = 1),
|
||||
# then accessing that PTE in user mode should raise page fault if the
|
||||
# (r,w,x) permission of PTE is not granted.
|
||||
# When satp.mode=sv32 and PTE does not have (r,w,x) PMP permissions, this test
|
||||
# covers the following scenarios in user privilege modes for level 1 PTE.
|
||||
#
|
||||
# Set PTE.U = 1 & PTE.R = 0 and test the read access.
|
||||
# Set PTE.U = 1 & PTE.W = 0 and test the write access.
|
||||
# Set PTE.U = 1 & PTE.X = 0 and test the execute access.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test------------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------Load test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_load,CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
TEST_STATUS
|
||||
|
||||
# ----------------Store test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_store,CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
sw t1,0(a1) # test the store access
|
||||
TEST_STATUS
|
||||
UMODE_ECALL # ecall to go to m mode
|
||||
|
||||
# ----------------------Execute test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_execute,CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
# -------------LEVEL 1 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_execute # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,check_execute # loads the address of check_execute
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
|
||||
|
||||
|
||||
check_execute:
|
||||
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
j exit # Jump to exit
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # Exit logic
|
||||
|
||||
.data
|
||||
.align 24 # Superpage align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
147
verif/tests/custom/sv32/vm_pte_u_bit_set_03.S
Normal file
147
verif/tests/custom/sv32/vm_pte_u_bit_set_03.S
Normal file
|
|
@ -0,0 +1,147 @@
|
|||
#=======================================================================
|
||||
# U Bit Permission set for Level 0 PTE
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE belongs to user mode i.e. its U permission bit is set (pte.u = 1),
|
||||
# then accessing that PTE in user mode should be successful if the
|
||||
# (r,w,x) permission of PTE is granted.
|
||||
# When satp.mode=sv32 and PTE has (r,w,x) PMP permissions, this test
|
||||
# covers the following scenarios in user privilege modes for level 0 PTE.
|
||||
#
|
||||
# Set PTE.U = 1 & PTE.R = 1 and test the read access.
|
||||
# Set PTE.U = 1 & PTE.W = 1 and test the write access.
|
||||
# Set PTE.U = 1 & PTE.X = 1 and test the execute access.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL1 PTE Setup to point to LEVEL0 PTE----------------
|
||||
la a1,pgtb_l0 # loads the address of pgtb_l0
|
||||
mv a0, a1 # generrates the VA for pgtb_l0
|
||||
ori a2, x0, ( PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------LEVEL 0 PTE Setup for load and store test--------------
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_V | PTE_U | PTE_R | PTE_W) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode-----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
sw t1,0(a1) # test the store access
|
||||
nop
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
|
||||
check_execute:
|
||||
|
||||
li t1, 0x45 # page fault should raise
|
||||
ecall
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
181
verif/tests/custom/sv32/vm_pte_u_bit_set_04.S
Normal file
181
verif/tests/custom/sv32/vm_pte_u_bit_set_04.S
Normal file
|
|
@ -0,0 +1,181 @@
|
|||
#=======================================================================
|
||||
# U Bit Permission set for Level 0 PTE
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE belongs to user mode i.e. its U permission bit is set (pte.u = 1),
|
||||
# then accessing that PTE in user mode should raise page fault if the
|
||||
# (r,w,x) permission of PTE is not granted.
|
||||
# When satp.mode=sv32 and PTE does not have (r,w,x) PMP permissions, this test
|
||||
# covers the following scenarios in user privilege modes for level 0 PTE.
|
||||
#
|
||||
# Set PTE.U = 1 & PTE.R = 0 and test the read access.
|
||||
# Set PTE.U = 1 & PTE.W = 0 and test the write access.
|
||||
# Set PTE.U = 1 & PTE.X = 0 and test the execute access.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL1 PTE Setup to point to LEVEL0 PTE----------------
|
||||
la a1,pgtb_l0 # loads the address of label pgtb_l0
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
# ----------------LEVEL0 PTE Setup to point to LEVEL0 PTE----------------
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l0, LEVEL0 ) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode-----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------Load test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_load,CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
TEST_STATUS
|
||||
|
||||
# ----------------Store test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_store,CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
sw t1,0(a1) # test the store access
|
||||
TEST_STATUS
|
||||
UMODE_ECALL # ecall to go to m mode
|
||||
|
||||
# ----------------------Execute test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_execute,CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
# -------------LEVEL 1 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_execute # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_V | PTE_U ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,check_execute # loads the address of check_execute
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
|
||||
check_execute:
|
||||
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
j exit # Jump to exit
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret # return
|
||||
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # Exit logic
|
||||
|
||||
.data
|
||||
.align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
180
verif/tests/custom/sv32/vm_pte_u_bit_unset_level_0.S
Normal file
180
verif/tests/custom/sv32/vm_pte_u_bit_unset_level_0.S
Normal file
|
|
@ -0,0 +1,180 @@
|
|||
#=======================================================================
|
||||
# U Bit Permission Unset for Level 0 PTE
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE does not have the U bit (pte.U=0) permission, accessing it in U
|
||||
# mode would raise a page fault exception of the corresponding access type.
|
||||
# When satp.mode=sv32 and PTE has (r,w,x) PMP permissions, this test
|
||||
# covers the following scenarios in user privilege modes for level 0 PTE.
|
||||
#
|
||||
# Set PTE.U = 0 and test the read access.
|
||||
# Set PTE.U = 0 and test the write access.
|
||||
# Set PTE.U = 0 and test the execute access.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL1 PTE Setup to point to LEVEL0 PTE----------------
|
||||
la a1,pgtb_l0 # loads the address of pgtb_l0
|
||||
mv a0, a1 # generrates the VA for label pgtb_l0
|
||||
ori a2, x0, ( PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------LEVEL 0 PTE Setup for load and store test--------------
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_V | PTE_W | PTE_R ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode-----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------Load test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_load,CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
TEST_STATUS # checks the status of the test
|
||||
# ----------------Store test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_store,CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
sw t1,0(a1) # test the store access
|
||||
TEST_STATUS # checks the status of the test
|
||||
UMODE_ECALL # ecall to go to m mode
|
||||
|
||||
|
||||
# ----------------------Execute test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_execute,CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
# -------------LEVEL 1 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_execute # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_V | PTE_X ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,check_execute # loads the address of check_execute
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
|
||||
|
||||
check_execute:
|
||||
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # Exit logic
|
||||
|
||||
.data
|
||||
.align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
176
verif/tests/custom/sv32/vm_pte_u_bit_unset_level_1.S
Normal file
176
verif/tests/custom/sv32/vm_pte_u_bit_unset_level_1.S
Normal file
|
|
@ -0,0 +1,176 @@
|
|||
#=======================================================================
|
||||
# U Bit Permission Unset for Level1 PTE
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE does not have the U bit (pte.U=0) permission, accessing it in U
|
||||
# mode would raise a page fault exception of the corresponding access type.
|
||||
# When satp.mode=sv32 and PTE has (r,w,x) PMP permissions, this test
|
||||
# covers the following scenarios in user privilege modes for level 1 PTE.
|
||||
#
|
||||
# Set PTE.U = 0 and test the read access.
|
||||
# Set PTE.U = 0 and test the write access.
|
||||
# Set PTE.U = 0 and test the execute access.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test------------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------Load test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_load,CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
TEST_STATUS # checks the status of the test
|
||||
# ----------------Store test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_store,CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
sw t1,0(a1) # test the store access
|
||||
TEST_STATUS # checks the status of the test
|
||||
UMODE_ECALL # ecall to go to m mode
|
||||
|
||||
# ----------------------Execute test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_execute,CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
# -------------LEVEL 1 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_execute # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_V | PTE_X ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,check_execute # loads the address of check_execute
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
|
||||
|
||||
|
||||
check_execute:
|
||||
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # Exit logic
|
||||
|
||||
.data
|
||||
.align 24 # Superpage align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
148
verif/tests/custom/sv32/vm_rwx_access_smode_01.S
Normal file
148
verif/tests/custom/sv32/vm_rwx_access_smode_01.S
Normal file
|
|
@ -0,0 +1,148 @@
|
|||
#=======================================================================
|
||||
# RWX access on S-mode pages in S-mode for level1 PTE when pte.r=1,
|
||||
# pte.w=1, pte.x=1
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE belongs to supervisor mode i.e. its U permission bit is clear
|
||||
# (pte.u = 0), then accessing that PTE in supervisor mode should be
|
||||
# successful if the corresponding (r,w,x) permission of PTE is granted.
|
||||
# Otherwise raise page fault exception of the corresponding access type.
|
||||
#
|
||||
# When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has
|
||||
# non-reserved RWX encoding, pte.u=0 and pte.v=1, then test the
|
||||
# following in supervisor privilege mode for level 0 and level 1 PTE.
|
||||
#
|
||||
# - Test the read access for pte.r=1
|
||||
# - Test the write access for pte.w=1
|
||||
# - Test the execute access for pte.x=1
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# --------LEVEL 1 PTE Setup for load and store and execute access-------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0,( PTE_D | PTE_A | PTE_W | PTE_R | PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
vm_en:
|
||||
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
|
||||
sw t1,0(a1) # test the store access
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
|
||||
check_execute:
|
||||
|
||||
li t1, 0x45 # test the execute access
|
||||
SMODE_ECALL # to go back to M mode
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
.align 24 # Superpage align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
152
verif/tests/custom/sv32/vm_rwx_access_smode_02.S
Normal file
152
verif/tests/custom/sv32/vm_rwx_access_smode_02.S
Normal file
|
|
@ -0,0 +1,152 @@
|
|||
#=======================================================================
|
||||
# RWX access on S-mode pages in S-mode for level0 PTE when pte.r=1,
|
||||
# pte.w=1, pte.x=1
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE belongs to supervisor mode i.e. its U permission bit is clear
|
||||
# (pte.u = 0), then accessing that PTE in supervisor mode should be
|
||||
# successful if the corresponding (r,w,x) permission of PTE is granted.
|
||||
# Otherwise raise page fault exception of the corresponding access type.
|
||||
#
|
||||
# When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has
|
||||
# non-reserved RWX encoding, pte.u=0 and pte.v=1, then test the
|
||||
# following in supervisor privilege mode for level 0 and level 1 PTE.
|
||||
#
|
||||
# - Test the read access for pte.r=1
|
||||
# - Test the write access for pte.w=1
|
||||
# - Test the execute access for pte.x=1
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# --------LEVEL 1 PTE Setup for load and store and execute access-------
|
||||
|
||||
la a1,pgtb_l0 # loads the address of pgtb_l0
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l0, LEVEL0 ) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0,( PTE_D | PTE_A | PTE_W | PTE_R | PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
vm_en:
|
||||
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
|
||||
sw t1,0(a1) # test the store access
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
|
||||
check_execute:
|
||||
|
||||
li t1, 0x45 # test the execute access
|
||||
SMODE_ECALL # to go back to M mode
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
180
verif/tests/custom/sv32/vm_rwx_access_smode_03.S
Normal file
180
verif/tests/custom/sv32/vm_rwx_access_smode_03.S
Normal file
|
|
@ -0,0 +1,180 @@
|
|||
#=======================================================================
|
||||
# RWX access on S-mode pages in S-mode for level1 PTE when pte.r=0,
|
||||
# pte.w=0, pte.x=0
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE belongs to supervisor mode i.e. its U permission bit is clear
|
||||
# (pte.u = 0), then accessing that PTE in supervisor mode should be
|
||||
# successful if the corresponding (r,w,x) permission of PTE is granted.
|
||||
# Otherwise raise page fault exception of the corresponding access type.
|
||||
#
|
||||
# When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has
|
||||
# non-reserved RWX encoding, pte.u=0 and pte.v=1, then test the
|
||||
# following in supervisor privilege mode for level 0 and level 1 PTE.
|
||||
#
|
||||
# - Test the read access for pte.r=0
|
||||
# - Test the write access for pte.w=0
|
||||
# - Test the execute access for pte.x=0
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test------------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A| PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------Store test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_store,CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
|
||||
sw t1,0(a1) # test the store access
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
# ----------------Load test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_load,CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
TEST_STATUS # checks the status of the test
|
||||
SMODE_ECALL # changes mode M to S and set the MEPC
|
||||
|
||||
# ----------------------Execute test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_execute,CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
# -------------LEVEL 1 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_execute # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_V ) # sets the permission bits (PTE_X = 0)
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode-----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,check_execute # loads the address of check_execute
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
|
||||
check_execute:
|
||||
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
.align 24 # Superpage align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
183
verif/tests/custom/sv32/vm_rwx_access_smode_04.S
Normal file
183
verif/tests/custom/sv32/vm_rwx_access_smode_04.S
Normal file
|
|
@ -0,0 +1,183 @@
|
|||
#=======================================================================
|
||||
# RWX access on S-mode pages in S-mode for level0 PTE when pte.r=0,
|
||||
# pte.w=0, pte.x=0
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE belongs to supervisor mode i.e. its U permission bit is clear
|
||||
# (pte.u = 0), then accessing that PTE in supervisor mode should be
|
||||
# successful if the corresponding (r,w,x) permission of PTE is granted.
|
||||
# Otherwise raise page fault exception of the corresponding access type.
|
||||
#
|
||||
# When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has
|
||||
# non-reserved RWX encoding, pte.u=0 and pte.v=1, then test the
|
||||
# following in supervisor privilege mode for level 0 and level 1 PTE.
|
||||
#
|
||||
# - Test the read access for pte.r=0
|
||||
# - Test the write access for pte.w=0
|
||||
# - Test the execute access for pte.x=0
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test------------
|
||||
|
||||
la a1,pgtb_l0 # loads the address of label pgtb_l0
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A| PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l0, LEVEL0 ) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------Store test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_store,CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
|
||||
sw t1,0(a1) # test the store access
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
# ----------------Load test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_load,CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
TEST_STATUS # checks the status of the test
|
||||
SMODE_ECALL # changes mode M to S and set the MEPC
|
||||
|
||||
# ----------------------Execute test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_execute,CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
# -------------LEVEL 1 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_execute # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_V ) # sets the permission bits (PTE_X = 0)
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode-----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,check_execute # loads the address of check_execute
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
|
||||
check_execute:
|
||||
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
197
verif/tests/custom/sv32/vm_rwx_reserved_level_0.S
Normal file
197
verif/tests/custom/sv32/vm_rwx_reserved_level_0.S
Normal file
|
|
@ -0,0 +1,197 @@
|
|||
#=======================================================================
|
||||
# RWX Access of Level0 PTE in User and Supervisor mode when RWX
|
||||
# reserved PTE persmissions (PTE.W=1 only)
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
# If PTE has reserved RWX encodings (pte.w=1 & pte.r=0 & pte.x=0),
|
||||
# then accessing it would raise page fault exception of the corresponding
|
||||
# access type. this test covers the following scenarios in both supervisor
|
||||
# and user privilege modes for level0 PTE.
|
||||
# Level 0
|
||||
# Set PTE.R = 0 and PTE.W = 1 and PTE.X = 0 test the RWX access in SMode
|
||||
# Set PTE.R = 0 and PTE.W = 1 and PTE.X = 0 test the RWX access in UMode
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL1 PTE Setup to point to LEVEL0 PTE----------------
|
||||
la a1,pgtb_l0 # loads the address of label pgtb_l0
|
||||
mv a0, a1 # generrates the VA for label pgtb_l0
|
||||
ori a2, x0, ( PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------LEVEL 0 PTE Setup for load and store test--------------
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_V | PTE_A | SET_PTE_U | PTE_D | PTE_W) # sets the permission bits -- only W permission
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode-----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------Load test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_load,CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
nop
|
||||
TEST_STATUS # checks the status of the test
|
||||
# ----------------Store test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_store,CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
sw t1,0(a1) # test the store access
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
#ifdef smode
|
||||
SMODE_ECALL # changes mode M to S and set the MEPC
|
||||
#else
|
||||
UMODE_ECALL # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
# ----------------------Execute test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_execute,CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
# -------------LEVEL 0 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_execute # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_W | PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,check_execute # loads the address of check_execute
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
|
||||
|
||||
check_execute:
|
||||
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
j exit # Jump to exit
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
.align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
190
verif/tests/custom/sv32/vm_rwx_reserved_level_1.S
Normal file
190
verif/tests/custom/sv32/vm_rwx_reserved_level_1.S
Normal file
|
|
@ -0,0 +1,190 @@
|
|||
#=======================================================================
|
||||
# RWX Access of Level1 PTE in User and Supervisor mode when RWX
|
||||
# reserved PTE persmissions (PTE.W=1 only)
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
# If PTE has reserved RWX encodings (pte.w=1 & pte.r=0 & pte.x=0),
|
||||
# then accessing it would raise page fault exception of the corresponding
|
||||
# access type. this test covers the following scenarios in both supervisor
|
||||
# and user privilege modes for level1 PTE.
|
||||
# Level 1
|
||||
# Set PTE.R = 0 and PTE.W = 1 and PTE.X = 0 test the RWX access in SMode
|
||||
# Set PTE.R = 0 and PTE.W = 1 and PTE.X = 0 test the RWX access in UMode
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#ifdef smode
|
||||
#define SET_PTE_U 0
|
||||
#else
|
||||
#define SET_PTE_U PTE_U
|
||||
#endif
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test------------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32 ( a1, a2, t1, a0, pgtb_l1, LEVEL1 ) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_V | PTE_A | SET_PTE_U | PTE_D | PTE_W ) # sets the permission bits -- only W permission
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode----------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC value to a1
|
||||
#endif
|
||||
|
||||
# ----------------Virtualization Enabeled-------------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# ----------------Load test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_load,CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
TEST_STATUS # checks the status of the test
|
||||
# ----------------Store test prolog--------------------------------------
|
||||
|
||||
TEST_PROLOG(check_store,CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
sw t1,0(a1) # test the store access
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
#ifdef smode
|
||||
SMODE_ECALL # changes mode M to S and set the MEPC
|
||||
#else
|
||||
UMODE_ECALL # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
# ----------------------Execute test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_execute,CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
# -------------LEVEL 1 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_execute # loads the address of label vm_en
|
||||
mv a0, a1 # set the VA to PA (identity mapping)
|
||||
ori a2, x0, ( PTE_D | PTE_A | SET_PTE_U | PTE_X | PTE_W | PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,check_execute # loads the address of check_execute
|
||||
#ifdef smode
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
#else
|
||||
CHANGE_T0_U_MODE(a1) # changes mode M to U and set the MEPC
|
||||
#endif
|
||||
|
||||
check_execute:
|
||||
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
j exit # Jump to exit
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
.align 24 # Superpage align
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
122
verif/tests/custom/sv32/vm_satp_access.S
Normal file
122
verif/tests/custom/sv32/vm_satp_access.S
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
#=======================================================================
|
||||
# Access satp in M, S, and U mode using csrrw, csrrc, csrrs
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# Satp is only accessible in M and S mode and illegal instruction
|
||||
# exception is generated when accessed in lower privilege mode.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#define ALL_F_S 0xffffffff
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
li s1, ALL_F_S # loads the random value in s1
|
||||
li s2, SATP32_PPN # loads the SATP32_PPN value in s2
|
||||
li s3, SATP32_ASID # loads the SATP32_ASID value in s3
|
||||
|
||||
machine_mode:
|
||||
|
||||
csrc satp,s1 # tests the satp access in M mode using csrc
|
||||
csrs satp,s2 # tests the satp access in M mode using csrs
|
||||
csrw satp,s3 # tests the satp access in M mode using csrw
|
||||
la t5, supervisor_mode # loads the supervisor_mode label
|
||||
CHANGE_T0_S_MODE(t5) # changes mode from M to S
|
||||
|
||||
supervisor_mode:
|
||||
|
||||
csrc satp,s1 # tests the satp access in S mode using csrc
|
||||
csrs satp,s2 # tests the satp access in S mode using csrs
|
||||
csrw satp,s3 # tests the satp access in S mode using csrw
|
||||
SMODE_ECALL # ecall to go back to M mode
|
||||
la t5, pre_user_mode # loads the user_mode label
|
||||
CHANGE_T0_U_MODE(t5) # changes mode from M to U
|
||||
|
||||
pre_user_mode:
|
||||
|
||||
TEST_PROLOG(user_mode,CAUSE_ILLEGAL_INSTRUCTION) # load the MEPC addr and expected cause
|
||||
|
||||
user_mode:
|
||||
|
||||
csrc satp,s1 # tests the satp access in S mode using csrc
|
||||
UMODE_ECALL # ecall to go back to M mode
|
||||
j test_pass # jumps to exit label
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
104
verif/tests/custom/sv32/vm_satp_asid.S
Normal file
104
verif/tests/custom/sv32/vm_satp_asid.S
Normal file
|
|
@ -0,0 +1,104 @@
|
|||
#=======================================================================
|
||||
# SATP ASIDLEN
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# ASIDLEN is the number of ASID bits implemented. MAXASID bits for
|
||||
# sv32 is 9
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the mem
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
.set EXPECTED_ASID, 0x00400000
|
||||
.set ASID_IMPLE_CVA6, 0x00400000
|
||||
|
||||
ALL_MEM_PMP # set the PMP permissions
|
||||
csrw satp,x0 # write satp with all zeros (bare mode)
|
||||
la t5, EXPECTED_ASID # ASID bits expected for CVA6
|
||||
la t0, ASID_IMPLE_CVA6 # ASID bits implemented for CVA6
|
||||
csrw satp, t0 # Writes the ASID bits implemented to SATP
|
||||
csrr t1, satp # READS the ASID bits from the SATP
|
||||
and t1, t1, t5 # Checks the expected ASID bits and Implemented bits
|
||||
beq t1, t5, test_pass # Jumps to done if equal
|
||||
j test_fail
|
||||
|
||||
trap_handler:
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
csrr t5,mepc # read the value of mepc
|
||||
|
||||
bne t3,t5, test_fail # check the value of mepc with it's expected value
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # Exit logic
|
||||
|
||||
.data
|
||||
.align 24
|
||||
rvtest_check:
|
||||
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0x00000000
|
||||
.word 0x00000000
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
96
verif/tests/custom/sv32/vm_satp_mode_set.S
Normal file
96
verif/tests/custom/sv32/vm_satp_mode_set.S
Normal file
|
|
@ -0,0 +1,96 @@
|
|||
#=======================================================================
|
||||
# RW Access of satp to
|
||||
# test whether SV-32 is working properly
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
# Verification of supported address translation scheme i.e sv32
|
||||
# is selected by writing satp.mode=sv32 and reading back the satp/ This
|
||||
# covers the following scenarios in machine mode.
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the memory
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
|
||||
check_satp:
|
||||
csrr t1, satp # tests the load access
|
||||
srli t1, t1, 31 # t1 should be equal to 1
|
||||
li t2,1
|
||||
bne t1,t2,test_fail # checks either t1 == t2
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
rvtest_check:
|
||||
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0xcafecafe
|
||||
.word 0xbeefdead
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
188
verif/tests/custom/sv32/vm_sum_clear_level_0.S
Normal file
188
verif/tests/custom/sv32/vm_sum_clear_level_0.S
Normal file
|
|
@ -0,0 +1,188 @@
|
|||
#=======================================================================
|
||||
# RWX Access of Level0 PTE in Supervisor mode when mstatus.SUM unset
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE belongs to user mode i.e. its U permission bit is set
|
||||
# (pte.u = 1) and m/sstatus.SUM = 0, then accessing that PTE in
|
||||
# supervisor mode would raise page fault exception of the
|
||||
# corresponding access type.
|
||||
#
|
||||
# - Set pte.u=1 & s/mstatus.SUM = 0 and test the read acces.
|
||||
# - Set pte.u=1 & s/mstatus.SUM = 0 and test the write access.
|
||||
# - Set pte.u=1 & s/mstatus.SUM = 0 and test the execute access.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the mem
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
PTE_LEVEL0:
|
||||
|
||||
# ----------------LEVEL 0 PTE Setup for load and store test------------
|
||||
|
||||
la a1,pgtb_l0 # loads the address of label pgtb_l0
|
||||
la a0, _start # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
# sets the permission bits
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_W | PTE_R | PTE_V )
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_W | PTE_R | PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
li a1, MSTATUS_SUM
|
||||
csrc mstatus, a1 # Clear mstatus.SUM
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
|
||||
# ----------------Virtualization Enabeled---------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# -------------------Load Test Prolog-------------------------
|
||||
|
||||
TEST_PROLOG(check_load, CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
check_load: # test the load access
|
||||
|
||||
lw t1,0(a1)
|
||||
TEST_STATUS # checks the status of the test
|
||||
nop
|
||||
|
||||
# -------------------Store Test Prolog------------------------
|
||||
|
||||
TEST_PROLOG(check_store, CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
check_store: # test the store access
|
||||
sw t1,0(a1)
|
||||
nop
|
||||
TEST_STATUS # checks the status of the test
|
||||
#ifdef smode
|
||||
SMODE_ECALL # SMODE ecall
|
||||
#else
|
||||
UMODE_ECALL # UMODE ecall
|
||||
#endif
|
||||
|
||||
# -------------------Execute Test Prolog-----------------------
|
||||
|
||||
TEST_PROLOG(check_execute, CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
|
||||
PTE_LEVEL0_EXECUTE:
|
||||
|
||||
# -------------LEVEL 1 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_execute # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
# sets the permission bits
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_X | PTE_V )
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,check_execute # loads the address of check_execute
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
|
||||
check_execute: # test the execute access
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
csrr t5,mepc # read the value of mepc
|
||||
|
||||
bne t3,t5, test_fail # check the value of mepc with it's expected value
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # Exit logic
|
||||
|
||||
.data
|
||||
rvtest_check:
|
||||
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0xcafecafe
|
||||
.word 0xbeefdead
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
183
verif/tests/custom/sv32/vm_sum_clear_level_1.S
Normal file
183
verif/tests/custom/sv32/vm_sum_clear_level_1.S
Normal file
|
|
@ -0,0 +1,183 @@
|
|||
#=======================================================================
|
||||
# RWX Access of Level1 PTE in Supervisor mode when mstatus.SUM unset
|
||||
#-----------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE belongs to user mode i.e. its U permission bit is set
|
||||
# (pte.u = 1) and m/sstatus.SUM = 0, then accessing that PTE in
|
||||
# supervisor mode would raise page fault exception of the
|
||||
# corresponding access type.
|
||||
#
|
||||
# - Set pte.u=1 & s/mstatus.SUM = 0 and test the read acces.
|
||||
# - Set pte.u=1 & s/mstatus.SUM = 0 and test the write access.
|
||||
# - Set pte.u=1 & s/mstatus.SUM = 0 and test the execute access.
|
||||
#
|
||||
#=======================================================================
|
||||
|
||||
#include "macros.h"
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the mem
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
PTE_LEVEL1:
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test-----------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
# sets the permission bits
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_W | PTE_R | PTE_V )
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_W | PTE_R | PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
li a1, MSTATUS_SUM
|
||||
csrc mstatus, a1 # Clear mstatus.SUM
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
|
||||
# ----------------Virtualization Enabeled---------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
# -------------------Load Test Prolog-------------------------
|
||||
|
||||
TEST_PROLOG(check_load, CAUSE_LOAD_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
check_load: # test the load access
|
||||
|
||||
lw t1,0(a1)
|
||||
TEST_STATUS # checks the status of the test
|
||||
nop
|
||||
|
||||
# -------------------Store Test Prolog------------------------
|
||||
|
||||
TEST_PROLOG(check_store, CAUSE_STORE_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
check_store: # test the store access
|
||||
sw t1,0(a1)
|
||||
nop
|
||||
TEST_STATUS # checks the status of the test
|
||||
#ifdef smode
|
||||
SMODE_ECALL # SMODE ecall
|
||||
#else
|
||||
UMODE_ECALL # UMODE ecall
|
||||
#endif
|
||||
|
||||
# -------------------Execute Test Prolog-----------------------
|
||||
|
||||
TEST_PROLOG(check_execute, CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
PTE_LEVEL1_EXECUTE:
|
||||
|
||||
# -------------LEVEL 1 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_execute # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
# sets the permission bits
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_X | PTE_V )
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,check_execute # loads the address of check_execute
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
|
||||
check_execute: # test the execute access
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
li t1, CAUSE_USER_ECALL # load the value of user ecall
|
||||
beq t0,t1,continue_in_m_mode # checks for ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
csrr t5,mepc # read the value of mepc
|
||||
|
||||
bne t3,t5, test_fail # check the value of mepc with it's expected value
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # Exit logic
|
||||
|
||||
.data
|
||||
.align 24
|
||||
rvtest_check:
|
||||
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0xcafecafe
|
||||
.word 0xbeefdead
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
177
verif/tests/custom/sv32/vm_sum_set_level_0.S
Normal file
177
verif/tests/custom/sv32/vm_sum_set_level_0.S
Normal file
|
|
@ -0,0 +1,177 @@
|
|||
#=======================================================================================
|
||||
# RWX access on U-mode pages in S-mode with s/mstatus.SUM set for Level 0 PTE
|
||||
#---------------------------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE belongs to user mode i.e. its U permission bit is set (pte.u = 1)
|
||||
# and m/sstatus.SUM = 1, then RW access to that PTE in supervisor mode would
|
||||
# be successful but eXecute access would raise instruction page fault exception
|
||||
# in s-mode.
|
||||
#
|
||||
# When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has non-reserved RWX
|
||||
# encoding, and pte.v=1, then test the following in supervisor mode for level0 PTE.
|
||||
#
|
||||
# - Set pte.r=1 & pte.u=1 & s/mstatus.SUM = 1 and test the read acces.
|
||||
# - Set pte.w=1 & pte.u=1 & s/mstatus.SUM = 1 and test the write access.
|
||||
# - Set pte.x=1 & pte.u=1 & s/mstatus.SUM = 1 and test the execute access.
|
||||
#
|
||||
#=======================================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
ALL_MEM_PMP # PMP permission to all the mem
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
PTE_LEVEL1_SUPERVISOR:
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test---------------------
|
||||
|
||||
la a1,pgtb_l0 # loads the address of label pgtb_l0
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_W | PTE_R | PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level0
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
li a1, MSTATUS_SUM
|
||||
csrs mstatus, a1 # Clear mstatus.SUM
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
|
||||
# ----------------Virtualization Enabeled---------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
|
||||
sw t1,0(a1) # test the store access
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
SMODE_ECALL # SMODE ecall
|
||||
|
||||
# ----------------------Execute test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_execute, CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
# -------------LEVEL 0 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_execute # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l0, LEVEL0) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,check_execute # loads the address of check_execute
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
|
||||
check_execute:
|
||||
# test the execute access
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
rvtest_check:
|
||||
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 12
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0xcafecafe
|
||||
.word 0xbeefdead
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
170
verif/tests/custom/sv32/vm_sum_set_level_1.S
Normal file
170
verif/tests/custom/sv32/vm_sum_set_level_1.S
Normal file
|
|
@ -0,0 +1,170 @@
|
|||
#=======================================================================================
|
||||
# RWX access on U-mode pages in S-mode with s/mstatus.SUM set for Level 1 PTE
|
||||
#---------------------------------------------------------------------------------------
|
||||
# Test Description:
|
||||
#
|
||||
# If PTE belongs to user mode i.e. its U permission bit is set (pte.u = 1)
|
||||
# and m/sstatus.SUM = 1, then RW access to that PTE in supervisor mode would
|
||||
# be successful but eXecute access would raise instruction page fault exception
|
||||
# in s-mode.
|
||||
#
|
||||
# When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has non-reserved RWX
|
||||
# encoding, and pte.v=1, then test the following in supervisor mode for level1 PTE.
|
||||
#
|
||||
# - Set pte.r=1 & pte.u=1 & s/mstatus.SUM = 1 and test the read acces.
|
||||
# - Set pte.w=1 & pte.u=1 & s/mstatus.SUM = 1 and test the write access.
|
||||
# - Set pte.x=1 & pte.u=1 & s/mstatus.SUM = 1 and test the execute access.
|
||||
#
|
||||
#=======================================================================================
|
||||
|
||||
#include "macros.h"
|
||||
|
||||
#define _MMODE_ "M"
|
||||
#define _SUMODE_ "SU"
|
||||
|
||||
.text
|
||||
.global _start
|
||||
.option norvc
|
||||
|
||||
_start:
|
||||
|
||||
ALL_MEM_PMP # PMP permission to all the mem
|
||||
la t1,trap_handler # loads the address of trap handler
|
||||
csrw mtvec,t1 # sets the mtvec to trap handler
|
||||
|
||||
# ----------------LEVEL 1 PTE Setup for load and store test------------
|
||||
|
||||
la a1,vm_en # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_data # loads the address of label rvtest_data
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_W | PTE_R | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
la a1,rvtest_check # loads the address of label rvtest_check
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_W | PTE_R | PTE_V) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
li a1, MSTATUS_SUM
|
||||
csrs mstatus, a1 # Clear mstatus.SUM
|
||||
la a1,vm_en # loads the address of vm_en
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC value to a1
|
||||
|
||||
# ----------------Virtualization Enabeled-----------------------------
|
||||
|
||||
vm_en:
|
||||
|
||||
la a1, rvtest_data # loads the address of label rvtest_data
|
||||
|
||||
check_store:
|
||||
|
||||
sw t1,0(a1) # test the store access
|
||||
|
||||
check_load:
|
||||
|
||||
lw t1,0(a1) # tests the load access
|
||||
SMODE_ECALL # SMODE ecall
|
||||
|
||||
# ----------------------Execute test prolog------------------------------
|
||||
|
||||
TEST_PROLOG(check_execute, CAUSE_FETCH_PAGE_FAULT) # load the addr and expected cause
|
||||
|
||||
# -------------LEVEL 1 PTE Setup for execute test------------------------
|
||||
# Setup a new PTE to test execute
|
||||
la a1,check_execute # loads the address of label vm_en
|
||||
mv a0, a1 # VA = PA - Identity Map
|
||||
ori a2, x0, ( PTE_D | PTE_A | PTE_U | PTE_X | PTE_V ) # sets the permission bits
|
||||
PTE_SETUP_RV32(a1, a2, t1, a0, pgtb_l1, LEVEL1) # setup the PTE for level1
|
||||
|
||||
# ----------------Set the SATP and change the mode---------------------
|
||||
|
||||
SATP_SETUP_SV32(pgtb_l1) # set the SATP for virtualization
|
||||
la a1,check_execute # loads the address of check_execute
|
||||
CHANGE_T0_S_MODE(a1) # changes mode M to S and set the MEPC
|
||||
|
||||
check_execute:
|
||||
# test the execute access
|
||||
li t1, 0x45 # page fault should raise
|
||||
TEST_STATUS # checks the status of the test
|
||||
j test_pass
|
||||
|
||||
trap_handler:
|
||||
|
||||
csrr t0, mcause # read the value of mcause
|
||||
la t1, rvtest_check # load the address of trvtest_check
|
||||
|
||||
lw t2, 0(t1) # if cause expected then load 1 else 0
|
||||
lw t3, 4(t1) # load the expected value of mepc
|
||||
lw t4, 8(t1) # load the expected value of mcause
|
||||
|
||||
li t1, CAUSE_SUPERVISOR_ECALL # load the value of supervisor ecall
|
||||
beq t0,t1,continue_in_m_mode # checks if ecall is occured
|
||||
|
||||
beqz t2, test_fail # Jumps to exit if cause is not expected
|
||||
|
||||
csrr t5,mepc # read the value of mepc
|
||||
bne t3,t5,test_fail # check the value of mepc with it's expected value
|
||||
|
||||
bne t0, t4, test_fail # jumps to exit if EXPECTED_CAUSE is'nt equal to mcause
|
||||
|
||||
li t5, CAUSE_FETCH_PAGE_FAULT # load the value of fetch page fault exception
|
||||
beq t0,t5,continue_in_m_mode # if fetch page fault jump to next instr in M mode
|
||||
|
||||
continue_execution:
|
||||
|
||||
INCREMENT_MEPC _SUMODE_ # update the value of mepc
|
||||
j trap_epilogs
|
||||
|
||||
continue_in_m_mode:
|
||||
|
||||
INCREMENT_MEPC _MMODE_ # update the value of mepc
|
||||
li t1,MSTATUS_MPP # update the MPP to MSTATUS_MPP for M mode
|
||||
csrs mstatus,t1 # update the value mstatus MPP
|
||||
|
||||
trap_epilogs:
|
||||
|
||||
la t1, rvtest_check # load the addr of rvtest_check
|
||||
li t2, 0
|
||||
sw t2, 0(t1) # Clear the expected cause
|
||||
sw t2, 4(t1) # Clear the exception PC
|
||||
sw t2, 8(t1) # Clear cause execution number
|
||||
mret
|
||||
|
||||
test_pass:
|
||||
|
||||
li x1, 0 # Write 0 in x1 if test pass
|
||||
j exit # Jump to exit
|
||||
|
||||
test_fail:
|
||||
|
||||
li x1, 1 # Write 1 in x1 if test failed
|
||||
|
||||
COREV_VERIF_EXIT_LOGIC # exit logic
|
||||
|
||||
.data
|
||||
.align 24
|
||||
rvtest_check:
|
||||
.word 0xdeadbeef # 1 for cause expected 0 for no cause
|
||||
.word 0xbeefdead # write the value of mepc here (where cause is expected)
|
||||
.word 0xcafecafe # write the value of expect cause
|
||||
.align 22
|
||||
rvtest_data:
|
||||
.word 0xbeefcafe
|
||||
.word 0xdeadcafe
|
||||
.word 0xcafecafe
|
||||
.word 0xbeefdead
|
||||
.align 12
|
||||
pgtb_l1:
|
||||
.zero 4096
|
||||
pgtb_l0:
|
||||
.zero 4096
|
||||
|
||||
.align 4; .global tohost; tohost: .dword 0;
|
||||
.align 4; .global fromhost; fromhost: .dword 0;
|
||||
512
verif/tests/testlist_riscv-mmu-sv32-arch-test-cv32a60x.yaml
Normal file
512
verif/tests/testlist_riscv-mmu-sv32-arch-test-cv32a60x.yaml
Normal file
|
|
@ -0,0 +1,512 @@
|
|||
# Copyright Google LLC
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
# ================================================================================
|
||||
# Regression test list format
|
||||
# --------------------------------------------------------------------------------
|
||||
# test : Assembly test name
|
||||
# description : Description of this test
|
||||
# gen_opts : Instruction generator options
|
||||
# iterations : Number of iterations of this test
|
||||
# no_iss : Enable/disable ISS simulator (Optional)
|
||||
# gen_test : Test name used by the instruction generator
|
||||
# asm_tests : Path to directed, hand-coded assembly test file or directory
|
||||
# rtl_test : RTL simulation test name
|
||||
# cmp_opts : Compile options passed to the instruction generator
|
||||
# sim_opts : Simulation options passed to the instruction generator
|
||||
# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional)
|
||||
# compare_opts : Options for the RTL & ISS trace comparison
|
||||
# gcc_opts : gcc compile options
|
||||
# --------------------------------------------------------------------------------
|
||||
|
||||
- test: rv32_vm_satp_access
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_satp_access.S
|
||||
|
||||
- test: rv32_vm_invalid_pte_level_1_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_invalid_pte_level_1.S
|
||||
|
||||
- test: rv32_vm_invalid_pte_level_1_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -Dsmdoe=True -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_invalid_pte_level_1.S
|
||||
|
||||
- test: rv32_vm_invalid_pte_level_0_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_invalid_pte_level_0.S
|
||||
|
||||
- test: rv32_vm_invalid_pte_level_0_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -Dsmdoe=True -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_invalid_pte_level_0.S
|
||||
|
||||
- test: rv32_vm_misaligned_superpage_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_misaligned_superpage.S
|
||||
|
||||
- test: rv32_vm_misaligned_superpage_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -Dsmdoe=True -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_misaligned_superpage.S
|
||||
|
||||
- test: rv32_vm_sum_set_level_1
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_sum_set_level_1.S
|
||||
|
||||
- test: rv32_vm_sum_set_level_0
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_sum_set_level_0.S
|
||||
|
||||
- test: rv32_vm_rwx_access_smode_01
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_rwx_access_smode_01.S
|
||||
|
||||
- test: rv32_vm_rwx_access_smode_02
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_rwx_access_smode_02.S
|
||||
|
||||
- test: rv32_vm_rwx_access_smode_03
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_rwx_access_smode_03.S
|
||||
|
||||
- test: rv32_vm_rwx_access_smode_04
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_rwx_access_smode_04.S
|
||||
|
||||
- test: rv32_vm_access_bit_level_0_01_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -Dsmode=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_access_bit_level_0.S
|
||||
|
||||
- test: rv32_vm_access_bit_level_0_01_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_access_bit_level_0.S
|
||||
|
||||
- test: rv32_vm_access_bit_level_1_02_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -Dsmode=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_access_bit_level_1.S
|
||||
|
||||
- test: rv32_vm_access_bit_level_1_02_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_access_bit_level_1.S
|
||||
|
||||
- test: rv32_vm_mxr_clear_level_0_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -Dsmode=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_mxr_clear_level_0.S
|
||||
|
||||
- test: rv32_vm_mxr_clear_level_0_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_mxr_clear_level_0.S
|
||||
|
||||
- test: rv32_vm_mxr_clear_level_1_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -Dsmode=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_mxr_clear_level_1.S
|
||||
|
||||
- test: rv32_vm_mxr_clear_level_1_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_mxr_clear_level_1.S
|
||||
|
||||
- test: rv32_vm_sum_clear_level_0
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -Dsmode=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_sum_clear_level_0.S
|
||||
|
||||
- test: rv32_vm_sum_clear_level_1
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -Dsmode=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_sum_clear_level_1.S
|
||||
|
||||
- test: rv32_vm_pmp_check_level_0_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -Dsmode=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_pmp_check_level_0.S
|
||||
|
||||
- test: rv32_vm_pmp_check_level_0_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_pmp_check_level_0.S
|
||||
|
||||
- test: rv32_vm_pmp_check_level_1_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -Dsmode=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_pmp_check_level_1.S
|
||||
|
||||
- test: rv32_vm_pmp_check_level_1_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_pmp_check_level_1.S
|
||||
|
||||
- test: rv32_vm_dirty_bit_level_1_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_dirty_bit_level_1.S
|
||||
|
||||
- test: rv32_vm_dirty_bit_level_1_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -Dsmode=True -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_dirty_bit_level_1.S
|
||||
|
||||
- test: rv32_vm_dirty_bit_level_0_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_dirty_bit_level_0.S
|
||||
|
||||
- test: rv32_vm_dirty_bit_level_0_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -Dsmode=True -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_dirty_bit_level_0.S
|
||||
|
||||
- test: rv32_vm_mstatus_tvm_level_1_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_mstatus_tvm_level_1.S
|
||||
|
||||
- test: rv32_vm_mstatus_tvm_level_1_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -Dsmode=True -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_mstatus_tvm_level_1.S
|
||||
|
||||
- test: rv32_vm_mstatus_tvm_level_0_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_mstatus_tvm_level_0.S
|
||||
|
||||
- test: rv32_vm_mstatus_tvm_level_0_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -Dsmode=True -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_mstatus_tvm_level_0.S
|
||||
|
||||
- test: rv32_vm_mxr_set_level_1_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_mxr_set_level_1.S
|
||||
|
||||
- test: rv32_vm_mxr_set_level_1_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -Dsmode=True -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_mxr_set_level_1.S
|
||||
|
||||
- test: rv32_vm_mxr_set_level_0_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_mxr_set_level_0.S
|
||||
|
||||
- test: rv32_vm_mxr_set_level_0_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -Dsmode=True -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_mxr_set_level_0.S
|
||||
|
||||
- test: rv32_vm_rwx_reserved_level_1_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_rwx_reserved_level_1.S
|
||||
|
||||
- test: rv32_vm_rwx_reserved_level_1_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -Dsmode=True -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_rwx_reserved_level_1.S
|
||||
|
||||
- test: rv32_vm_rwx_reserved_level_0_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_rwx_reserved_level_0.S
|
||||
|
||||
- test: rv32_vm_rwx_reserved_level_0_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -Dsmode=True -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_rwx_reserved_level_0.S
|
||||
|
||||
- test: rv32_vm_satp_mode_set
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_satp_mode_set.S
|
||||
|
||||
- test: rv32_vm_nonlead_pte_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_nonleaf_pte.S
|
||||
|
||||
- test: rv32_vm_nonlead_pte_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -Dsmode=True -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_nonleaf_pte.S
|
||||
|
||||
- test: rv32_vm_pte_pmp_check_level_1_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_pte_pmp_check_level_1.S
|
||||
|
||||
- test: rv32_vm_pte_pmp_check_level_1_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -Dsmode=True -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_pte_pmp_check_level_1.S
|
||||
|
||||
- test: rv32_vm_pte_pmp_check_level_0_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_pte_pmp_check_level_0.S
|
||||
|
||||
- test: rv32_vm_pte_pmp_check_level_0_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DENTROPY=0x1 -static -Dsmode=True -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/sv32/vm_pte_pmp_check_level_0.S
|
||||
|
||||
- test: rv32_vm_bare_mode_level_1_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_bare_mode_level_1.S
|
||||
|
||||
- test: rv32_vm_bare_mode_level_1_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -Dsmode=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_bare_mode_level_1.S
|
||||
|
||||
- test: rv32_vm_bare_mode_level_0_u
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_bare_mode_level_0.S
|
||||
|
||||
- test: rv32_vm_bare_mode_level_0_s
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -Dsmode=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_bare_mode_level_0.S
|
||||
|
||||
- test: rv32_vm_pte_u_bit_set_01
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_pte_u_bit_set_01.S
|
||||
|
||||
- test: rv32_vm_pte_u_bit_set_02
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_pte_u_bit_set_02.S
|
||||
|
||||
- test: rv32_vm_pte_u_bit_set_03
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_pte_u_bit_set_03.S
|
||||
|
||||
- test: rv32_vm_pte_u_bit_set_04
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_pte_u_bit_set_04.S
|
||||
|
||||
- test: rv32_vm_pte_u_bit_unset_level_1
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_pte_u_bit_unset_level_1.S
|
||||
|
||||
- test: rv32_vm_pte_u_bit_unset_level_0
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
march: rv32izicsr
|
||||
mabi: ilp32
|
||||
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/ -Drvtest_mtrap_routine=True -Drvtest_strap_routine=True"
|
||||
asm_tests: <path_var>/custom/sv32/vm_pte_u_bit_unset_level_0.S
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue