Set up infrastructure for Spike YAML parameter tests (#2089)

.gitlab-ci.yml

@@ -88,7 +88,8 @@ build_tools:
   extends:
     - .setup_job
   script:
-    - git submodule update --init verif/core-v-verif
+    # core-v-verif imports yaml-cpp as a submodule ==> recurse
+    - git submodule update --init --recursive verif/core-v-verif
     - source $SYN_VCS_BASHRC
     # ROOT_PROJECT is used by Spike installer and designates the toplevel of core-v-verif tree.
     - 'export ROOT_PROJECT=$(pwd)'

verif/sim/Makefile

@@ -54,6 +54,23 @@ ifneq ($(steps),)
   spike_stepout = --steps=$(steps)
 endif
 
+##############################################
+# Set up Spike configuration files
+##############################################
+
+# Set default Spike parameter file.
+spike_yaml ?= $(CVA6_REPO_DIR)/verif/spike_configs/$(target).yaml
+
+# Set up flags for Spike solo and tandem invocations, but only if parameter file exists.
+ifneq ($(wildcard $(spike_yaml)),)
+  spike_params += --yaml-param $(spike_yaml)
+  spike-yaml-plusarg = +config_file=$(CVA6_REPO_DIR)/verif/spike_configs/$(target).yaml
+endif
+
+##############################################
+# Waveform configuration
+##############################################
+
 # TRACE_FAST, TRACE_COMPACT and VERDI are mutually exclusive and imply non-empty DEBUG.
 ifneq ($(TRACE_FAST),)
 ifneq ($(TRACE_COMPACT),)
@@ -132,6 +149,7 @@ vcs-testharness:
 	make -C $(path_var) vcs_build target=$(target) defines=$(subst +define+,,$(isscomp_opts))$(if $(spike-tandem),SPIKE_TANDEM=1)
 	$(path_var)/work-vcs/simv $(if $(VERDI), -verdi -do $(path_var)/util/init_testharness.do,) +permissive \
 	  +tohost_addr=$(shell $$RISCV/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
+          $(spike-yaml-plusarg) \
 	  +elf_file=$(elf) +permissive-off ++$(elf) $(issrun_opts)  \
 	  $(if $(spike-tandem),-sv_lib $(SPIKE_INSTALL_DIR)/lib/libdisasm) \
 	  $(if $(spike-tandem),-sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv) \
@@ -214,6 +232,21 @@ COMMON_COMP_UVM_FLAGS = \
 COMMON_PLUS_ARGS = \
 	++$(elf) \
 	+elf_file=$(elf) \
+        $(spike-yaml-plusarg) \
+	+tohost_addr=$(shell $$RISCV/bin/$(CV_SW_PREFIX)nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
+	+signature=$(elf).signature_output  +UVM_TESTNAME=uvmt_cva6_firmware_test_c
+
+ifneq ($(UVM_VERBOSITY),)
+COMMON_PLUS_ARGS += +UVM_VERBOSITY=$(UVM_VERBOSITY)
+endif
+
+COMMON_RUN_UVM_FLAGS = \
+	-sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv \
+	-sv_lib $(SPIKE_INSTALL_DIR)/lib/libfesvr \
+	-sv_lib $(SPIKE_INSTALL_DIR)/lib/libdisasm \
+	++$(elf) \
+	+elf_file=$(elf) \
+	$(spike-yaml-plusarg) \
 	+tohost_addr=$(shell $$RISCV/bin/$(CV_SW_PREFIX)nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
 	+signature=$(elf).signature_output  +UVM_TESTNAME=uvmt_cva6_firmware_test_c
 

verif/spike_configs/cv32a65x.yaml

@@ -0,0 +1,28 @@
+spike_param_tree:
+  bootrom: true
+  bootrom_base: 0x10000
+  bootrom_size: 0x1000
+  dram: true
+  dram_base: 0x80000000
+  dram_size: 0x40000000
+  generic_core_config: false
+  max_steps: 200000
+  max_steps_enabled: false
+  isa: rv32imc_zba_zbb_zbs_zbc_zicsr_zifencei
+  priv: MSU
+  core_configs:
+    - isa: rv32imc_zba_zbb_zbs_zbc_zicsr_zifencei
+      marchid: 0x3
+      misa_we: false
+      misa_we_enable: true
+      misaligned: false
+      mmu_mode: sv39
+      mvendorid: 0x00000602
+      pmpaddr0: 0x0
+      pmpcfg0: 0x0
+      pmpregions: 0x0
+      priv: MSU
+      status_fs_field_we: false
+      status_fs_field_we_enable: false
+      status_vs_field_we: false
+      status_vs_field_we_enable: false