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Removing unnecessary branch operators
This commit is contained in:
Florian Zaruba
parent
0a81031e5a
commit
74c33bf1ba
5 changed files with 50 additions and 60 deletions
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@ -63,14 +63,14 @@ package ariane_pkg;
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// ---------------
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// EX Stage
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// ---------------
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typedef enum logic [7:0] { // basic ALU op
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typedef enum logic [5:0] { // basic ALU op
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ADD, SUB, ADDW, SUBW,
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// logic operations
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XORL, ORL, ANDL,
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// shifts
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SRA, SRL, SLL, SRLW, SLLW, SRAW,
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// comparisons
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LTS, LTU, LES, LEU, GTS, GTU, GES, GEU, EQ, NE,
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LTS, LTU, GES, GEU, EQ, NE,
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// jumps
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JAL, JALR,
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// set lower than operations
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37
src/alu.sv
37
src/alu.sv
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@ -58,11 +58,8 @@ module alu
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SUB, SUBW,
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// COMPARATOR OPs
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EQ, NE,
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GTU, GEU,
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LTU, LEU,
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GTS, GES,
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LTS, LES,
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SLTS, SLTU,
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GEU, LTU,
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GES, LTS,
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SLETS, SLETU: adder_op_b_negate = 1'b1;
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default: ;
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@ -150,12 +147,7 @@ module alu
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cmp_signed = 1'b0;
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unique case (operator_i)
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GTS,
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GES,
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LTS,
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LES,
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SLTS,
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SLETS: begin
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GES, LTS: begin
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cmp_signed = 1'b1;
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end
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@ -187,15 +179,12 @@ module alu
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cmp_result = 1'b1;
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unique case (operator_i)
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EQ: cmp_result = is_equal;
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NE: cmp_result = (~is_equal);
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GTS, GTU: cmp_result = is_greater_equal && (~is_equal);
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EQ: cmp_result = is_equal;
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NE: cmp_result = (~is_equal);
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// GTS, GTU: cmp_result = is_greater_equal && (~is_equal);
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GES, GEU: cmp_result = is_greater_equal;
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LTS, SLTS,
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LTU, SLTU: cmp_result = (~is_greater_equal);
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SLETS,
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SLETU,
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LES, LEU: cmp_result = (~is_greater_equal) || is_equal;
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LTS, LTU: cmp_result = (~is_greater_equal);
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// LES, LEU: cmp_result = (~is_greater_equal) || is_equal;
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default: ;
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endcase
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@ -228,13 +217,9 @@ module alu
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SRLW, SRAW: result_o = {{32{shift_result32[31]}}, shift_result32[31:0]};
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// Comparison Operations
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EQ, NE,
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GTU, GEU,
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LTU, LEU,
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GTS, GES,
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LTS, LES,
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SLTS, SLTU,
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SLETS, SLETU: result_o = {63'b0, cmp_result};
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EQ, NE,
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LTU, GEU,
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GES, LTS : result_o = {63'b0, cmp_result};
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default: ; // default case to suppress unique warning
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endcase
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@ -127,6 +127,7 @@ module ariane
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logic [63:0] operand_b_id_ex;
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logic [63:0] operand_c_id_ex;
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logic [63:0] pc_id_ex;
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logic is_compressed_instr_id_ex;
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// ALU
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logic alu_ready_ex_id;
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logic alu_valid_id_ex;
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@ -34,6 +34,7 @@ module branch_engine (
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output exception branch_ex_o // branch exception out
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);
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logic [63:0] target_address;
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logic [63:0] next_pc;
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always_comb begin : target_address_calc
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target_address = 64'b0;
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@ -42,17 +43,20 @@ module branch_engine (
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branchpredict_o.is_taken = 1'b0;
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branchpredict_o.valid = valid_i;
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branchpredict_o.is_mispredict = 1'b0;
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// calculate next PC, depending on whether the instruction is compressed or not this may be different
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next_pc = pc_i + (is_compressed_instr_i) ? 64'h2 : 64'h4;
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// calculate target address simple 64 bit addition
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target_address = $signed(operand_a_i) + $signed(operand_b_i);
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// save pc
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branchpredict_o.pc = pc_i;
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// write target address which goes to pc gen
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branchpredict_o.target_address = (comparison_result_i) ? target_address : next_pc;
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branchpredict_o.is_taken = comparison_result_i;
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if (valid_i) begin
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// save pc
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branchpredict_o.pc = pc_i;
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// calculate target address simple 64 bit addition
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target_address = $signed(operand_a_i) + $signed(operand_b_i);
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// write target address which goes to pc gen
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branchpredict_o.target_address = (comparison_result_i) ? target_address : pc_i + (is_compressed_instr_i) ? 64'h2 : 64'h4;
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branchpredict_o.is_taken = comparison_result_i;
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// we mis-predicted e.g.: the predicted address is unequal to the actual address
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if (target_address[1:0] == 2'b0) begin
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// TODO in case of branch which is not taken it is not necessary to check for the address
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if ( target_address != predict_address_i // we mis-predicted the address of the branch
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|| predict_taken_i != comparison_result_i // we mis-predicted the outcome of the branch
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|| predict_branch_valid_i == 1'b0 // this means branch-prediction thought it was no branch but in reality it was one
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50
src/lsu.sv
50
src/lsu.sv
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@ -353,32 +353,32 @@ module lsu #(
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// essentially the same part as in IDLE but we can't accept a new store
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// as the store could immediately be performed and we would collide on the
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// trans id part (e.g.: a structural hazard)
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if (op == LD_OP & lsu_valid_i) begin
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translation_req = 1'b1;
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// we can never handle a load in a single cycle
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// but at least on a tlb hit we can output it to the memory
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if (translation_valid) begin
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// check if the address is in the store buffer otherwise we need
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// to wait until the store buffer has cleared its entry
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if (~address_match) begin
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// lets request this read
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data_req_i[1] = 1'b1;
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// we already got a grant here so lets wait for the rvalid
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if (data_gnt_o[1]) begin
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NS = LOAD_WAIT_RVALID;
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end else begin // we didn't get a grant so wait for it in a separate stage
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NS = LOAD_WAIT_GNT;
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end
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end
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end else begin// otherwise we need to wait for the translation
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NS = LOAD_WAIT_TRANSLATION;
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end
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// STORE
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end else if (op == ST_OP & lsu_valid_i) begin
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NS = STORE;
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end else begin
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// if (op == LD_OP & lsu_valid_i) begin
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// translation_req = 1'b1;
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// // we can never handle a load in a single cycle
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// // but at least on a tlb hit we can output it to the memory
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// if (translation_valid) begin
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// // check if the address is in the store buffer otherwise we need
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// // to wait until the store buffer has cleared its entry
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// if (~address_match) begin
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// // lets request this read
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// data_req_i[1] = 1'b1;
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// // we already got a grant here so lets wait for the rvalid
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// if (data_gnt_o[1]) begin
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// NS = LOAD_WAIT_RVALID;
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// end else begin // we didn't get a grant so wait for it in a separate stage
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// NS = LOAD_WAIT_GNT;
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// end
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// end
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// end else begin// otherwise we need to wait for the translation
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// NS = LOAD_WAIT_TRANSLATION;
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// end
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// // STORE
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// end else if (op == ST_OP & lsu_valid_i) begin
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// NS = STORE;
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// end else begin
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NS = IDLE;
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end
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// end
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end else begin
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// and stall
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