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Remove flush logic from arbiter, moved to units
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2 changed files with 21 additions and 53 deletions
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@ -25,7 +25,6 @@ module dcache_arbiter #(
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(
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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input logic flush_i,
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// slave port
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output logic [11:0] address_index_o,
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output logic [43:0] address_tag_o,
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@ -53,8 +52,6 @@ module dcache_arbiter #(
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);
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// one-hot encoded
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localparam DATA_WIDTH = NR_PORTS;
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// registers
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enum logic {IDLE, WAIT_FLUSH} CS, NS;
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// remember the request port in case of a multi-cycle transaction
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logic [DATA_WIDTH-1:0] request_port_n, request_port_q;
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// local ports
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@ -68,12 +65,6 @@ module dcache_arbiter #(
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// FIFO output port
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logic [DATA_WIDTH-1:0] out_data;
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logic pop;
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logic flush_ready;
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// essentially wait for the queue to be empty
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// or we just got a grant -> this means we issued a memory request in this cycle
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// although we are ready if we only got a single element in the queue and an rvalid
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// which means we are getting this element back in this cycle
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assign flush_ready = (empty & ~(|data_gnt_i)) | (single_element & data_rvalid_i);
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fifo #(
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.dtype ( logic [DATA_WIDTH-1:0] ),
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@ -96,51 +87,36 @@ module dcache_arbiter #(
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always_comb begin : read_req_write
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automatic logic [DATA_WIDTH-1:0] request_index = request_port_q;
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data_req_o = 1'b0;
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in_data = '{default: 0};
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push = 1'b0;
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request_port_n = request_port_q;
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NS = CS;
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for (int i = 0; i < NR_PORTS; i++)
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data_gnt_o[i] = 1'b0;
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case (CS)
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// ----------------------------
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// Single-cycle memory requests
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// ----------------------------
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IDLE: begin
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// only go for a new request if we can wait for the valid e.g.: we have enough space in the buffer
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if (~full) begin
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for (int unsigned i = 0; i < NR_PORTS; i++) begin
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if (data_req_i[i] == 1'b1) begin
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data_req_o = data_req_i[i];
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// save the request port for future states
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request_port_n = i;
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request_index = i;
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// wait for the grant
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if (data_gnt_i) begin
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// set the slave on which we are waiting
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in_data = 1'b1 << i[DATA_WIDTH-1:0];
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push = 1'b1;
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end
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break; // break here as this is a priority select
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end
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// ----------------------------
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// Single-cycle memory requests
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// ----------------------------
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// only go for a new request if we can wait for the valid e.g.: we have enough space in the buffer
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if (~full) begin
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for (int unsigned i = 0; i < NR_PORTS; i++) begin
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if (data_req_i[i] == 1'b1) begin
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data_req_o = data_req_i[i];
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// save the request port for future states
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request_port_n = i;
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request_index = i;
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// wait for the grant
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if (data_gnt_i) begin
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// set the slave on which we are waiting
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in_data = 1'b1 << i[DATA_WIDTH-1:0];
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push = 1'b1;
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end
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break; // break here as this is a priority select
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end
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end
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// ----------------------------
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// Flush logic
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// ----------------------------
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// here we are waiting for the FIFO to drain until we are ready to accept new requests
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WAIT_FLUSH: begin
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// if the flush has finished go to IDLE
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if (flush_ready)
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NS = IDLE;
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end
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default : /* default */;
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endcase
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end
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// pass through all signals from the correct slave port
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address_index_o = address_index_i[request_index];
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data_wdata_o = data_wdata_i[request_index];
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@ -151,11 +127,6 @@ module dcache_arbiter #(
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address_tag_o = address_tag_i[request_port_q];
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kill_req_o = kill_req_i[request_port_q];
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tag_valid_o = tag_valid_i[request_port_q];
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// if we got a flush and we are not ready for the flush wait and for it and don't accept any incoming data
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// e.g.: jump to the flush wait state
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if (flush_i && !flush_ready)
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NS = WAIT_FLUSH;
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end
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// ------------
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@ -183,11 +154,9 @@ module dcache_arbiter #(
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// sequential process
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if(~rst_ni) begin
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CS <= IDLE;
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if (~rst_ni) begin
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request_port_q <= 1'b0;
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end else begin
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CS <= NS;
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request_port_q <= request_port_n;
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end
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end
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@ -40,7 +40,6 @@ module dcache_arbiter_tb;
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dcache_arbiter dut (
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.clk_i ( clk ),
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.rst_ni ( rst_ni ),
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.flush_i ( 1'b0 ),
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.address_index_o ( slave.address_index ),
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.address_tag_o ( slave.address_tag ),
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