github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-24 14:17:16 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 3

improve case coding style to improve CC (#1607)

Browse source
This commit is contained in:
JeanRochCoulon 2023-11-10 12:15:42 +01:00 • committed by GitHub
parent 220f534b6d
commit 7872d0124c
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 18 additions and 14 deletions
Download patch file Download diff file Expand all files Collapse all files

32
core/load_unit.sv
View file

@ -476,23 +476,27 @@ module load_unit
result_o = {{riscv::XLEN - 32 + 16{rdata_sign_bit}}, shifted_data[15:0]};
ariane_pkg::LB, ariane_pkg::LBU:
result_o = {{riscv::XLEN - 32 + 24{rdata_sign_bit}}, shifted_data[7:0]};
ariane_pkg::FLW: begin
default: begin
// FLW, FLH and FLB have been defined here in default case to improve Code Coverage
if (CVA6Cfg.FpPresent) begin
result_o = {{riscv::XLEN - 32{rdata_sign_bit}}, shifted_data[31:0]};
unique case (ldbuf_rdata.operation)
ariane_pkg::FLW: begin
result_o = {{riscv::XLEN - 32{rdata_sign_bit}}, shifted_data[31:0]};
end
ariane_pkg::FLH: begin
result_o = {{riscv::XLEN - 32 + 16{rdata_sign_bit}}, shifted_data[15:0]};
end
ariane_pkg::FLB: begin
result_o = {{riscv::XLEN - 32 + 24{rdata_sign_bit}}, shifted_data[7:0]};
end
default: begin
result_o = shifted_data[riscv::XLEN-1:0];
end
endcase
end else begin
result_o = shifted_data[riscv::XLEN-1:0];
end
end
ariane_pkg::FLH: begin
if (CVA6Cfg.FpPresent) begin
result_o = {{riscv::XLEN - 32 + 16{rdata_sign_bit}}, shifted_data[15:0]};
end
end
ariane_pkg::FLB: begin
if (CVA6Cfg.FpPresent) begin
result_o = {{riscv::XLEN - 32 + 24{rdata_sign_bit}}, shifted_data[7:0]};
end
end
default: result_o = shifted_data[riscv::XLEN-1:0];
endcase
end
// end result mux fast