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Modify coding style to improve CC (#1642)

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AEzzejjari 2023-11-21 19:04:55 +01:00 • committed by GitHub
parent 77880fcbd3
commit 7963448287
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3 changed files with 35 additions and 38 deletions
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4
core/commit_stage.sv
View file

@ -127,7 +127,7 @@ module commit_stage
we_gpr_o[0] = 1'b1;
end
// check whether the instruction we retire was a store
if (commit_instr_i[0].fu == STORE && !instr_0_is_amo) begin
if ((!CVA6Cfg.RVA && commit_instr_i[0].fu == STORE) || (CVA6Cfg.RVA && commit_instr_i[0].fu == STORE && !instr_0_is_amo)) begin
// check if the LSU is ready to accept another commit entry (e.g.: a non-speculative store)
if (commit_lsu_ready_i) begin
commit_ack_o[0] = 1'b1;
@ -185,7 +185,7 @@ module commit_stage
// from interrupt service routine
// Fence synchronizes data and instruction streams. That means that we need to flush the private icache
// and the private dcache. This is the most expensive instruction.
if (commit_instr_i[0].op == FENCE_I || (flush_dcache_i && commit_instr_i[0].fu != STORE)) begin
if (commit_instr_i[0].op == FENCE_I || (flush_dcache_i && DCACHE_TYPE == int'(config_pkg::WB) && commit_instr_i[0].fu != STORE)) begin
commit_ack_o[0] = no_st_pending_i;
// tell the controller to flush the I$
fence_i_o = no_st_pending_i;

22
core/controller.sv
View file

@ -137,17 +137,17 @@ module controller
// Set PC to commit stage and flush pipeline
if (flush_csr_i || flush_acc_i) begin
set_pc_commit_o = 1'b1;
flush_if_o = 1'b1;
flush_unissued_instr_o = 1'b1;
flush_id_o = 1'b1;
flush_ex_o = 1'b1;
set_pc_commit_o = 1'b1;
flush_if_o = 1'b1;
flush_unissued_instr_o = 1'b1;
flush_id_o = 1'b1;
flush_ex_o = 1'b1;
end else if (CVA6Cfg.RVA && flush_commit_i) begin
set_pc_commit_o = 1'b1;
flush_if_o = 1'b1;
flush_unissued_instr_o = 1'b1;
flush_id_o = 1'b1;
flush_ex_o = 1'b1;
set_pc_commit_o = 1'b1;
flush_if_o = 1'b1;
flush_unissued_instr_o = 1'b1;
flush_id_o = 1'b1;
flush_ex_o = 1'b1;
end
// ---------------------------------
@ -175,7 +175,7 @@ module controller
// ----------------------
always_comb begin
// halt the core if the fence is active
halt_o = halt_csr_i || halt_acc_i || fence_active_q;
halt_o = halt_csr_i || halt_acc_i || (DCACHE_TYPE == int'(config_pkg::WB) && fence_active_q);
end
// ----------------------

47
core/csr_regfile.sv
View file

@ -1067,7 +1067,7 @@ module csr_regfile
trap_to_priv_lvl = riscv::PRIV_LVL_M;
// Exception is taken and we are not in debug mode
// exceptions in debug mode don't update any fields
if (!debug_mode_q && ex_i.cause != riscv::DEBUG_REQUEST && ex_i.valid) begin
if ((CVA6Cfg.DebugEn && !debug_mode_q && ex_i.cause != riscv::DEBUG_REQUEST && ex_i.valid) || (!CVA6Cfg.DebugEn && ex_i.valid)) begin
// do not flush, flush is reserved for CSR writes with side effects
flush_o = 1'b0;
// figure out where to trap to
@ -1081,7 +1081,8 @@ module csr_regfile
)-1:0]]))) begin
// traps never transition from a more-privileged mode to a less privileged mode
// so if we are already in M mode, stay there
trap_to_priv_lvl = (priv_lvl_o == riscv::PRIV_LVL_M) ? riscv::PRIV_LVL_M : riscv::PRIV_LVL_S;
if (priv_lvl_o == riscv::PRIV_LVL_M) trap_to_priv_lvl = riscv::PRIV_LVL_M;
else trap_to_priv_lvl = riscv::PRIV_LVL_S;
end
// trap to supervisor mode
@ -1287,32 +1288,28 @@ module csr_regfile
CSR_SET: csr_wdata = csr_wdata_i | csr_rdata;
CSR_CLEAR: csr_wdata = (~csr_wdata_i) & csr_rdata;
CSR_READ: csr_we = 1'b0;
SRET: begin
if (CVA6Cfg.RVS) begin
// the return should not have any write or read side-effects
csr_we = 1'b0;
csr_read = 1'b0;
sret = 1'b1; // signal a return from supervisor mode
end
end
MRET: begin
// the return should not have any write or read side-effects
csr_we = 1'b0;
csr_read = 1'b0;
mret = 1'b1; // signal a return from machine mode
end
DRET: begin
if (CVA6Cfg.DebugEn) begin
default: begin
if (CVA6Cfg.RVS && csr_op_i == SRET) begin
// the return should not have any write or read side-effects
csr_we = 1'b0;
csr_read = 1'b0;
sret = 1'b1; // signal a return from supervisor mode
end else if (CVA6Cfg.DebugEn && csr_op_i == DRET) begin
// the return should not have any write or read side-effects
csr_we = 1'b0;
csr_read = 1'b0;
dret = 1'b1; // signal a return from debug mode
end else begin
csr_we = 1'b0;
csr_read = 1'b0;
end
end
default: begin
csr_we = 1'b0;
csr_read = 1'b0;
end
endcase
// if we are violating our privilges do not update the architectural state
if (privilege_violation) begin
@ -1349,13 +1346,13 @@ module csr_regfile
// check counter-enabled counter CSR accesses
// counter address range is C00 to C1F
if (csr_addr_i inside {[riscv::CSR_CYCLE : riscv::CSR_HPM_COUNTER_31]}) begin
unique case (priv_lvl_o)
riscv::PRIV_LVL_M: privilege_violation = 1'b0;
riscv::PRIV_LVL_S: if (CVA6Cfg.RVS) privilege_violation = ~mcounteren_q[csr_addr_i[4:0]];
riscv::PRIV_LVL_U:
if (CVA6Cfg.RVU)
privilege_violation = ~mcounteren_q[csr_addr_i[4:0]] & ~scounteren_q[csr_addr_i[4:0]];
endcase
if (priv_lvl_o == riscv::PRIV_LVL_M) begin
privilege_violation = 1'b0;
end else if (priv_lvl_o == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin
privilege_violation = ~mcounteren_q[csr_addr_i[4:0]];
end else if (priv_lvl_o == riscv::PRIV_LVL_U && CVA6Cfg.RVU) begin
privilege_violation = ~mcounteren_q[csr_addr_i[4:0]] & ~scounteren_q[csr_addr_i[4:0]];
end
end
end
end
@ -1394,7 +1391,7 @@ module csr_regfile
wfi_d = 1'b0;
// or alternatively if there is no exception pending and we are not in debug mode wait here
// for the interrupt
end else if (!debug_mode_q && csr_op_i == WFI && !ex_i.valid) begin
end else if (((CVA6Cfg.DebugEn && !debug_mode_q) && csr_op_i == WFI && !ex_i.valid) || (!CVA6Cfg.DebugEn && csr_op_i == WFI && !ex_i.valid)) begin
wfi_d = 1'b1;
end
end
@ -1418,7 +1415,7 @@ module csr_regfile
// privilege level we are jumping and whether the vectored mode is
// activated for _that_ privilege level.
if (ex_i.cause[riscv::XLEN-1] &&
((trap_to_priv_lvl == riscv::PRIV_LVL_M && mtvec_q[0])
((((CVA6Cfg.RVS || CVA6Cfg.RVU) && trap_to_priv_lvl == riscv::PRIV_LVL_M && mtvec_q[0]) || (!CVA6Cfg.RVS && !CVA6Cfg.RVU && mtvec_q[0]))
|| (CVA6Cfg.RVS && trap_to_priv_lvl == riscv::PRIV_LVL_S && stvec_q[0]))) begin
trap_vector_base_o[7:2] = ex_i.cause[5:0];
end