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Updated documentation with details on scoreboard
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Florian Zaruba
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3 changed files with 68 additions and 26 deletions
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@ -40,9 +40,9 @@ The instruction queue is part of the IF stage. Its purpose is to decouple the in
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| **Signal** | **Direction** | **Description** | **Category** |
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|---------------------|---------------|-------------------------------------------------------------------------------------------------|-----------------------------|
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| epc_i | Input | EPC from CSR registers, depending on the privilege level the epc points to a different address. | CSR Regs |
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| ecall_i | Input | Ecall request from WB | WB/Commit |
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| epc_wb_i | Input | EPC Writeback | WB/Commit |
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| epc_wb_valid_i | Input | EPC from WB is valid | WB/Commit |
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| ecall_i | Input | Ecall request from WB | Commit |
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| epc_commit_i | Input | EPC Commit | Commit |
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| epc_commit_valid_i | Input | EPC from Commit is valid | Commit |
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| flush_s1_i | Input | Flush PC Gen stage | Control |
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| flush_s2_i | Input | Flush fetch stage | Control |
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| bp_pc_i | Input | Branch prediction PC, from EX stage | EX -- Update BP/take branch |
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@ -112,9 +112,38 @@ The field functional unit can be of the following types:
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#### Interface
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| **Signal** | **Direction** | **Description** | **Category** |
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|-----------------------|---------------|----------------------------------------------------------------------------------|------------------------|
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| flush_i | Input | Flush Scoreboard | Control |
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| full_o | Output | Scoreboard is full | Control |
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| rd_clobber_o | Output | Used destination registers, includes the FU that is going to write this register | To issue/read operands |
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| rs1_i | Input | Check the scoreboard for a valid register at that address | From read operands |
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| rs2_i | Input | Check the scoreboard for a valid register at that address | From read operands |
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| rs1_o | Output | Data for rs1 | To read operands |
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| rs1_valid_o | Output | Data for rs1 is valid | To read operands |
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| rs2_o | Output | Data for rs2 | To read operands |
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| rs2_valid_o | Output | Data for rs2 is valid | To read operands |
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| commit_instr_o | Output | Instruction to commit | To WB stage |
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| commit_instr_valid_o | Output | Instruction to commit is valid | To WB stage |
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| decoded_instr_i | Input | Decoded instruction entering scoreboard | From ID |
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| decoded_instr_valid_i | Input | Decoded instruction entering scoreboard is valid | From ID |
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| issue_instr_o | Output | Instruction to issue stage | To Issue |
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| issue_instr_valid_o | Output | Instruction to issue stage is valid | To Issue |
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### Issue
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The issue stage itself is not a real stage in the sense that it is pipelined, it is still part of the decode stage. The purpose of the issue stage is to find out whether we can issue the current top of the scoreboard to one of the functional units. It therefore takes into account whether the any other FU has or is going to write the destination register of the current instruction and whether or not the necessary functional unit is currently busy. If the FU is not busy and there are no dependencies we can issue the instruction to the execute stage.
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### Compressed Decoder
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The compressed decoders purpose is to expand a compressed instruction (16 bit) to its 32 bit equivalent.
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### Interface
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| **Signal** | **Direction** | **Description** | **Category** |
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|-------------------|---------------|---------------------------------------------------------------------------------------------------------|---------------------|
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| flush_i | Input | Flush the scoreboard, there was an architectural state change that needs to invalidate the whole buffer | From controller |
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| flush_i | Input | Flush ID, there was an architectural state change that needs to invalidate the whole buffer | From controller |
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| ready_o | Output | The scoreboard is ready to accept new instructions. | To ID |
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| valid_i | Input | The instruction is valid | From ID |
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| imm_i | Input | Immediate field in | From ID |
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@ -125,7 +154,7 @@ The field functional unit can be of the following types:
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| op_i | Input | Operation to perform | From ID |
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| exception_i | Input | Exception | From ID |
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| exception_valid_i | Input | Exception is valid | From ID |
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| epc_i | Input | Exception pointer | From ID |
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| epc_i | Input | Exception PC | From ID |
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| FU_ALU_o | Output | Signals to ALU e.g.: operation to perform etc. | To ALU |
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| FU_ALU_i | Input | Signals from ALU e.g.: finished operation, result | From ALU |
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| FU_MULT_o | Output | Signals to Multiplier | To Mult |
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@ -134,30 +163,41 @@ The field functional unit can be of the following types:
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| FU_LSU_i | Input | Signals from LSU | From LSU |
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| Regfile | Inout | Signals from and to register file | From/To regfile |
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| CSR | Inout | Signals from and to CSR register file | From/To CSR regfile |
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| | | | |
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### Compressed Decoder
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The compressed decoders purpose is to expand a compressed instruction (16 bit) to its 32 bit equivalent.
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### Interface
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| **Signal** | **Direction** | **Description** | **Category** |
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| ---------- | ------------- | ---------------------- | ------------ |
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| flush_i | Input | EPC from CSR registers | CSR Regs |
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## Execute Stage (EX)
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### Read Operands
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The read operands stage is still part of the scoreboard but conceptually lies at the boundary between ID and EX. The operands where read in the previous cycle but we can still use forwarding to get the source operands from either:
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1. Register file
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2. Scoreboard
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3. Functional Unit (Forwarding)
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4. Immediate field
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The scoreboard and forwarding are mutually exclusive. The selection logic is a classical priority selection giving precedence to results form the scoreboard/FU over the register file.
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### Interface
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| **Signal** | **Direction** | **Description** | **Category** |
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| ---------- | ------------- | ---------------------- | ------------ |
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| flush_i | Input | EPC from CSR registers | CSR Regs |
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| **Signal** | **Direction** | **Description** | **Category** |
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|------------|---------------|---------------------------------------------------|--------------|
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| flush_i | Input | Flush ex stage | CSR Regs |
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| FU_ALU_i | Input | Signals to ALU e.g.: operation to perform etc. | To ALU |
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| FU_ALU_o | Output | Signals from ALU e.g.: finished operation, result | From ALU |
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| FU_MULT_i | Input | Signals to Multiplier | To Mult |
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| FU_MULT_o | Output | Signals from Multiplier | From Mult |
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| FU_LSU_i | Input | Signals to LSU | To LSU |
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| FU_LSU_o | Output | Signals from LSU | From LSU |
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## Writeback Stage (WB)
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### Write-Back
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The writeback stage is the single commit point in the whole architecture. Everything prior to this stage was just computed in a temporary fashion. This is also the only point where an exception can occur.
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The write-back stage writes the results from the FU back to the scoreboard. They are committed in-order in the next stage.
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## Commit Stage (Commit)
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The commit stage is the single commit point in the whole architecture. Everything prior to this stage was just computed in a temporary fashion. This is also the only point where an exception can occur.
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The commit stage is entirely decoupled from the rest of the pipeline. It has access to the scoreboard which issues finished instructions in-order to the commit stage.
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### CSR Register File
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@ -179,8 +219,6 @@ The CSR register file contains all registers which are not directly related to a
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| tlbflush | ? | Flush TLB |
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| cflush | ? | Flush Cache |
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And the following machine mode CSR registers:
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| **Register** | **Address** | **Description** |
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@ -207,9 +245,13 @@ We need to be careful when altering some of the register. Some of those register
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### Interface
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| **Signal** | **Direction** | **Description** | **Category** |
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| ---------- | ------------- | ---------------------- | ------------ |
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| flush_i | Input | EPC from CSR registers | CSR Regs |
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| **Signal** | **Direction** | **Description** | **Category** |
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|----------------|---------------|----------------------------------------------|--------------------------|
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| flush_i | Input | Flush WB stage | CSR Regs |
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| instr_commit_i | Input | Instruction to commit | From Scoreboard/ID Stage |
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| CSR Regs | Output | Interface to CSR registers | To CSR Registers |
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| Regfile | Output | Interface to the architectural register file | To regfile |
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| Exception | Output | Exception occured | To PC gen |
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## MMU
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