mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-20 12:17:19 -04:00
Verible reformat (#2014)
This commit is contained in:
JeanRochCoulon
GitHub
parent
ec44b22920
commit
80e6d7cffc
18 changed files with 185 additions and 229 deletions
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@ -434,7 +434,7 @@ module cache_ctrl
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end
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end
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default:;
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default: ;
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endcase
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@ -161,8 +161,8 @@ module miss_handler
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logic [ 63:0] amo_operand_b;
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// 32b request
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logic [31:0] halfword;
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logic [$clog2(CVA6Cfg.DCACHE_LINE_WIDTH)-1:0] cl_offset;
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logic [ 31:0] halfword;
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logic [ $clog2(CVA6Cfg.DCACHE_LINE_WIDTH)-1:0] cl_offset;
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// ------------------------------
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// Cache Management
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@ -225,8 +225,8 @@ module miss_handler
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amo_resp_o.result = '0;
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amo_operand_b = '0;
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halfword = '0;
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cl_offset = '0;
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halfword = '0;
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cl_offset = '0;
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case (state_q)
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@ -496,7 +496,7 @@ module miss_handler
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end
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end
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default:;
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default: ;
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endcase
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end
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50
core/cva6.sv
50
core/cva6.sv
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@ -1513,31 +1513,31 @@ module cva6
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.INTERRUPTS(INTERRUPTS)
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) instr_tracer_i (
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// .tracer_if(tracer_if),
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.pck (clk_i),
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.rstn (rst_ni),
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.flush_unissued (flush_unissued_instr_ctrl_id),
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.flush_all (flush_ctrl_ex),
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.instruction (id_stage_i.fetch_entry_i.instruction),
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.fetch_valid (id_stage_i.fetch_entry_valid_i),
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.fetch_ack (id_stage_i.fetch_entry_ready_o),
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.issue_ack (issue_stage_i.i_scoreboard.issue_ack_i),
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.issue_sbe (issue_stage_i.i_scoreboard.issue_instr_o),
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.waddr (waddr_commit_id),
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.wdata (wdata_commit_id),
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.we_gpr (we_gpr_commit_id),
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.we_fpr (we_fpr_commit_id),
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.commit_instr (commit_instr_id_commit),
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.commit_ack (commit_ack),
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.st_valid (ex_stage_i.lsu_i.i_store_unit.store_buffer_i.valid_i),
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.st_paddr (ex_stage_i.lsu_i.i_store_unit.store_buffer_i.paddr_i),
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.ld_valid (ex_stage_i.lsu_i.i_load_unit.req_port_o.tag_valid),
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.ld_kill (ex_stage_i.lsu_i.i_load_unit.req_port_o.kill_req),
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.ld_paddr (ex_stage_i.lsu_i.i_load_unit.paddr_i),
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.resolve_branch (resolved_branch),
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.commit_exception (commit_stage_i.exception_o),
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.priv_lvl (priv_lvl),
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.debug_mode (debug_mode),
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.hart_id_i (hart_id_i)
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.pck(clk_i),
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.rstn(rst_ni),
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.flush_unissued(flush_unissued_instr_ctrl_id),
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.flush_all(flush_ctrl_ex),
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.instruction(id_stage_i.fetch_entry_i.instruction),
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.fetch_valid(id_stage_i.fetch_entry_valid_i),
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.fetch_ack(id_stage_i.fetch_entry_ready_o),
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.issue_ack(issue_stage_i.i_scoreboard.issue_ack_i),
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.issue_sbe(issue_stage_i.i_scoreboard.issue_instr_o),
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.waddr(waddr_commit_id),
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.wdata(wdata_commit_id),
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.we_gpr(we_gpr_commit_id),
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.we_fpr(we_fpr_commit_id),
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.commit_instr(commit_instr_id_commit),
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.commit_ack(commit_ack),
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.st_valid(ex_stage_i.lsu_i.i_store_unit.store_buffer_i.valid_i),
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.st_paddr(ex_stage_i.lsu_i.i_store_unit.store_buffer_i.paddr_i),
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.ld_valid(ex_stage_i.lsu_i.i_load_unit.req_port_o.tag_valid),
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.ld_kill(ex_stage_i.lsu_i.i_load_unit.req_port_o.kill_req),
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.ld_paddr(ex_stage_i.lsu_i.i_load_unit.paddr_i),
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.resolve_branch(resolved_branch),
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.commit_exception(commit_stage_i.exception_o),
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.priv_lvl(priv_lvl),
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.debug_mode(debug_mode),
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.hart_id_i(hart_id_i)
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);
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// mock tracer for Verilator, to be used with spike-dasm
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@ -11,182 +11,178 @@
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// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
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module cva6_fifo_v3 #(
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parameter bit FALL_THROUGH = 1'b0, // fifo is in fall-through mode
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parameter int unsigned DATA_WIDTH = 32, // default data width if the fifo is of type logic
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parameter int unsigned DEPTH = 8, // depth can be arbitrary from 0 to 2**32
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parameter type dtype = logic [DATA_WIDTH-1:0],
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parameter bit FPGA_EN = 1'b0,
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parameter bit FALL_THROUGH = 1'b0, // fifo is in fall-through mode
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parameter int unsigned DATA_WIDTH = 32, // default data width if the fifo is of type logic
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parameter int unsigned DEPTH = 8, // depth can be arbitrary from 0 to 2**32
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parameter type dtype = logic [DATA_WIDTH-1:0],
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parameter bit FPGA_EN = 1'b0,
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// DO NOT OVERWRITE THIS PARAMETER
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parameter int unsigned ADDR_DEPTH = (DEPTH > 1) ? $clog2(DEPTH) : 1
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)(
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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input logic flush_i, // flush the queue
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input logic testmode_i, // test_mode to bypass clock gating
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parameter int unsigned ADDR_DEPTH = (DEPTH > 1) ? $clog2(DEPTH) : 1
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) (
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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input logic flush_i, // flush the queue
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input logic testmode_i, // test_mode to bypass clock gating
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// status flags
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output logic full_o, // queue is full
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output logic empty_o, // queue is empty
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output logic [ADDR_DEPTH-1:0] usage_o, // fill pointer
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output logic full_o, // queue is full
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output logic empty_o, // queue is empty
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output logic [ADDR_DEPTH-1:0] usage_o, // fill pointer
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// as long as the queue is not full we can push new data
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input dtype data_i, // data to push into the queue
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input logic push_i, // data is valid and can be pushed to the queue
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input dtype data_i, // data to push into the queue
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input logic push_i, // data is valid and can be pushed to the queue
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// as long as the queue is not empty we can pop new elements
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output dtype data_o, // output data
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input logic pop_i // pop head from queue
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output dtype data_o, // output data
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input logic pop_i // pop head from queue
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);
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// local parameter
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// FIFO depth - handle the case of pass-through, synthesizer will do constant propagation
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localparam int unsigned FifoDepth = (DEPTH > 0) ? DEPTH : 1;
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// clock gating control
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logic gate_clock;
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// pointer to the read and write section of the queue
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logic [ADDR_DEPTH - 1:0] read_pointer_n, read_pointer_q, write_pointer_n, write_pointer_q;
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// keep a counter to keep track of the current queue status
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// this integer will be truncated by the synthesis tool
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logic [ADDR_DEPTH:0] status_cnt_n, status_cnt_q;
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// actual memory
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dtype [FifoDepth - 1:0] mem_n, mem_q;
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// local parameter
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// FIFO depth - handle the case of pass-through, synthesizer will do constant propagation
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localparam int unsigned FifoDepth = (DEPTH > 0) ? DEPTH : 1;
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// clock gating control
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logic gate_clock;
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// pointer to the read and write section of the queue
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logic [ADDR_DEPTH - 1:0] read_pointer_n, read_pointer_q, write_pointer_n, write_pointer_q;
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// keep a counter to keep track of the current queue status
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// this integer will be truncated by the synthesis tool
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logic [ADDR_DEPTH:0] status_cnt_n, status_cnt_q;
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// actual memory
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dtype [FifoDepth - 1:0] mem_n, mem_q;
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// fifo ram signals for fpga target
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logic fifo_ram_we;
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logic [ADDR_DEPTH-1:0] fifo_ram_read_address;
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logic [ADDR_DEPTH-1:0] fifo_ram_write_address;
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logic [$bits(dtype)-1:0] fifo_ram_wdata;
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logic [$bits(dtype)-1:0] fifo_ram_rdata;
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// fifo ram signals for fpga target
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logic fifo_ram_we;
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logic [ADDR_DEPTH-1:0] fifo_ram_read_address;
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logic [ADDR_DEPTH-1:0] fifo_ram_write_address;
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logic [$bits(dtype)-1:0] fifo_ram_wdata;
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logic [$bits(dtype)-1:0] fifo_ram_rdata;
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assign usage_o = status_cnt_q[ADDR_DEPTH-1:0];
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assign usage_o = status_cnt_q[ADDR_DEPTH-1:0];
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if (DEPTH == 0) begin : gen_pass_through
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assign empty_o = ~push_i;
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assign full_o = ~pop_i;
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end else begin : gen_fifo
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assign full_o = (status_cnt_q == FifoDepth[ADDR_DEPTH:0]);
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assign empty_o = (status_cnt_q == 0) & ~(FALL_THROUGH & push_i);
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if (DEPTH == 0) begin : gen_pass_through
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assign empty_o = ~push_i;
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assign full_o = ~pop_i;
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end else begin : gen_fifo
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assign full_o = (status_cnt_q == FifoDepth[ADDR_DEPTH:0]);
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assign empty_o = (status_cnt_q == 0) & ~(FALL_THROUGH & push_i);
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end
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// status flags
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// read and write queue logic
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always_comb begin : read_write_comb
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// default assignment
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read_pointer_n = read_pointer_q;
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write_pointer_n = write_pointer_q;
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status_cnt_n = status_cnt_q;
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if (FPGA_EN) begin
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fifo_ram_we = '0;
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fifo_ram_read_address = read_pointer_q;
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fifo_ram_write_address = '0;
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fifo_ram_wdata = '0;
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data_o = (DEPTH == 0) ? data_i : fifo_ram_rdata;
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end else begin
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data_o = (DEPTH == 0) ? data_i : mem_q[read_pointer_q];
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mem_n = mem_q;
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gate_clock = 1'b1;
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end
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// status flags
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// read and write queue logic
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always_comb begin : read_write_comb
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// default assignment
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read_pointer_n = read_pointer_q;
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// push a new element to the queue
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if (push_i && ~full_o) begin
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if (FPGA_EN) begin
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fifo_ram_we = 1'b1;
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fifo_ram_write_address = write_pointer_q;
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fifo_ram_wdata = data_i;
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end else begin
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// push the data onto the queue
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mem_n[write_pointer_q] = data_i;
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// un-gate the clock, we want to write something
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gate_clock = 1'b0;
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end
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// increment the write counter
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if (write_pointer_q == FifoDepth[ADDR_DEPTH-1:0] - 1) write_pointer_n = '0;
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else write_pointer_n = write_pointer_q + 1;
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// increment the overall counter
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status_cnt_n = status_cnt_q + 1;
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end
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if (pop_i && ~empty_o) begin
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// read from the queue is a default assignment
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// but increment the read pointer...
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if (read_pointer_n == FifoDepth[ADDR_DEPTH-1:0] - 1) read_pointer_n = '0;
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else read_pointer_n = read_pointer_q + 1;
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// ... and decrement the overall count
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status_cnt_n = status_cnt_q - 1;
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end
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// keep the count pointer stable if we push and pop at the same time
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if (push_i && pop_i && ~full_o && ~empty_o) status_cnt_n = status_cnt_q;
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// FIFO is in pass through mode -> do not change the pointers
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if (FALL_THROUGH && (status_cnt_q == 0) && push_i) begin
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data_o = data_i;
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if (pop_i) begin
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status_cnt_n = status_cnt_q;
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read_pointer_n = read_pointer_q;
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write_pointer_n = write_pointer_q;
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status_cnt_n = status_cnt_q;
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if (FPGA_EN) begin
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fifo_ram_we = '0;
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fifo_ram_read_address = read_pointer_q;
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fifo_ram_write_address = '0;
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fifo_ram_wdata = '0;
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data_o = (DEPTH == 0) ? data_i : fifo_ram_rdata;
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end else begin
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data_o = (DEPTH == 0) ? data_i : mem_q[read_pointer_q];
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mem_n = mem_q;
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gate_clock = 1'b1;
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end
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// push a new element to the queue
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if (push_i && ~full_o) begin
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if (FPGA_EN) begin
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fifo_ram_we = 1'b1;
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fifo_ram_write_address = write_pointer_q;
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fifo_ram_wdata = data_i;
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end else begin
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// push the data onto the queue
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mem_n[write_pointer_q] = data_i;
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// un-gate the clock, we want to write something
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gate_clock = 1'b0;
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end
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// increment the write counter
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if (write_pointer_q == FifoDepth[ADDR_DEPTH-1:0] - 1)
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write_pointer_n = '0;
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else
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write_pointer_n = write_pointer_q + 1;
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// increment the overall counter
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status_cnt_n = status_cnt_q + 1;
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end
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if (pop_i && ~empty_o) begin
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// read from the queue is a default assignment
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// but increment the read pointer...
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if (read_pointer_n == FifoDepth[ADDR_DEPTH-1:0] - 1)
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read_pointer_n = '0;
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else
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read_pointer_n = read_pointer_q + 1;
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// ... and decrement the overall count
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status_cnt_n = status_cnt_q - 1;
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end
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// keep the count pointer stable if we push and pop at the same time
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if (push_i && pop_i && ~full_o && ~empty_o)
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status_cnt_n = status_cnt_q;
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// FIFO is in pass through mode -> do not change the pointers
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if (FALL_THROUGH && (status_cnt_q == 0) && push_i) begin
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data_o = data_i;
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if (pop_i) begin
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status_cnt_n = status_cnt_q;
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read_pointer_n = read_pointer_q;
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write_pointer_n = write_pointer_q;
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end
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end
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end
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end
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end
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// sequential process
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// sequential process
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (~rst_ni) begin
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read_pointer_q <= '0;
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write_pointer_q <= '0;
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status_cnt_q <= '0;
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end else begin
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if (flush_i) begin
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read_pointer_q <= '0;
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write_pointer_q <= '0;
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status_cnt_q <= '0;
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end else begin
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read_pointer_q <= read_pointer_n;
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write_pointer_q <= write_pointer_n;
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status_cnt_q <= status_cnt_n;
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end
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end
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end
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if (FPGA_EN) begin : gen_fpga_queue
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AsyncDpRam #(
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.ADDR_WIDTH(ADDR_DEPTH),
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.DATA_DEPTH(DEPTH),
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.DATA_WIDTH($bits(dtype))
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) fifo_ram (
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.Clk_CI (clk_i),
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.WrEn_SI (fifo_ram_we),
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.RdAddr_DI(fifo_ram_read_address),
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.WrAddr_DI(fifo_ram_write_address),
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.WrData_DI(fifo_ram_wdata),
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.RdData_DO(fifo_ram_rdata)
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);
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end else begin : gen_asic_queue
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if(~rst_ni) begin
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read_pointer_q <= '0;
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write_pointer_q <= '0;
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status_cnt_q <= '0;
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end else begin
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if (flush_i) begin
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read_pointer_q <= '0;
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write_pointer_q <= '0;
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status_cnt_q <= '0;
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end else begin
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read_pointer_q <= read_pointer_n;
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write_pointer_q <= write_pointer_n;
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status_cnt_q <= status_cnt_n;
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end
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end
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if (~rst_ni) begin
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mem_q <= '0;
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end else if (!gate_clock) begin
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mem_q <= mem_n;
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end
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end
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end
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if (FPGA_EN) begin : gen_fpga_queue
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AsyncDpRam #(
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.ADDR_WIDTH (ADDR_DEPTH),
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.DATA_DEPTH (DEPTH),
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.DATA_WIDTH ($bits(dtype))
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) fifo_ram (
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.Clk_CI ( clk_i ),
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.WrEn_SI ( fifo_ram_we ),
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.RdAddr_DI ( fifo_ram_read_address ),
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.WrAddr_DI ( fifo_ram_write_address ),
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.WrData_DI ( fifo_ram_wdata ),
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.RdData_DO ( fifo_ram_rdata )
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);
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end else begin : gen_asic_queue
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if(~rst_ni) begin
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mem_q <= '0;
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end else if (!gate_clock) begin
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mem_q <= mem_n;
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end
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end
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end
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// pragma translate_off
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// pragma translate_off
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`ifndef VERILATOR
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initial begin
|
||||
assert (DEPTH > 0) else $error("DEPTH must be greater than 0.");
|
||||
end
|
||||
initial begin
|
||||
assert (DEPTH > 0)
|
||||
else $error("DEPTH must be greater than 0.");
|
||||
end
|
||||
|
||||
full_write : assert property(
|
||||
@(posedge clk_i) disable iff (~rst_ni) (full_o |-> ~push_i))
|
||||
else $fatal (1, "Trying to push new data although the FIFO is full.");
|
||||
full_write :
|
||||
assert property (@(posedge clk_i) disable iff (~rst_ni) (full_o |-> ~push_i))
|
||||
else $fatal(1, "Trying to push new data although the FIFO is full.");
|
||||
|
||||
empty_read : assert property(
|
||||
@(posedge clk_i) disable iff (~rst_ni) (empty_o |-> ~pop_i))
|
||||
else $fatal (1, "Trying to pop data although the FIFO is empty.");
|
||||
empty_read :
|
||||
assert property (@(posedge clk_i) disable iff (~rst_ni) (empty_o |-> ~pop_i))
|
||||
else $fatal(1, "Trying to pop data although the FIFO is empty.");
|
||||
`endif
|
||||
// pragma translate_on
|
||||
// pragma translate_on
|
||||
|
||||
endmodule // fifo_v3
|
||||
endmodule // fifo_v3
|
||||
|
|
|
|||
|
|
@ -116,15 +116,12 @@ package cva6_config_pkg;
|
|||
PMPAddrRstVal: {16{64'h0}},
|
||||
PMPEntryReadOnly: 16'd0,
|
||||
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
|
||||
// idempotent region
|
||||
NrNonIdempotentRules: unsigned'(2),
|
||||
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
|
||||
NonIdempotentLength: 1024'({64'b0, 64'b0}),
|
||||
NrExecuteRegionRules: unsigned'(3),
|
||||
// DRAM, Boot ROM, Debug Module
|
||||
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
|
||||
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
|
||||
// cached region
|
||||
NrCachedRegionRules: unsigned'(1),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
|
|
|
|||
|
|
@ -115,15 +115,12 @@ package cva6_config_pkg;
|
|||
PMPAddrRstVal: {16{64'h0}},
|
||||
PMPEntryReadOnly: 16'd0,
|
||||
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
|
||||
// idempotent region
|
||||
NrNonIdempotentRules: unsigned'(2),
|
||||
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
|
||||
NonIdempotentLength: 1024'({64'b0, 64'b0}),
|
||||
NrExecuteRegionRules: unsigned'(3),
|
||||
// DRAM, Boot ROM, Debug Module
|
||||
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
|
||||
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
|
||||
// cached region
|
||||
NrCachedRegionRules: unsigned'(1),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
|
|
|
|||
|
|
@ -116,15 +116,12 @@ package cva6_config_pkg;
|
|||
PMPAddrRstVal: {16{64'h0}},
|
||||
PMPEntryReadOnly: 16'd0,
|
||||
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
|
||||
// idempotent region
|
||||
NrNonIdempotentRules: unsigned'(2),
|
||||
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
|
||||
NonIdempotentLength: 1024'({64'b0, 64'b0}),
|
||||
NrExecuteRegionRules: unsigned'(3),
|
||||
// DRAM, Boot ROM, Debug Module
|
||||
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
|
||||
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
|
||||
// cached region
|
||||
NrCachedRegionRules: unsigned'(1),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
|
|
|
|||
|
|
@ -120,7 +120,6 @@ package cva6_config_pkg;
|
|||
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
|
||||
NonIdempotentLength: 1024'({64'b0, 64'b0}),
|
||||
NrExecuteRegionRules: unsigned'(3),
|
||||
// DRAM, Boot ROM, Debug Module
|
||||
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
|
||||
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
|
||||
NrCachedRegionRules: unsigned'(1),
|
||||
|
|
|
|||
|
|
@ -116,15 +116,12 @@ package cva6_config_pkg;
|
|||
PMPAddrRstVal: {16{64'h0}},
|
||||
PMPEntryReadOnly: 16'd0,
|
||||
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
|
||||
// idempotent region
|
||||
NrNonIdempotentRules: unsigned'(2),
|
||||
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
|
||||
NonIdempotentLength: 1024'({64'b0, 64'b0}),
|
||||
NrExecuteRegionRules: unsigned'(3),
|
||||
// DRAM, Boot ROM, Debug Module
|
||||
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
|
||||
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
|
||||
// cached region
|
||||
NrCachedRegionRules: unsigned'(1),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
|
|
|
|||
|
|
@ -116,15 +116,12 @@ package cva6_config_pkg;
|
|||
PMPAddrRstVal: {16{64'h0}},
|
||||
PMPEntryReadOnly: 16'd0,
|
||||
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
|
||||
// idempotent region
|
||||
NrNonIdempotentRules: unsigned'(2),
|
||||
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
|
||||
NonIdempotentLength: 1024'({64'b0, 64'b0}),
|
||||
NrExecuteRegionRules: unsigned'(3),
|
||||
// DRAM, Boot ROM, Debug Module
|
||||
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
|
||||
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
|
||||
// cached region
|
||||
NrCachedRegionRules: unsigned'(1),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
|
|
|
|||
|
|
@ -116,15 +116,12 @@ package cva6_config_pkg;
|
|||
PMPAddrRstVal: {16{64'h0}},
|
||||
PMPEntryReadOnly: 16'd0,
|
||||
NOCType: config_pkg::NOC_TYPE_L15_BIG_ENDIAN,
|
||||
// idempotent region
|
||||
NrNonIdempotentRules: unsigned'(2),
|
||||
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
|
||||
NonIdempotentLength: 1024'({64'b0, 64'b0}),
|
||||
NrExecuteRegionRules: unsigned'(3),
|
||||
// DRAM, Boot ROM, Debug Module
|
||||
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
|
||||
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
|
||||
// cached region
|
||||
NrCachedRegionRules: unsigned'(1),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
|
|
|
|||
|
|
@ -116,15 +116,12 @@ package cva6_config_pkg;
|
|||
PMPAddrRstVal: {16{64'h0}},
|
||||
PMPEntryReadOnly: 16'd0,
|
||||
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
|
||||
// idempotent region
|
||||
NrNonIdempotentRules: unsigned'(2),
|
||||
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
|
||||
NonIdempotentLength: 1024'({64'b0, 64'b0}),
|
||||
NrExecuteRegionRules: unsigned'(3),
|
||||
// DRAM, Boot ROM, Debug Module
|
||||
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
|
||||
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
|
||||
// cached region
|
||||
NrCachedRegionRules: unsigned'(1),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
|
|
|
|||
|
|
@ -123,15 +123,12 @@ package cva6_config_pkg;
|
|||
PMPAddrRstVal: {16{64'h0}},
|
||||
PMPEntryReadOnly: 16'd0,
|
||||
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
|
||||
// idempotent region
|
||||
NrNonIdempotentRules: unsigned'(2),
|
||||
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
|
||||
NonIdempotentLength: 1024'({64'b0, 64'b0}),
|
||||
NrExecuteRegionRules: unsigned'(3),
|
||||
// DRAM, Boot ROM, Debug Module
|
||||
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
|
||||
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
|
||||
// cached region
|
||||
NrCachedRegionRules: unsigned'(1),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
|
|
|
|||
|
|
@ -116,15 +116,12 @@ package cva6_config_pkg;
|
|||
PMPAddrRstVal: {16{64'h0}},
|
||||
PMPEntryReadOnly: 16'd0,
|
||||
NOCType: config_pkg::NOC_TYPE_L15_BIG_ENDIAN,
|
||||
// idempotent region
|
||||
NrNonIdempotentRules: unsigned'(2),
|
||||
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
|
||||
NonIdempotentLength: 1024'({64'b0, 64'b0}),
|
||||
NrExecuteRegionRules: unsigned'(3),
|
||||
// DRAM, Boot ROM, Debug Module
|
||||
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
|
||||
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
|
||||
// cached region
|
||||
NrCachedRegionRules: unsigned'(1),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
|
|
|
|||
|
|
@ -116,15 +116,12 @@ package cva6_config_pkg;
|
|||
PMPAddrRstVal: {16{64'h0}},
|
||||
PMPEntryReadOnly: 16'd0,
|
||||
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
|
||||
// idempotent region
|
||||
NrNonIdempotentRules: unsigned'(2),
|
||||
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
|
||||
NonIdempotentLength: 1024'({64'b0, 64'b0}),
|
||||
NrExecuteRegionRules: unsigned'(3),
|
||||
// DRAM, Boot ROM, Debug Module
|
||||
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
|
||||
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
|
||||
// cached region
|
||||
NrCachedRegionRules: unsigned'(1),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
|
|
|
|||
|
|
@ -113,15 +113,12 @@ package cva6_config_pkg;
|
|||
PMPAddrRstVal: {16{64'h0}},
|
||||
PMPEntryReadOnly: 16'd0,
|
||||
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
|
||||
// idempotent region
|
||||
NrNonIdempotentRules: unsigned'(2),
|
||||
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
|
||||
NonIdempotentLength: 1024'({64'b0, 64'b0}),
|
||||
NrExecuteRegionRules: unsigned'(3),
|
||||
// DRAM, Boot ROM, Debug Module
|
||||
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
|
||||
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
|
||||
// cached region
|
||||
NrCachedRegionRules: unsigned'(1),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
|
|
|
|||
|
|
@ -113,15 +113,12 @@ package cva6_config_pkg;
|
|||
PMPAddrRstVal: {16{64'h0}},
|
||||
PMPEntryReadOnly: 16'd0,
|
||||
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
|
||||
// idempotent region
|
||||
NrNonIdempotentRules: unsigned'(2),
|
||||
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
|
||||
NonIdempotentLength: 1024'({64'b0, 64'b0}),
|
||||
NrExecuteRegionRules: unsigned'(3),
|
||||
// DRAM, Boot ROM, Debug Module
|
||||
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
|
||||
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
|
||||
// cached region
|
||||
NrCachedRegionRules: unsigned'(1),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
|
|
|
|||
|
|
@ -116,15 +116,12 @@ package cva6_config_pkg;
|
|||
PMPAddrRstVal: {16{64'h0}},
|
||||
PMPEntryReadOnly: 16'd0,
|
||||
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
|
||||
// idempotent region
|
||||
NrNonIdempotentRules: unsigned'(2),
|
||||
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
|
||||
NonIdempotentLength: 1024'({64'b0, 64'b0}),
|
||||
NrExecuteRegionRules: unsigned'(3),
|
||||
// DRAM, Boot ROM, Debug Module
|
||||
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
|
||||
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
|
||||
// cached region
|
||||
NrCachedRegionRules: unsigned'(1),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue