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Verible reformat (#2014)

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JeanRochCoulon 2024-04-08 11:26:08 +02:00 • committed by GitHub
parent ec44b22920
commit 80e6d7cffc
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18 changed files with 185 additions and 229 deletions
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2
core/cache_subsystem/cache_ctrl.sv
View file

@ -434,7 +434,7 @@ module cache_ctrl
end
end
default:;
default: ;
endcase

6
core/cache_subsystem/miss_handler.sv
View file

@ -161,8 +161,8 @@ module miss_handler
logic [ 63:0] amo_operand_b;
// 32b request
logic [31:0] halfword;
logic [$clog2(CVA6Cfg.DCACHE_LINE_WIDTH)-1:0] cl_offset;
logic [ 31:0] halfword;
logic [ $clog2(CVA6Cfg.DCACHE_LINE_WIDTH)-1:0] cl_offset;
// ------------------------------
// Cache Management
@ -496,7 +496,7 @@ module miss_handler
end
end
default:;
default: ;
endcase
end

50
core/cva6.sv
View file

@ -1513,31 +1513,31 @@ module cva6
.INTERRUPTS(INTERRUPTS)
) instr_tracer_i (
// .tracer_if(tracer_if),
.pck (clk_i),
.rstn (rst_ni),
.flush_unissued (flush_unissued_instr_ctrl_id),
.flush_all (flush_ctrl_ex),
.instruction (id_stage_i.fetch_entry_i.instruction),
.fetch_valid (id_stage_i.fetch_entry_valid_i),
.fetch_ack (id_stage_i.fetch_entry_ready_o),
.issue_ack (issue_stage_i.i_scoreboard.issue_ack_i),
.issue_sbe (issue_stage_i.i_scoreboard.issue_instr_o),
.waddr (waddr_commit_id),
.wdata (wdata_commit_id),
.we_gpr (we_gpr_commit_id),
.we_fpr (we_fpr_commit_id),
.commit_instr (commit_instr_id_commit),
.commit_ack (commit_ack),
.st_valid (ex_stage_i.lsu_i.i_store_unit.store_buffer_i.valid_i),
.st_paddr (ex_stage_i.lsu_i.i_store_unit.store_buffer_i.paddr_i),
.ld_valid (ex_stage_i.lsu_i.i_load_unit.req_port_o.tag_valid),
.ld_kill (ex_stage_i.lsu_i.i_load_unit.req_port_o.kill_req),
.ld_paddr (ex_stage_i.lsu_i.i_load_unit.paddr_i),
.resolve_branch (resolved_branch),
.commit_exception (commit_stage_i.exception_o),
.priv_lvl (priv_lvl),
.debug_mode (debug_mode),
.hart_id_i (hart_id_i)
.pck(clk_i),
.rstn(rst_ni),
.flush_unissued(flush_unissued_instr_ctrl_id),
.flush_all(flush_ctrl_ex),
.instruction(id_stage_i.fetch_entry_i.instruction),
.fetch_valid(id_stage_i.fetch_entry_valid_i),
.fetch_ack(id_stage_i.fetch_entry_ready_o),
.issue_ack(issue_stage_i.i_scoreboard.issue_ack_i),
.issue_sbe(issue_stage_i.i_scoreboard.issue_instr_o),
.waddr(waddr_commit_id),
.wdata(wdata_commit_id),
.we_gpr(we_gpr_commit_id),
.we_fpr(we_fpr_commit_id),
.commit_instr(commit_instr_id_commit),
.commit_ack(commit_ack),
.st_valid(ex_stage_i.lsu_i.i_store_unit.store_buffer_i.valid_i),
.st_paddr(ex_stage_i.lsu_i.i_store_unit.store_buffer_i.paddr_i),
.ld_valid(ex_stage_i.lsu_i.i_load_unit.req_port_o.tag_valid),
.ld_kill(ex_stage_i.lsu_i.i_load_unit.req_port_o.kill_req),
.ld_paddr(ex_stage_i.lsu_i.i_load_unit.paddr_i),
.resolve_branch(resolved_branch),
.commit_exception(commit_stage_i.exception_o),
.priv_lvl(priv_lvl),
.debug_mode(debug_mode),
.hart_id_i(hart_id_i)
);
// mock tracer for Verilator, to be used with spike-dasm

58
core/cva6_fifo_v3.sv
View file

@ -18,7 +18,7 @@ module cva6_fifo_v3 #(
parameter bit FPGA_EN = 1'b0,
// DO NOT OVERWRITE THIS PARAMETER
parameter int unsigned ADDR_DEPTH = (DEPTH > 1) ? $clog2(DEPTH) : 1
)(
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic flush_i, // flush the queue
@ -97,10 +97,8 @@ module cva6_fifo_v3 #(
end
// increment the write counter
if (write_pointer_q == FifoDepth[ADDR_DEPTH-1:0] - 1)
write_pointer_n = '0;
else
write_pointer_n = write_pointer_q + 1;
if (write_pointer_q == FifoDepth[ADDR_DEPTH-1:0] - 1) write_pointer_n = '0;
else write_pointer_n = write_pointer_q + 1;
// increment the overall counter
status_cnt_n = status_cnt_q + 1;
end
@ -108,17 +106,14 @@ module cva6_fifo_v3 #(
if (pop_i && ~empty_o) begin
// read from the queue is a default assignment
// but increment the read pointer...
if (read_pointer_n == FifoDepth[ADDR_DEPTH-1:0] - 1)
read_pointer_n = '0;
else
read_pointer_n = read_pointer_q + 1;
if (read_pointer_n == FifoDepth[ADDR_DEPTH-1:0] - 1) read_pointer_n = '0;
else read_pointer_n = read_pointer_q + 1;
// ... and decrement the overall count
status_cnt_n = status_cnt_q - 1;
end
// keep the count pointer stable if we push and pop at the same time
if (push_i && pop_i && ~full_o && ~empty_o)
status_cnt_n = status_cnt_q;
if (push_i && pop_i && ~full_o && ~empty_o) status_cnt_n = status_cnt_q;
// FIFO is in pass through mode -> do not change the pointers
if (FALL_THROUGH && (status_cnt_q == 0) && push_i) begin
@ -133,7 +128,7 @@ module cva6_fifo_v3 #(
// sequential process
always_ff @(posedge clk_i or negedge rst_ni) begin
if(~rst_ni) begin
if (~rst_ni) begin
read_pointer_q <= '0;
write_pointer_q <= '0;
status_cnt_q <= '0;
@ -152,20 +147,20 @@ module cva6_fifo_v3 #(
if (FPGA_EN) begin : gen_fpga_queue
AsyncDpRam #(
.ADDR_WIDTH (ADDR_DEPTH),
.DATA_DEPTH (DEPTH),
.DATA_WIDTH ($bits(dtype))
.ADDR_WIDTH(ADDR_DEPTH),
.DATA_DEPTH(DEPTH),
.DATA_WIDTH($bits(dtype))
) fifo_ram (
.Clk_CI ( clk_i ),
.WrEn_SI ( fifo_ram_we ),
.RdAddr_DI ( fifo_ram_read_address ),
.WrAddr_DI ( fifo_ram_write_address ),
.WrData_DI ( fifo_ram_wdata ),
.RdData_DO ( fifo_ram_rdata )
.Clk_CI (clk_i),
.WrEn_SI (fifo_ram_we),
.RdAddr_DI(fifo_ram_read_address),
.WrAddr_DI(fifo_ram_write_address),
.WrData_DI(fifo_ram_wdata),
.RdData_DO(fifo_ram_rdata)
);
end else begin : gen_asic_queue
always_ff @(posedge clk_i or negedge rst_ni) begin
if(~rst_ni) begin
if (~rst_ni) begin
mem_q <= '0;
end else if (!gate_clock) begin
mem_q <= mem_n;
@ -173,20 +168,21 @@ module cva6_fifo_v3 #(
end
end
// pragma translate_off
// pragma translate_off
`ifndef VERILATOR
initial begin
assert (DEPTH > 0) else $error("DEPTH must be greater than 0.");
assert (DEPTH > 0)
else $error("DEPTH must be greater than 0.");
end
full_write : assert property(
@(posedge clk_i) disable iff (~rst_ni) (full_o |-> ~push_i))
else $fatal (1, "Trying to push new data although the FIFO is full.");
full_write :
assert property (@(posedge clk_i) disable iff (~rst_ni) (full_o |-> ~push_i))
else $fatal(1, "Trying to push new data although the FIFO is full.");
empty_read : assert property(
@(posedge clk_i) disable iff (~rst_ni) (empty_o |-> ~pop_i))
else $fatal (1, "Trying to pop data although the FIFO is empty.");
empty_read :
assert property (@(posedge clk_i) disable iff (~rst_ni) (empty_o |-> ~pop_i))
else $fatal(1, "Trying to pop data although the FIFO is empty.");
`endif
// pragma translate_on
// pragma translate_on
endmodule // fifo_v3

3
core/include/cv32a60x_config_pkg.sv
View file

@ -116,15 +116,12 @@ package cva6_config_pkg;
PMPAddrRstVal: {16{64'h0}},
PMPEntryReadOnly: 16'd0,
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
// idempotent region
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000}),

3
core/include/cv32a6_embedded_config_pkg.sv
View file

@ -115,15 +115,12 @@ package cva6_config_pkg;
PMPAddrRstVal: {16{64'h0}},
PMPEntryReadOnly: 16'd0,
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
// idempotent region
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000}),

3
core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
View file

@ -116,15 +116,12 @@ package cva6_config_pkg;
PMPAddrRstVal: {16{64'h0}},
PMPEntryReadOnly: 16'd0,
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
// idempotent region
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000}),

1
core/include/cv32a6_imac_sv0_config_pkg.sv
View file

@ -120,7 +120,6 @@ package cva6_config_pkg;
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
NrCachedRegionRules: unsigned'(1),

3
core/include/cv32a6_imac_sv32_config_pkg.sv
View file

@ -116,15 +116,12 @@ package cva6_config_pkg;
PMPAddrRstVal: {16{64'h0}},
PMPEntryReadOnly: 16'd0,
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
// idempotent region
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000}),

3
core/include/cv32a6_imafc_sv32_config_pkg.sv
View file

@ -116,15 +116,12 @@ package cva6_config_pkg;
PMPAddrRstVal: {16{64'h0}},
PMPEntryReadOnly: 16'd0,
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
// idempotent region
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000}),

3
core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
View file

@ -116,15 +116,12 @@ package cva6_config_pkg;
PMPAddrRstVal: {16{64'h0}},
PMPEntryReadOnly: 16'd0,
NOCType: config_pkg::NOC_TYPE_L15_BIG_ENDIAN,
// idempotent region
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000}),

3
core/include/cv64a6_imafdc_sv39_config_pkg.sv
View file

@ -116,15 +116,12 @@ package cva6_config_pkg;
PMPAddrRstVal: {16{64'h0}},
PMPEntryReadOnly: 16'd0,
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
// idempotent region
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000}),

3
core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
View file

@ -123,15 +123,12 @@ package cva6_config_pkg;
PMPAddrRstVal: {16{64'h0}},
PMPEntryReadOnly: 16'd0,
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
// idempotent region
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000}),

3
core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
View file

@ -116,15 +116,12 @@ package cva6_config_pkg;
PMPAddrRstVal: {16{64'h0}},
PMPEntryReadOnly: 16'd0,
NOCType: config_pkg::NOC_TYPE_L15_BIG_ENDIAN,
// idempotent region
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000}),

3
core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
View file

@ -116,15 +116,12 @@ package cva6_config_pkg;
PMPAddrRstVal: {16{64'h0}},
PMPEntryReadOnly: 16'd0,
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
// idempotent region
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000}),

3
core/include/cv64a6_imafdch_sv39_config_pkg.sv
View file

@ -113,15 +113,12 @@ package cva6_config_pkg;
PMPAddrRstVal: {16{64'h0}},
PMPEntryReadOnly: 16'd0,
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
// idempotent region
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000}),

3
core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
View file

@ -113,15 +113,12 @@ package cva6_config_pkg;
PMPAddrRstVal: {16{64'h0}},
PMPEntryReadOnly: 16'd0,
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
// idempotent region
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000}),

3
core/include/cv64a6_imafdcv_sv39_config_pkg.sv
View file

@ -116,15 +116,12 @@ package cva6_config_pkg;
PMPAddrRstVal: {16{64'h0}},
PMPEntryReadOnly: 16'd0,
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
// idempotent region
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000}),