mirror of
https://github.com/openhwgroup/cva6.git
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Fixes and Update CVXIF non regression tests, regression and TB (#2424)
This commit is contained in:
Guillaume Chauvon
GitHub
parent
6269f72b63
commit
81671e39fa
12 changed files with 149 additions and 98 deletions
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@ -232,6 +232,24 @@ spyglass:
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- mv spyglass/sg_run_results/cva6_sg_reports/cva6_lint_lint_rtl artifacts/lint_reports
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- python3 .gitlab-ci/scripts/report_spyglass_lint.py spyglass/reference_summary.rpt artifacts/lint_reports/cva6_lint_lint_rtl/summary.rpt
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cvxif-regression:
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extends:
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- .synthesis_test
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variables:
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DASHBOARD_JOB_TITLE: "CVXIF non-regression test $DV_SIMULATORS"
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DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge most CoreV-X-Interface in testharness"
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DASHBOARD_SORT_INDEX: 5
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DASHBOARD_JOB_CATEGORY: "Basic"
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COLLECT_SIMU_LOGS: 1
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parallel:
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matrix:
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- DV_SIMULATORS:
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- "veri-testharness,spike"
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- "vcs-testharness,spike"
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script:
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- bash verif/regress/cvxif_verif_regression.sh
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- !reference [.simu_after_script]
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asic-synthesis:
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extends:
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- .synthesis_test
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@ -11,27 +11,28 @@ module copro_alu
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import cvxif_instr_pkg::*;
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#(
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parameter int unsigned NrRgprPorts = 2,
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parameter int unsigned XLEN = 32,
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parameter type hartid_t = logic,
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parameter type id_t = logic,
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parameter type registers_t = logic
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) (
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input logic clk_i,
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input logic rst_ni,
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input registers_t registers_i,
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input opcode_t opcode_i,
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input hartid_t hartid_i,
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input id_t id_i,
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input logic [ 4:0] rd_i,
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output logic [31:0] result_o, // TODO parametrize to 64 bits
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output hartid_t hartid_o,
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output id_t id_o,
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output logic [ 4:0] rd_o,
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output logic valid_o,
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output logic we_o
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input logic clk_i,
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input logic rst_ni,
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input registers_t registers_i,
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input opcode_t opcode_i,
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input hartid_t hartid_i,
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input id_t id_i,
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input logic [ 4:0] rd_i,
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output logic [XLEN-1:0] result_o,
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output hartid_t hartid_o,
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output id_t id_o,
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output logic [ 4:0] rd_o,
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output logic valid_o,
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output logic we_o
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);
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logic [31:0] result_n, result_q;
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logic [XLEN-1:0] result_n, result_q;
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hartid_t hartid_n, hartid_q;
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id_t id_n, id_q;
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logic valid_n, valid_q;
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@ -12,6 +12,7 @@ module cvxif_example_coprocessor
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#(
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// CVXIF Types
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parameter int unsigned NrRgprPorts = 2,
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parameter int unsigned XLEN = 32,
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parameter type readregflags_t = logic,
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parameter type writeregflags_t = logic,
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parameter type id_t = logic,
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@ -25,7 +26,7 @@ module cvxif_example_coprocessor
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parameter type x_result_t = logic,
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parameter type cvxif_req_t = logic,
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parameter type cvxif_resp_t = logic,
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localparam type registers_t = logic [NrRgprPorts-1:0][31:0]
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localparam type registers_t = logic [NrRgprPorts-1:0][XLEN-1:0]
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) (
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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@ -52,8 +53,8 @@ module cvxif_example_coprocessor
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hartid_t issue_hartid, hartid;
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id_t issue_id, id;
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logic [4:0] issue_rd, rd;
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logic [31:0] result;
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logic we;
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logic [XLEN-1:0] result;
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logic we;
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// Issue and Register interface
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// Mandatory when X_ISSUE_REGISTER_SPLIT = 0
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@ -117,6 +118,7 @@ module cvxif_example_coprocessor
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// Result interface
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copro_alu #(
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.NrRgprPorts(NrRgprPorts),
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.XLEN(XLEN),
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.hartid_t(hartid_t),
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.id_t(id_t),
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.registers_t(registers_t)
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@ -56,7 +56,7 @@ module cvxif_fu
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assign x_ready_o = 1'b1; // Readyness of cvxif_fu is determined in issue stage by CVXIF issue interface
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// Result signals
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assign x_valid_o = x_illegal_i ? 1'b1 : result_valid_i;
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assign x_valid_o = x_illegal_i && x_valid_i ? 1'b1 : result_valid_i;
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assign x_result_o = result_i.data;
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assign x_trans_id_o = x_illegal_i ? x_trans_id_i : result_i.id;
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assign x_we_o = result_i.we;
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@ -65,7 +65,7 @@ module cvxif_fu
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// Handling of illegal instruction exception
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always_comb begin
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x_exception_o = '0; // No exception in this interface
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if (x_illegal_i) begin
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if (x_illegal_i && x_valid_i) begin
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x_exception_o.valid = '1;
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x_exception_o.cause = riscv::ILLEGAL_INSTR;
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if (CVA6Cfg.TvalEn)
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@ -394,10 +394,10 @@ module issue_read_operands
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// check that all operands are available, otherwise stall
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// forward corresponding register
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always_comb begin : operands_available
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stall_raw = '{default: stall_i};
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stall_rs1 = '{default: stall_i};
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stall_rs2 = '{default: stall_i};
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stall_rs3 = '{default: stall_i};
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stall_raw = '{default: stall_i};
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stall_rs1 = '{default: stall_i};
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stall_rs2 = '{default: stall_i};
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stall_rs3 = '{default: stall_i};
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// operand forwarding signals
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forward_rs1 = '0;
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forward_rs2 = '0;
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@ -417,10 +417,7 @@ module issue_read_operands
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if (!issue_instr_i[i].use_zimm && ((CVA6Cfg.FpPresent && is_rs1_fpr(
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issue_instr_i[i].op
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)) ? rd_clobber_fpr_i[issue_instr_i[i].rs1] != NONE :
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rd_clobber_gpr_i[issue_instr_i[i].rs1] != NONE) ||
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((CVA6Cfg.CvxifEn && x_issue_valid_o &&
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x_issue_resp_i.accept && x_issue_resp_i.register_read[0]) &&
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rd_clobber_gpr_i[issue_instr_i[i].rs1] != NONE)) begin
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rd_clobber_gpr_i[issue_instr_i[i].rs1] != NONE)) begin
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// check if the clobbering instruction is not a CSR instruction, CSR instructions can only
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// be fetched through the register file since they can't be forwarded
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// if the operand is available, forward it. CSRs don't write to/from FPR
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@ -438,10 +435,7 @@ module issue_read_operands
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if (((CVA6Cfg.FpPresent && is_rs2_fpr(
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issue_instr_i[i].op
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)) ? rd_clobber_fpr_i[issue_instr_i[i].rs2] != NONE :
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rd_clobber_gpr_i[issue_instr_i[i].rs2] != NONE) ||
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((CVA6Cfg.CvxifEn &&
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x_issue_valid_o && x_issue_resp_i.accept && x_issue_resp_i.register_read[1]) &&
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rd_clobber_gpr_i[issue_instr_i[i].rs2] != NONE)) begin
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rd_clobber_gpr_i[issue_instr_i[i].rs2] != NONE)) begin
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// if the operand is available, forward it. CSRs don't write to/from FPR
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if (rs2_valid_i[i] && (CVA6Cfg.FpPresent && is_rs2_fpr(
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issue_instr_i[i].op
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@ -455,12 +449,9 @@ module issue_read_operands
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end
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// Only check clobbered gpr for OFFLOADED instruction
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if (((CVA6Cfg.FpPresent && is_imm_fpr(
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if ((CVA6Cfg.FpPresent && is_imm_fpr(
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issue_instr_i[i].op
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)) ? rd_clobber_fpr_i[issue_instr_i[i].result[REG_ADDR_SIZE-1:0]] != NONE : 0) ||
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((CVA6Cfg.CvxifEn && OPERANDS_PER_INSTR == 3 &&
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x_issue_valid_o && x_issue_resp_i.accept && x_issue_resp_i.register_read[2]) &&
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rd_clobber_gpr_i[issue_instr_i[i].result[REG_ADDR_SIZE-1:0]] != NONE)) begin
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)) ? rd_clobber_fpr_i[issue_instr_i[i].result[REG_ADDR_SIZE-1:0]] != NONE : 0) begin
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// if the operand is available, forward it. CSRs don't write to/from FPR so no need to check
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if (rs3_valid_i[i]) begin
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forward_rs3[i] = 1'b1;
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@ -470,6 +461,24 @@ module issue_read_operands
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end
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end
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end
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if (CVA6Cfg.CvxifEn) begin
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// Remove unecessary forward and stall in case source register is not needed by coprocessor.
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if (x_issue_valid_o && x_issue_resp_i.accept) begin
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if (~x_issue_resp_i.register_read[0]) begin
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forward_rs1[0] = 1'b0;
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stall_rs1[0] = 1'b0;
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end
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if (~x_issue_resp_i.register_read[1]) begin
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forward_rs2[0] = 1'b0;
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stall_rs2[0] = 1'b0;
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end
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if (OPERANDS_PER_INSTR == 3 && ~x_issue_resp_i.register_read[2]) begin
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forward_rs3[0] = 1'b0;
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stall_rs3[0] = 1'b0;
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end
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end
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stall_raw[0] = stall_rs1[0] || stall_rs2[0] || stall_rs3[0];
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end
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if (CVA6Cfg.SuperscalarEn) begin
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if (!issue_instr_i[1].use_zimm && (!CVA6Cfg.FpPresent || (is_rs1_fpr(
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@ -111,6 +111,7 @@ module ariane import ariane_pkg::*; #(
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if (CVA6Cfg.CvxifEn) begin : gen_example_coprocessor
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cvxif_example_coprocessor #(
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.NrRgprPorts (CVA6Cfg.NrRgprPorts),
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.XLEN (CVA6Cfg.XLEN),
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.readregflags_t (readregflags_t),
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.writeregflags_t (writeregflags_t),
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.id_t (id_t),
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@ -130,6 +131,13 @@ module ariane import ariane_pkg::*; #(
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.cvxif_req_i ( cvxif_req ),
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.cvxif_resp_o ( cvxif_resp )
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);
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end else begin
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always_comb begin
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cvxif_resp = '0;
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cvxif_resp.compressed_ready = 1'b1;
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cvxif_resp.issue_ready = 1'b1;
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cvxif_resp.register_ready = 1'b1;
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end
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end
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@ -4,7 +4,7 @@
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# This file has been generated by SpyGlass:
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# Report Name : summary
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# Report Created by: runner_riscv-public
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# Report Created on: Fri Jul 26 00:36:54 2024
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# Report Created on: Thu Aug 1 11:05:24 2024
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# Working Directory: /gitlab-runner/runner_riscv-public/builds/yD5zmwgi3/0/riscv-ci/cva6/spyglass
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# SpyGlass Version : SpyGlass_vS-2021.09-SP2-3
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# Policy Name : SpyGlass(SpyGlass_vS-2021.09-SP2-03)
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@ -17,9 +17,9 @@
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# starc(SpyGlass_vS-2021.09-SP2-03)
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# starc2005(SpyGlass_vS-2021.09-SP2-03)
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#
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# Total Number of Generated Messages : 1521
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# Total Number of Generated Messages : 1526
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# Number of Waived Messages : 2
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# Number of Reported Messages : 1519
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# Number of Reported Messages : 1524
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# Number of Overlimit Messages : 0
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#
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#
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@ -106,24 +106,24 @@ WARNING STARC05-2.1.3.1 2 Bit-width of function arguments must
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WARNING STARC05-2.1.4.5 1 Bit-wise operators must be used instead
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of logic operators in multi-bit
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operations.
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WARNING STARC05-2.1.5.3 1 Conditional expressions should evaluate
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WARNING STARC05-2.1.5.3 2 Conditional expressions should evaluate
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to a scalar.
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WARNING STARC05-2.2.3.3 14 Do not assign over the same signal in
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an always construct for sequential
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circuits
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WARNING W224 1 Multi-bit expression found when one-bit
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WARNING W224 2 Multi-bit expression found when one-bit
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expression expected
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WARNING W240 322 An input has been declared but is not
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WARNING W240 319 An input has been declared but is not
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read
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WARNING W263 4 A case expression width does not match
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case select expression width
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WARNING W287b 36 Output port of an instance is not
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connected
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WARNING W415a 537 Signal may be multiply assigned (beside
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WARNING W415a 544 Signal may be multiply assigned (beside
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initialization) in the same scope.
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WARNING W480 3 Loop index is not of type integer
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WARNING W486 2 Shift overflow - some bits may be lost
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WARNING W528 487 A signal or variable is set but never
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WARNING W528 486 A signal or variable is set but never
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read
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INFO W240 1 An input has been declared but is not
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read
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@ -11,7 +11,9 @@
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Custom Instruction to challenge CV-X-IF protocol
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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This section describes some custom instruction, for stress or challenge the CV-X-IF protocol for the 3 implemented interfaces, it's just to interact with the cvxif agent.
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All instructions use opcode `CUSTOM_3`(0x7b, 0b111_1011).
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Most instructions use opcode `CUSTOM_3`(0x7b, 0b111_1011).
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Except for 4 of them using opcode `MADD, MSUB, NMADD, NMSUB`
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- **CUS_NOP**: Custom No Operation
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**Format**: cus_nop -> |0000000000000000000000000|111_1011|
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@ -20,8 +22,6 @@ All instructions use opcode `CUSTOM_3`(0x7b, 0b111_1011).
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**Pseudocode**: cus_nop
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**Invalid values**: NONE
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- **CUS_ADD**: Custom Add
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**Format**: cus_add rd, rs1, rs2 -> |0000000|rs2|rs1|001|rd|111_1011|
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@ -30,8 +30,6 @@ All instructions use opcode `CUSTOM_3`(0x7b, 0b111_1011).
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**Pseudocode**: x[rd] = x[rs1] + x[rs2]
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**Invalid values**: NONE
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- **CUS_DOUBLE_RS1**: Custom Double RS1
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**Format**: cus_add rd, rs1, rs1 -> |0000001|rs2|rs1|001|rd|111_1011|
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@ -42,8 +40,6 @@ All instructions use opcode `CUSTOM_3`(0x7b, 0b111_1011).
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**Pseudocode**: x[rd] = x[rs1] + x[rs1]
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**Invalid values**: NONE
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- **CUS_DOUBLE_RS2**: Custom Double RS2
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**Format**: cus_add rd, rs2, rs2 -> |0000010|rs2|rs1|001|rd|111_1011|
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@ -54,8 +50,6 @@ All instructions use opcode `CUSTOM_3`(0x7b, 0b111_1011).
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**Pseudocode**: x[rd] = x[rs2] + x[rs2]
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**Invalid values**: NONE
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- **CUS_ADD_MULTI**: Custom Multicycle Add
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**Format**: addi rd, rs1, rs2 -> |0000011|rs2|rs1|001|rd|111_1011|
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@ -64,8 +58,6 @@ All instructions use opcode `CUSTOM_3`(0x7b, 0b111_1011).
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**Pseudocode**: x[rd] = x[rs1] + x[rs2]
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**Invalid values**: NONE
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- **CUS_ADD_RS3_MADD**: Custom Add with RS3 opcode == MADD
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**Format**: addi rd, rs1, rs2, rs3 -> |rs3|00|rs2|rs1|000|rd|100_0011|
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@ -74,8 +66,6 @@ All instructions use opcode `CUSTOM_3`(0x7b, 0b111_1011).
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**Pseudocode**: x[rd] = x[rs1] + x[rs2] + x[rs3]
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**Invalid values**: NONE
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- **CUS_ADD_RS3_MSUB**: Custom Add with RS3 opcode == MSUB
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**Format**: addi rd, rs1, rs2, rs3 -> |rs3|00|rs2|rs1|000|rd|100_0111|
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@ -84,8 +74,6 @@ All instructions use opcode `CUSTOM_3`(0x7b, 0b111_1011).
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**Pseudocode**: x[rd] = x[rs1] + x[rs2] + x[rs3]
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**Invalid values**: NONE
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- **CUS_ADD_RS3_NMADD**: Custom Add with RS3 opcode == NMADD
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**Format**: addi rd, rs1, rs2, rs3 -> |rs3|00|rs2|rs1|000|rd|100_1111|
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@ -94,18 +82,14 @@ All instructions use opcode `CUSTOM_3`(0x7b, 0b111_1011).
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**Pseudocode**: x[rd] = x[rs1] + x[rs2] + x[rs3]
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**Invalid values**: NONE
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- **CUS_ADD_RS3_NMSUB**: Custom Add with RS3 opcode == NMSUB
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- **CUS_ADD_RS3_NMADD**: Custom Add with RS3 opcode == NMSUB
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**Format**: addi rd, rs1, rs2, rs3 -> |rs3|00|rs2|rs1|000|rd|100_0011|
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**Format**: addi rd, rs1, rs2, rs3 -> |rs3|00|rs2|rs1|000|rd|100_1011|
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**Description**: add register rs1, rs2 to rs3, and store the result in rd.
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|
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**Pseudocode**: x[rd] = x[rs1] + x[rs2] + x[rs3]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
- **CUS_ADD_RS3_RTYPE**: Custom Add with RS3, rd is x10 (a0)
|
||||
|
||||
**Format**: addi a0, rs1, rs2, rs3 -> |0000100|rs2|rs1|001|rs3|100_0011|
|
||||
|
|
@ -114,18 +98,14 @@ All instructions use opcode `CUSTOM_3`(0x7b, 0b111_1011).
|
|||
|
||||
**Pseudocode**: x[10] = x[rs1] + x[rs2] + x[rs3]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
- **CUS_CNOP** : Custom Compressed NOP
|
||||
|
||||
**Format**: cus_cnop -> |111|0|00000|00000|00|
|
||||
**Format**: cus_cnop -> |111|0|rs1|rs2|00|
|
||||
|
||||
**Description**: Extends to CUS_NOP : do nothing, it's just a hint instruction.
|
||||
|
||||
**Pseudocode**: cus_cnop
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
- **CUS_CADD** : Custom Compressed ADD
|
||||
|
||||
**Format**: cus_cnop -> |111|1|rs1|rs2|00|
|
||||
|
|
@ -133,5 +113,3 @@ All instructions use opcode `CUSTOM_3`(0x7b, 0b111_1011).
|
|||
**Description**: Extends to CUS_ADD rs1, rs2 -> x10 : Add rs1 + rs2 into x10 (a0).
|
||||
|
||||
**Pseudocode**: cus_cadd
|
||||
|
||||
**Invalid values**: NONE
|
||||
52
verif/regress/cvxif_verif_regression.sh
Normal file
52
verif/regress/cvxif_verif_regression.sh
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
# Copyright 2024 Thales DIS France SAS
|
||||
#
|
||||
# Licensed under the Solderpad Hardware Licence, Version 2.0 (the License);
|
||||
# you may not use this file except in compliance with the License.
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
|
||||
# You may obtain a copy of the License at https://solderpad.org/licenses/
|
||||
#
|
||||
# Original Author: Guillaume Chauvon
|
||||
|
||||
|
||||
# where are the tools
|
||||
if ! [ -n "$RISCV" ]; then
|
||||
echo "Error: RISCV variable undefined"
|
||||
return
|
||||
fi
|
||||
|
||||
|
||||
# install the required tools
|
||||
source ./verif/regress/install-verilator.sh
|
||||
source ./verif/regress/install-spike.sh
|
||||
|
||||
# install the required test suites
|
||||
source ./verif/regress/install-riscv-tests.sh
|
||||
|
||||
# setup sim env
|
||||
source ./verif/sim/setup-env.sh
|
||||
|
||||
echo "$SPIKE_INSTALL_DIR$"
|
||||
|
||||
if ! [ -n "$DV_SIMULATORS" ]; then
|
||||
DV_SIMULATORS=vcs-testharness,spike
|
||||
fi
|
||||
|
||||
if ! [ -n "$UVM_VERBOSITY" ]; then
|
||||
export UVM_VERBOSITY=UVM_NONE
|
||||
fi
|
||||
|
||||
export cvxif=1 # For CVXIF in Spike
|
||||
export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
|
||||
|
||||
|
||||
cd verif/sim/
|
||||
make -C ../.. clean
|
||||
make clean_all
|
||||
python3 cva6.py --testlist=../tests/testlist_cvxif.yaml --test cvxif_add_nop --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
|
||||
make -C ../.. clean
|
||||
make clean_all
|
||||
python3 cva6.py --testlist=../tests/testlist_cvxif.yaml --test cvxif_add_nop --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS $DV_OPTS
|
||||
make -C ../.. clean
|
||||
make clean_all
|
||||
|
||||
cd -
|
||||
|
|
@ -36,7 +36,6 @@ if ! [ -n "$UVM_VERBOSITY" ]; then
|
|||
export UVM_VERBOSITY=UVM_NONE
|
||||
fi
|
||||
|
||||
export cvxif=1 # For CVXIF in Spike
|
||||
export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
|
||||
|
||||
CC_OPTS="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -lgcc"
|
||||
|
|
@ -62,7 +61,6 @@ make clean_all
|
|||
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS $DV_OPTS
|
||||
python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS $DV_OPTS
|
||||
python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
|
||||
python3 cva6.py --testlist=../tests/testlist_cvxif.yaml --test cvxif_add_nop --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS $DV_OPTS
|
||||
python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS --linker=../tests/custom/common/test.ld --gcc_opts="$CC_OPTS" $DV_OPTS
|
||||
make -C ../.. clean
|
||||
make clean_all
|
||||
|
|
|
|||
|
|
@ -114,28 +114,13 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #(
|
|||
.noc_resp_i ( axi_ariane_resp )
|
||||
);
|
||||
|
||||
if (CVA6Cfg.CvxifEn) begin : gen_example_coprocessor
|
||||
cvxif_example_coprocessor #(
|
||||
.NrRgprPorts (CVA6Cfg.NrRgprPorts),
|
||||
.readregflags_t (readregflags_t),
|
||||
.writeregflags_t (writeregflags_t),
|
||||
.id_t (id_t),
|
||||
.hartid_t (hartid_t),
|
||||
.x_compressed_req_t (x_compressed_req_t),
|
||||
.x_compressed_resp_t (x_compressed_resp_t),
|
||||
.x_issue_req_t (x_issue_req_t),
|
||||
.x_issue_resp_t (x_issue_resp_t),
|
||||
.x_register_t (x_register_t),
|
||||
.x_commit_t (x_commit_t),
|
||||
.x_result_t (x_result_t),
|
||||
.cvxif_req_t (cvxif_req_t),
|
||||
.cvxif_resp_t (cvxif_resp_t)
|
||||
) i_cvxif_coprocessor (
|
||||
.clk_i ( clk_i ),
|
||||
.rst_ni ( rst_ni ),
|
||||
.cvxif_req_i ( cvxif_req ),
|
||||
.cvxif_resp_o ( cvxif_resp )
|
||||
);
|
||||
if (CVA6Cfg.CvxifEn) begin : gen_cvxif_default_response
|
||||
always_comb begin
|
||||
cvxif_resp = '0;
|
||||
cvxif_resp.compressed_ready = 1'b1;
|
||||
cvxif_resp.issue_ready = 1'b1;
|
||||
cvxif_resp.register_ready = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ start0:
|
|||
CUS_ADD(01011, 01010, 01011);
|
||||
CUS_ADD(01010, 01011, 01011);
|
||||
lw a0, num1;
|
||||
CUS_ADD_RS1(01000,01010,01011);
|
||||
CUS_ADD_RS1(01100,01010,01011);
|
||||
lw a1, num2;
|
||||
CUS_ADD(01010,01011,00000);
|
||||
|
||||
|
|
@ -48,7 +48,7 @@ branch1:
|
|||
branch2:
|
||||
CUS_ADD(01010, 01010, 01011);
|
||||
lw a0, num1;
|
||||
CUS_ADD_RS1(01000,01010,01011);
|
||||
CUS_ADD_RS1(01100,01010,01011);
|
||||
lw a1, num2;
|
||||
CUS_ADD(01010,01011,00000);
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue