Merge branch 'openhwgroup:master' into TraceInterface

.gitlab-ci.yml

@@ -304,6 +304,20 @@ fpga-build:
     - mv corev_apu/fpga/work-fpga/ariane_xilinx.bit artifacts/ariane_xilinx_$TARGET.bit
     - python3 .gitlab-ci/scripts/report_fpga.py corev_apu/fpga/reports/ariane.utilization.rpt
 
+pmp_tests:
+  timeout : 2 hours
+  extends:
+    - .synthesis_test
+  variables:
+    DASHBOARD_JOB_TITLE: "PMP $DV_TARGET"
+    DASHBOARD_JOB_DESCRIPTION: "Physical Memory Protection tests"
+    DASHBOARD_SORT_INDEX: 2
+    DASHBOARD_JOB_CATEGORY: "Test suites"
+    DV_SIMULATORS: "vcs-uvm"
+    SPIKE_TANDEM: 1
+  script: source verif/regress/pmp_cv32a60x_tests.sh
+  after_script: *simu_after_script
+
 .regress_test:
   stage: heavy tests
   before_script:

.gitlab-ci/scripts/github_integration.py

@@ -3,6 +3,7 @@ This module makes it possible to trigger GitHub workflows.
 """
 
 from os import environ as env
+import time
 import requests
 
 def api_url(owner, repo):
@@ -52,6 +53,7 @@ class DashboardDone(Workflow):
             'pr_number': str(pr),
             'success': success,
         }
+        time.sleep(120)
         return self._trigger(inputs)
 
     def send_success(self, pr):

.gitlab-ci/scripts/report_synth.py

@@ -82,7 +82,7 @@ hier_metric = rb.TableMetric('Hierarchies details')
 for i in hier:
     hier_metric.add_value(
         i[0],  # hier
-        f"{int(float(i[1])/kgate_ratio)} kGates",  # area
+        f"{float(i[1])/kgate_ratio:.3f} kGates",  # area
         f"{int(float(i[2]))} %",  # %
         #int(float(i[3]))/int(float(i[1])*100),  # % combi
         #int(float(i[4]))/int(float(i[1])*100),  # % reg

Bender.yml

@@ -122,6 +122,7 @@ sources:
       # Frontend (i.e., fetch, decode, dispatch)
       - core/frontend/btb.sv
       - core/frontend/bht.sv
+      - core/frontend/bht2lvl.sv
       - core/frontend/ras.sv
       - core/frontend/instr_scan.sv
       - core/frontend/instr_queue.sv

CODEOWNERS

@@ -7,9 +7,18 @@ core/mmu_sv39 @sjthales
 core/cvxif_example @Gchauvon
 core/cvxif_fu.sv @Gchauvon
 
-# APU
+# HPDCache
+
+core/cache_subsystem/hpdcache @cfuguet
+core/cache_subsystem/cva6_hpdcache* @cfuguet
+core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @cfuguet
+core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv @cfuguet
+
+# OpenPiton
 
 corev_apu/openpiton @Jbalkind
+core/cache_subsystem/wt_l15_adapter.sv @Jbalkind
+core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @Jbalkind
 
 ## Documentation
 

Flist.ariane

@@ -72,6 +72,7 @@ core/decoder.sv
 core/ex_stage.sv
 core/frontend/btb.sv
 core/frontend/bht.sv
+core/frontend/bht2lvl.sv
 core/frontend/ras.sv
 core/frontend/instr_scan.sv
 core/frontend/instr_queue.sv

README.md

@@ -1,4 +1,4 @@
-# CVA6 RISC-V CPU [![Build Status](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml/badge.svg?branch=master)](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml) [![CVA6 dashboard](https://riscv-ci.pages.thales-invia.fr/dashboard/badge.svg)](https://riscv-ci.pages.thales-invia.fr/dashboard/) [![Documentation Status](https://readthedocs.com/projects/openhw-group-cva6-user-manual/badge/?version=latest)](https://docs.openhwgroup.org/projects/cva6-user-manual/?badge=latest) [![GitHub release](https://img.shields.io/github/release/openhwgroup/cva6?include_prereleases=&sort=semver&color=blue)](https://github.com/openhwgroup/cva6/releases/)
+# CVA6 RISC-V CPU [![Build Status](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml/badge.svg?branch=master)](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml) [![CVA6 dashboard](https://riscv-ci.pages.thales-invia.fr/dashboard/badge_master.svg)](https://riscv-ci.pages.thales-invia.fr/dashboard/dashboard_cva6.html) [![Documentation Status](https://readthedocs.com/projects/openhw-group-cva6-user-manual/badge/?version=latest)](https://docs.openhwgroup.org/projects/cva6-user-manual/?badge=latest) [![GitHub release](https://img.shields.io/github/release/openhwgroup/cva6?include_prereleases=&sort=semver&color=blue)](https://github.com/openhwgroup/cva6/releases/)
 
 CVA6 is a 6-stage, single-issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA V 2.3 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore, it is compliant to the draft external debug spec 0.13.
 

config/riscv-config/cv64a60ax/spec/isa_spec.yaml

@@ -23,7 +23,7 @@ hart0: &hart0
   physical_addr_sz: 39
   pmp_granularity: 10 # FIXME: To verify
   misa:
-    # reset-val: 0xC00000000214312F # B: bit 1, C: bit 2, I = bit 8, M = bit 12, Z = bit 25
+   reset-val: 0x800000000014312D # B: bit 1, C: bit 2, I = bit 8, M = bit 12, Z = bit 25
    rv64:
      accessible: true
      mxl:

core/Flist.cva6

@@ -144,6 +144,7 @@ ${CVA6_REPO_DIR}/core/cva6_fifo_v3.sv
 // What is "frontend"?
 ${CVA6_REPO_DIR}/core/frontend/btb.sv
 ${CVA6_REPO_DIR}/core/frontend/bht.sv
+${CVA6_REPO_DIR}/core/frontend/bht2lvl.sv
 ${CVA6_REPO_DIR}/core/frontend/ras.sv
 ${CVA6_REPO_DIR}/core/frontend/instr_scan.sv
 ${CVA6_REPO_DIR}/core/frontend/instr_queue.sv

core/cache_subsystem/wt_l15_adapter.sv

@@ -303,8 +303,12 @@ module wt_l15_adapter
   always_comb begin : p_rtrn_logic
     icache_rtrn_o.rtype = ICACHE_IFILL_ACK;
     dcache_rtrn_o.rtype = DCACHE_LOAD_ACK;
-    icache_rtrn_vld_o   = 1'b0;
-    dcache_rtrn_vld_o   = 1'b0;
+    icache_rtrn_vld_o = 1'b0;
+    dcache_rtrn_vld_o = 1'b0;
+    icache_rtrn_o.inv.vld = rtrn_fifo_data.l15_inval_icache_inval;
+    icache_rtrn_o.inv.all = rtrn_fifo_data.l15_inval_icache_all_way;
+    dcache_rtrn_o.inv.vld = rtrn_fifo_data.l15_inval_dcache_inval;
+    dcache_rtrn_o.inv.all = rtrn_fifo_data.l15_inval_dcache_all_way;
     if (!rtrn_fifo_empty) begin
       unique case (rtrn_fifo_data.l15_returntype)
         L15_LOAD_RET: begin
@@ -370,13 +374,9 @@ module wt_l15_adapter
   // invalidation signal mapping
   assign icache_rtrn_o.inv.idx = {rtrn_fifo_data.l15_inval_address_15_4, 4'b0000};
   assign icache_rtrn_o.inv.way = rtrn_fifo_data.l15_inval_way;
-  assign icache_rtrn_o.inv.vld = rtrn_fifo_data.l15_inval_icache_inval;
-  assign icache_rtrn_o.inv.all = rtrn_fifo_data.l15_inval_icache_all_way;
 
   assign dcache_rtrn_o.inv.idx = {rtrn_fifo_data.l15_inval_address_15_4, 4'b0000};
   assign dcache_rtrn_o.inv.way = rtrn_fifo_data.l15_inval_way;
-  assign dcache_rtrn_o.inv.vld = rtrn_fifo_data.l15_inval_dcache_inval;
-  assign dcache_rtrn_o.inv.all = rtrn_fifo_data.l15_inval_dcache_all_way;
 
   fifo_v2 #(
       .dtype(l15_rtrn_t),

core/cva6_rvfi.sv

@@ -429,7 +429,8 @@ module cva6_rvfi
   genvar i;
   generate
     for (i = 0; i < 16; i++) begin
-      `CONNECT_RVFI_FULL(1'b1, pmpaddr[i], csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0])
+      `CONNECT_RVFI_FULL(1'b1, pmpaddr[i], {
+                         csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1], pmpcfg_q[i].addr_mode[1]})
     end
   endgenerate
   ;

core/cvxif_fu.sv

@@ -22,6 +22,8 @@ module cvxif_fu
     input  logic                                   clk_i,
     // Asynchronous reset active low - SUBSYSTEM
     input  logic                                   rst_ni,
+    // Virtualization mode state - CSR_REGFILE
+    input  logic                                   v_i,
     // CVXIF instruction is valid - ISSUE_STAGE
     input  logic                                   x_valid_i,
     // Transaction ID - ISSUE_STAGE
@@ -68,6 +70,10 @@ module cvxif_fu
     x_exception_o.cause = x_illegal_i ? riscv::ILLEGAL_INSTR : '0;
     if (CVA6Cfg.TvalEn)
       x_exception_o.tval = x_off_instr_i;  // TODO Optimization : Set exception in IRO.
+    // Hypervisor exception fields
+    x_exception_o.tval2 = {CVA6Cfg.GPLEN{1'b0}};
+    x_exception_o.tinst = '0;
+    x_exception_o.gva   = CVA6Cfg.RVH ? v_i : 1'b0;
   end
 
 endmodule

core/decoder.sv

@@ -186,6 +186,7 @@ module decoder
     ecall                                  = 1'b0;
     ebreak                                 = 1'b0;
     check_fprm                             = 1'b0;
+    tinst                                  = 32'h0;
 
     if (~ex_i.valid) begin
       case (instr.rtype.opcode)

core/ex_stage.sv

@@ -621,6 +621,7 @@ module ex_stage
     ) cvxif_fu_i (
         .clk_i,
         .rst_ni,
+        .v_i,
         .x_valid_i(|x_valid_i),
         .x_trans_id_i(cvxif_data.trans_id),
         .x_illegal_i(x_transaction_rejected_i),

core/frontend/bht2lvl.sv

@@ -0,0 +1,133 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+//
+// Original author: Gianmarco Ottavi, University of Bologna
+// Description: Private history BHT
+
+module bht2lvl #(
+    parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
+    parameter type bht_update_t = logic
+) (
+    input  logic                                                      clk_i,
+    input  logic                                                      rst_ni,
+    input  logic                                                      flush_i,
+    input  logic                        [           CVA6Cfg.VLEN-1:0] vpc_i,
+    input  bht_update_t                                               bht_update_i,
+    // we potentially need INSTR_PER_FETCH predictions/cycle
+    output ariane_pkg::bht_prediction_t [CVA6Cfg.INSTR_PER_FETCH-1:0] bht_prediction_o
+);
+
+  // the last bit is always zero, we don't need it for indexing
+  localparam OFFSET = CVA6Cfg.RVC == 1'b1 ? 1 : 2;
+  // re-shape the branch history table
+  localparam NR_ROWS = CVA6Cfg.BHTEntries / CVA6Cfg.INSTR_PER_FETCH;
+  // number of bits needed to index the row
+  localparam ROW_ADDR_BITS = $clog2(CVA6Cfg.INSTR_PER_FETCH);
+  localparam ROW_INDEX_BITS = CVA6Cfg.RVC == 1'b1 ? $clog2(CVA6Cfg.INSTR_PER_FETCH) : 1;
+  // number of bits we should use for prediction
+  localparam PREDICTION_BITS = $clog2(NR_ROWS) + OFFSET + ROW_ADDR_BITS;
+
+  struct packed {
+    logic valid;
+    logic [CVA6Cfg.BHTHist-1:0] hist;
+    logic [2**CVA6Cfg.BHTHist-1:0][1:0] saturation_counter;
+  }
+      bht_d[NR_ROWS-1:0][CVA6Cfg.INSTR_PER_FETCH-1:0],
+      bht_q[NR_ROWS-1:0][CVA6Cfg.INSTR_PER_FETCH-1:0];
+
+
+  logic [$clog2(NR_ROWS)-1:0] index, update_pc;
+  logic [CVA6Cfg.BHTHist-1:0] update_hist;
+  logic [ ROW_INDEX_BITS-1:0] update_row_index;
+
+  assign index       = vpc_i[PREDICTION_BITS-1:ROW_ADDR_BITS+OFFSET];
+  assign update_pc   = bht_update_i.pc[PREDICTION_BITS-1:ROW_ADDR_BITS+OFFSET];
+  assign update_hist = bht_q[update_pc][update_row_index].hist;
+
+  if (CVA6Cfg.RVC) begin : gen_update_row_index
+    assign update_row_index = bht_update_i.pc[ROW_ADDR_BITS+OFFSET-1:OFFSET];
+  end else begin
+    assign update_row_index = '0;
+  end
+
+
+  logic [1:0] saturation_counter;
+
+  // Get the current history of the entry
+  logic [CVA6Cfg.INSTR_PER_FETCH-1:0][CVA6Cfg.BHTHist-1:0] read_history;
+  for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin
+    assign read_history[i] = bht_q[index][i].hist;
+  end
+
+  // prediction assignment
+  for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_bht_output
+    assign bht_prediction_o[i].valid = bht_q[index][i].valid;
+    assign bht_prediction_o[i].taken = bht_q[index][i].saturation_counter[read_history[i]][1] == 1'b1;
+  end
+
+  always_comb begin : update_bht
+    bht_d = bht_q;
+    saturation_counter = bht_q[update_pc][update_row_index].saturation_counter[update_hist];
+
+    if (bht_update_i.valid) begin
+      bht_d[update_pc][update_row_index].valid = 1'b1;
+
+      if (saturation_counter == 2'b11) begin
+        // we can safely decrease it
+        if (!bht_update_i.taken)
+          bht_d[update_pc][update_row_index].saturation_counter[update_hist] = saturation_counter - 1;
+        // then check if it saturated in the negative regime e.g.: branch not taken
+      end else if (saturation_counter == 2'b00) begin
+        // we can safely increase it
+        if (bht_update_i.taken)
+          bht_d[update_pc][update_row_index].saturation_counter[update_hist] = saturation_counter + 1;
+      end else begin  // otherwise we are not in any boundaries and can decrease or increase it
+        if (bht_update_i.taken)
+          bht_d[update_pc][update_row_index].saturation_counter[update_hist] = saturation_counter + 1;
+        else
+          bht_d[update_pc][update_row_index].saturation_counter[update_hist] = saturation_counter - 1;
+      end
+
+      bht_d[update_pc][update_row_index].hist = {
+        update_hist[CVA6Cfg.BHTHist-2:0], bht_update_i.taken
+      };
+    end
+  end
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      for (int unsigned i = 0; i < NR_ROWS; i++) begin
+        for (int j = 0; j < CVA6Cfg.INSTR_PER_FETCH; j++) begin
+          bht_q[i][j] <= '0;
+          for (int k = 0; k < 2 ** CVA6Cfg.BHTHist; k++) begin
+            bht_q[i][j].saturation_counter[k] <= 2'b10;
+          end
+        end
+      end
+    end else begin
+      // evict all entries
+      if (flush_i) begin
+        for (int i = 0; i < NR_ROWS; i++) begin
+          for (int j = 0; j < CVA6Cfg.INSTR_PER_FETCH; j++) begin
+            bht_q[i][j].valid <= 1'b0;
+            bht_q[i][j].hist  <= '0;
+            for (int k = 0; k < 2 ** CVA6Cfg.BHTHist; k++) begin
+              bht_q[i][j].saturation_counter[k] <= 2'b10;
+            end
+          end
+        end
+      end else begin
+        bht_q <= bht_d;
+      end
+    end
+  end
+
+
+endmodule

core/frontend/frontend.sv

@@ -510,7 +510,7 @@ module frontend
 
   if (CVA6Cfg.BHTEntries == 0) begin
     assign bht_prediction = '0;
-  end else begin : bht_gen
+  end else if (CVA6Cfg.BPType == config_pkg::BHT) begin : bht_gen
     bht #(
         .CVA6Cfg   (CVA6Cfg),
         .bht_update_t(bht_update_t),
@@ -524,6 +524,18 @@ module frontend
         .bht_update_i    (bht_update),
         .bht_prediction_o(bht_prediction)
     );
+  end else if (CVA6Cfg.BPType == config_pkg::PH_BHT) begin : bht2lvl_gen
+    bht2lvl #(
+        .CVA6Cfg     (CVA6Cfg),
+        .bht_update_t(bht_update_t)
+    ) i_bht (
+        .clk_i,
+        .rst_ni,
+        .flush_i         (flush_bp_i),
+        .vpc_i           (icache_vaddr_q),
+        .bht_update_i    (bht_update),
+        .bht_prediction_o(bht_prediction)
+    );
   end
 
   // we need to inspect up to CVA6Cfg.INSTR_PER_FETCH instructions for branches

core/id_stage.sv

@@ -269,6 +269,13 @@ module id_stage #(
     end else begin
       assign stall_instr_fetch[0] = stall_macro_deco;
     end
+  end else begin
+    for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
+      assign is_illegal_rvc[i] = 1'b0;
+      assign instruction_rvc[i] = fetch_entry_i[i].instruction;
+      assign is_compressed_rvc[i] = 1'b0;
+      assign stall_instr_fetch[i] = 1'b0;
+    end
   end
 
   // ---------------------------------------------------------

core/include/build_config_pkg.sv

@@ -103,7 +103,9 @@ package build_config_pkg;
     cfg.ExceptionAddress = CVA6Cfg.ExceptionAddress;
     cfg.RASDepth = CVA6Cfg.RASDepth;
     cfg.BTBEntries = CVA6Cfg.BTBEntries;
+    cfg.BPType = CVA6Cfg.BPType;
     cfg.BHTEntries = CVA6Cfg.BHTEntries;
+    cfg.BHTHist = CVA6Cfg.BHTHist;
     cfg.DmBaseAddress = CVA6Cfg.DmBaseAddress;
     cfg.TvalEn = CVA6Cfg.TvalEn;
     cfg.DirectVecOnly = CVA6Cfg.DirectVecOnly;

core/include/config_pkg.sv

@@ -35,6 +35,12 @@ package config_pkg;
     HPDCACHE_WT_WB = 4
   } cache_type_t;
 
+  /// Branch predictor parameter
+  typedef enum logic {
+    BHT = 0,  // Bimodal predictor
+    PH_BHT = 1  // Private History Bimodal predictor
+  } bp_type_t;
+
   /// Data and Address length
   typedef enum logic [3:0] {
     ModeOff  = 0,
@@ -214,8 +220,12 @@ package config_pkg;
     int unsigned                 RASDepth;
     // Branch target buffer entries
     int unsigned                 BTBEntries;
+    // Branch predictor type
+    bp_type_t                    BPType;
     // Branch history entries
     int unsigned                 BHTEntries;
+    // Branch history bits
+    int unsigned                 BHTHist;
     // MMU instruction TLB entries
     int unsigned                 InstrTlbEntries;
     // MMU data TLB entries
@@ -299,7 +309,9 @@ package config_pkg;
     logic [63:0] ExceptionAddress;
     int unsigned RASDepth;
     int unsigned BTBEntries;
+    bp_type_t    BPType;
     int unsigned BHTEntries;
+    int unsigned BHTHist;
     int unsigned InstrTlbEntries;
     int unsigned DataTlbEntries;
     bit unsigned UseSharedTlb;

core/include/cv32a60x_config_pkg.sv

@@ -62,11 +62,13 @@ package cva6_config_pkg;
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(2),
       BTBEntries: unsigned'(0),
+      BPType: config_pkg::BHT,
       BHTEntries: unsigned'(32),
+      BHTHist: unsigned'(3),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(0),
       DirectVecOnly: bit'(1),
-      NrPMPEntries: unsigned'(8),
+      NrPMPEntries: unsigned'(0),
       PMPCfgRstVal: {64{64'h0}},
       PMPAddrRstVal: {64{64'h0}},
       PMPEntryReadOnly: 64'd0,

core/include/cv32a65x_config_pkg.sv

@@ -62,7 +62,9 @@ package cva6_config_pkg;
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(2),
       BTBEntries: unsigned'(0),
+      BPType: config_pkg::BHT,
       BHTEntries: unsigned'(32),
+      BHTHist: unsigned'(3),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(0),
       DirectVecOnly: bit'(1),

core/include/cv32a6_embedded_config_pkg_deprecated.sv

@@ -117,7 +117,9 @@ package cva6_config_pkg;
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
       BTBEntries: unsigned'(CVA6ConfigBTBEntries),
+      BPType: config_pkg::BHT,
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
+      BHTHist: unsigned'(3),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
       DirectVecOnly: bit'(0),

core/include/cv32a6_ima_sv32_fpga_config_pkg.sv

@@ -115,7 +115,9 @@ package cva6_config_pkg;
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
       BTBEntries: unsigned'(CVA6ConfigBTBEntries),
+      BPType: config_pkg::BHT,
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
+      BHTHist: unsigned'(3),
       DmBaseAddress: 64'h0,
       TvalEn: unsigned'(CVA6ConfigTvalEn),
       DirectVecOnly: bit'(0),

core/include/cv32a6_imac_sv0_config_pkg.sv

@@ -115,7 +115,9 @@ package cva6_config_pkg;
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
       BTBEntries: unsigned'(CVA6ConfigBTBEntries),
+      BPType: config_pkg::BHT,
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
+      BHTHist: unsigned'(3),
       DmBaseAddress: 64'h0,
       TvalEn: unsigned'(CVA6ConfigTvalEn),
       DirectVecOnly: bit'(0),

core/include/cv32a6_imac_sv32_config_pkg.sv

@@ -114,7 +114,9 @@ package cva6_config_pkg;
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
       BTBEntries: unsigned'(CVA6ConfigBTBEntries),
+      BPType: config_pkg::BHT,
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
+      BHTHist: unsigned'(3),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
       DirectVecOnly: bit'(0),

core/include/cv32a6_imafc_sv32_config_pkg.sv

@@ -115,7 +115,9 @@ package cva6_config_pkg;
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
       BTBEntries: unsigned'(CVA6ConfigBTBEntries),
+      BPType: config_pkg::BHT,
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
+      BHTHist: unsigned'(3),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
       DirectVecOnly: bit'(0),

core/include/cv64a60ax_config_pkg.sv

@@ -69,7 +69,9 @@ localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
    ExceptionAddress: 64'h808,
    RASDepth: unsigned'(4),
    BTBEntries: unsigned'(16),
+   BPType: config_pkg::BHT,
    BHTEntries: unsigned'(64),
+   BHTHist: unsigned'(3),
    DmBaseAddress: 64'h0,
    TvalEn: bit'(1),
    DirectVecOnly: bit'(0),

core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv

@@ -118,7 +118,9 @@ package cva6_config_pkg;
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
       BTBEntries: unsigned'(CVA6ConfigBTBEntries),
+      BPType: config_pkg::BHT,
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
+      BHTHist: unsigned'(3),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
       DirectVecOnly: bit'(0),

core/include/cv64a6_imafdc_sv39_config_pkg.sv

@@ -118,7 +118,9 @@ package cva6_config_pkg;
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
       BTBEntries: unsigned'(CVA6ConfigBTBEntries),
+      BPType: config_pkg::BHT,
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
+      BHTHist: unsigned'(3),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
       DirectVecOnly: bit'(0),

core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv

@@ -125,7 +125,9 @@ package cva6_config_pkg;
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
       BTBEntries: unsigned'(CVA6ConfigBTBEntries),
+      BPType: config_pkg::BHT,
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
+      BHTHist: unsigned'(3),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
       DirectVecOnly: bit'(0),

core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv

@@ -125,7 +125,9 @@ package cva6_config_pkg;
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
       BTBEntries: unsigned'(CVA6ConfigBTBEntries),
+      BPType: config_pkg::BHT,
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
+      BHTHist: unsigned'(3),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
       DirectVecOnly: bit'(0),

core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv

@@ -118,7 +118,9 @@ package cva6_config_pkg;
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
       BTBEntries: unsigned'(CVA6ConfigBTBEntries),
+      BPType: config_pkg::BHT,
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
+      BHTHist: unsigned'(3),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
       DirectVecOnly: bit'(0),

core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv

@@ -118,7 +118,9 @@ package cva6_config_pkg;
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
       BTBEntries: unsigned'(CVA6ConfigBTBEntries),
+      BPType: config_pkg::BHT,
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
+      BHTHist: unsigned'(3),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
       DirectVecOnly: bit'(0),

core/include/cv64a6_imafdch_sv39_config_pkg.sv

@@ -118,7 +118,9 @@ package cva6_config_pkg;
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
       BTBEntries: unsigned'(CVA6ConfigBTBEntries),
+      BPType: config_pkg::BHT,
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
+      BHTHist: unsigned'(3),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
       DirectVecOnly: bit'(0),

core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv

@@ -118,7 +118,9 @@ package cva6_config_pkg;
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
       BTBEntries: unsigned'(CVA6ConfigBTBEntries),
+      BPType: config_pkg::BHT,
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
+      BHTHist: unsigned'(3),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
       DirectVecOnly: bit'(0),

core/include/cv64a6_imafdcv_sv39_config_pkg.sv

@@ -120,7 +120,9 @@ package cva6_config_pkg;
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(CVA6ConfigRASDepth),
       BTBEntries: unsigned'(CVA6ConfigBTBEntries),
+      BPType: config_pkg::BHT,
       BHTEntries: unsigned'(CVA6ConfigBHTEntries),
+      BHTHist: unsigned'(3),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(CVA6ConfigTvalEn),
       DirectVecOnly: bit'(0),

core/include/cv64a6_mmu_config_pkg.sv

@@ -69,7 +69,9 @@ package cva6_config_pkg;
       ExceptionAddress: 64'h808,
       RASDepth: unsigned'(2),
       BTBEntries: unsigned'(0),
+      BPType: config_pkg::BHT,
       BHTEntries: unsigned'(32),
+      BHTHist: unsigned'(3),
       DmBaseAddress: 64'h0,
       TvalEn: bit'(0),
       DirectVecOnly: bit'(1),

docs/07_cv32a60x/index.rst

@@ -0,0 +1,8 @@
+CV32A60X documentation
+======================
+
+.. toctree::
+   :maxdepth: 1
+
+   riscv/unpriv.rst
+   riscv/priv.rst

docs/07_cv32a60x/riscv/Makefile

@@ -0,0 +1,10 @@
+#   Copyright 2025 Thales DIS France SAS
+#   Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
+#   you may not use this file except in compliance with the License.
+#   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+#   You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+#   Original Author: André Sintzoff - Thales DIS
+
+CONFIG := cv32a60x
+include ../../riscv-isa/build.mk

docs/07_cv32a60x/riscv/priv.rst

@@ -0,0 +1,14 @@
+..
+   Copyright (c) 2025 Thales DIS France SAS
+   Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+   You may obtain a copy of the License at https://solderpad.org/licenses/
+
+   Original Author: André Sintzoff - Thales DIS
+
+Privileged RISC-V ISA
+=====================
+
+.. raw:: html
+   :file: priv-isa-cv32a60x.html

docs/07_cv32a60x/riscv/unpriv.rst

@@ -0,0 +1,14 @@
+..
+   Copyright (c) 2025 Thales DIS France SAS
+   Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+   You may obtain a copy of the License at https://solderpad.org/licenses/
+
+   Original Author: André Sintzoff - Thales DIS
+
+Unprivileged RISC-V ISA
+=======================
+
+.. raw:: html
+   :file: unpriv-isa-cv32a60x.html

docs/Makefile

@@ -6,6 +6,8 @@ prepare:
 
 	make -C 06_cv64a6_mmu/riscv priv-html unpriv-html
 
+	make -C 07_cv32a60x/riscv priv-html unpriv-html
+
 sphinx:
 	sphinx-build . _build
 

docs/common/config_define.adoc

@@ -1,12 +1,21 @@
 
+ifeval::["{ohg-config}"=="CV32A60X"]
+:archi-CVA6:
+:archi-CV32A60X:
+// specify that it is a custom architecture
+:archi-not-default:
+endif::[]
+
 ifeval::["{ohg-config}"=="CV32A65X"]
 :archi-CVA6:
+:archi-CV32A65X:
 // specify that it is a custom architecture
 :archi-not-default:
 endif::[]
 
 ifeval::["{ohg-config}"=="CV64A6_MMU"]
 :archi-CVA6:
+:archi-CV64A6_MMU:
 // specify that it is a custom architecture
 :archi-not-default:
 endif::[]

docs/index.rst

@@ -69,5 +69,6 @@ The :doc:`CVA6 APU <05_cva6_apu/index>` describes an Application Processor Unit
    01_cva6_user/index.rst
    03_cva6_design/index.rst
    04_cv32a65x/index.rst
+   07_cv32a60x/index.rst
    06_cv64a6_mmu/index.rst
    05_cva6_apu/index.rst

docs/riscv-isa/src/machine.adoc

@@ -398,7 +398,7 @@ field is not implemented. The Implementation value should reflect the
 design of the RISC-V processor itself and not any surrounding system.
 endif::[]
 
-ifeval::["{ohg-config}" == "CV32A65X"]
+ifdef::archi-CV32A60X,archi-CV32A65X[]
 The `mimpid` CSR provides a unique encoding of the version of the
 processor implementation.
 
@@ -508,7 +508,7 @@ For RV32 only, `mstatush` is a 32-bit read/write register formatted as
 shown in <<mstatushreg>>. Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`.
 endif::[]
 
-ifeval::["{ohg-config}" == "CV32A65X"]
+ifdef::archi-CV32A60X,archi-CV32A65X[]
 [{ohg-config}] `mstatush` is a 32-bit read/write register formatted as
 shown in <<mstatushreg>>.
 endif::[]
@@ -1249,7 +1249,7 @@ different encoding than XS.
 ====
 endif::[]
 
-ifeval::["{ohg-config}" == "CV32A65X"]
+ifdef::archi-CV32A60X,archi-CV32A65X[]
 [{ohg-config}] The FS[1:0] and VS[1:0] *WARL* fields and the XS[1:0] read-only field are used
 to reduce the cost of context save and restore by setting and tracking
 the current state of the floating-point unit and any other user-mode
@@ -2115,7 +2115,7 @@ ifdef::archi-CVA6[]
 As the Sscofpmf extension is not implemented, `mip`.LCOFIP and `mie`.LCOFIE are read-only zeros.
 endif::[]
 
-ifeval::["{ohg-config}" == "CV32A65X"]
+ifdef::archi-CV32A60X,archi-CV32A65X[]
 [{ohg-config}]
 Multiple simultaneous interrupts destined for M-mode are handled in the
 following decreasing priority order: MEI, MSI, MTI.
@@ -2218,7 +2218,7 @@ As XLEN=64, `mcycleh`, `minstreth`, and `mhpmcounter__n__h`
 do not exist.
 endif::[]
 
-ifeval::["{ohg-config}" == "CV32A65X"]
+ifdef::archi-CV32A60X,archi-CV32A65X[]
 As the Sscofpmf extension is not implemented, the `mhpmevent__n__h` CSRs
 are not provided.
 endif::[]
@@ -3509,7 +3509,7 @@ As "{ohg-config}" does not distinguished different reset conditions,
 The `mcause` returns 0 after reset.
 endif::[]
 
-ifeval::["{ohg-config}" == "CV32A65X"]
+ifdef::archi-CV32A60X,archi-CV32A65X[]
 [{ohg-config}] Privilege mode is always M.
 As little-endian memory accesses are supported,
 the `mstatus`/`mstatush` field MBE is reset to 0.
@@ -4068,6 +4068,13 @@ endif::[]
 [[pmp]]
 === Physical Memory Protection
 
+ifeval::[{NrPMPEntries} == 0]
+[{ohg-config}] There is no optional physical memory protection (PMP)
+unit.
+endif::[]
+
+ifeval::[{NrPMPEntries} != 0]
+
 To support secure processing and contain faults, it is desirable to
 limit the physical addresses accessible by software running on a hart.
 An optional physical memory protection (PMP) unit provides per-hart
@@ -4491,3 +4498,5 @@ ifeval::["{ohg-config}" == "CV32A65X"]
 [{ohg-config}] As page-based virtual memory systems is not implemented, memory accesses
 check the PMP settings synchronously.
 endif::[]
+
+endif::[]

docs/riscv-isa/src/mm-formal.adoc

@@ -2,6 +2,6 @@
 == Formal Memory Model Specifications, Version 0.1
 [[mm-formal]]
 
-ifeval::["{ohg-config}" == "CV32A65X"]
+ifdef::archi-CV32A60X,archi-CV32A65X[]
 {ohg-config}: No RVWMO memory model.
 endif::[]

docs/riscv-isa/src/rv-32-64g.adoc

@@ -16,6 +16,39 @@ ifdef::archi-CVA6[]
 listings for {ohg-config}.
 endif::[]
 
+ifeval::[{RVA} == true]
+:AMO: AMO
+endif::[]
+ifeval::[{RVA} == false]
+:AMO: not used
+endif::[]
+ifeval::[{RVF} == true]
+:LOAD-FP: LOAD-FP
+:STORE-FP: STORE-FP
+:MADD: MADD
+:MSUB: MSUB
+:NMSUB: NMSUB
+:NMADD: NMADD
+:OP-FP: OP-FP
+endif::[]
+ifeval::[{RVF} == false]
+:LOAD-FP: _not-used_
+:STORE-FP: not used
+:MADD: not used
+:MSUB: not used
+:NMSUB: not used
+:NMADD: not used
+:OP-FP: not used
+endif::[]
+ifeval::[{RVV} == true]
+:OP-V: OP-V
+:OP-VE: OP-VE
+endif::[]
+ifeval::[{RVV} == false]
+:OP-V: not used
+:OP-VE: not used
+endif::[]
+
 // note: ≥ is unicode for >=
 [[opcodemap]]
 .RISC-V base opcode map, inst[1:0]=11
@@ -23,10 +56,10 @@ endif::[]
 |===
 |inst[4:2] .2+|000 .2+|001   .2+|010     .2+|011   .2+|100 .2+|101     .2+|110          .2+|111 (>32b)
 |inst[6:5]
-|00           |LOAD   |LOAD-FP  |_custom-0_ |MISC-MEM |OP-IMM |AUIPC      |OP-IMM-32       |48b
-|01           |STORE  |STORE-FP |_custom-1_ |AMO      |OP     |LUI        |OP-32           |64b
-|10           |MADD   |MSUB     |NMSUB      |NMADD    |OP-FP  |OP-V       |_custom-2/rv128_|48b
-|11           |BRANCH |JALR     |_reserved_ |JAL      |SYSTEM |OP-VE      |_custom-3/rv128_|≥80b
+|00           |LOAD   |{LOAD-FP}|_custom-0_ |MISC-MEM |OP-IMM |AUIPC      |OP-IMM-32       |48b
+|01           |STORE  |{STORE-FP}|_custom-1_|{AMO}    |OP     |LUI        |OP-32           |64b
+|10           |{MADD} |{MSUB}   |{NMSUB}    |{NMADD}  |{OP-FP}|{OP-V}     |_custom-2/rv128_|48b
+|11           |BRANCH |JALR     |_reserved_ |JAL      |SYSTEM |{OP-VE}    |_custom-3/rv128_|≥80b
 |===
 
 <<opcodemap>> shows a map of the major opcodes for

docs/riscv-isa/src/zimop.adoc

@@ -7,6 +7,6 @@ endif::[]
 
 === "Zcmop" Compressed May-Be-Operations Extension, Version 1.0
 
-ifeval::[{RVZimop} == false]
+ifeval::[{RVZcmop} == false]
 {ohg-config}: This extension is not supported.
 endif::[]

docs/scripts/spec_builder.py

@@ -51,14 +51,24 @@ DEFAULT_PARAMS = {
     'RVZabha': False,
     'RVZacas': False,
     'RVZawrs': False,
+    'RVZcmop': False,
     'RVZfa': False,
     'RVZfbf-RZvfbf': False,
     'RVZfh': False,
     'RVZfinx': False,
     'RVZicbo': False,
     'RVZicfilp': False,
+    'RVZifencei': False,
+    'RVZihintntl': False,
+    'RVZihintpause': False,
+    'RVZimop': False,
+    'RVZk': False,
     'RVZpm': False,
+    'RVZsmcdeleg': False,
+    'RVZsmcntrpmf': False,
+    'RVZsmcsrind-RVZsscsrind': False,
     'RVZsmctr': False,
+    'RVZsmdbltrp': False,
     'RVZsmepmp': False,
     'RVZsmmpm': False,
     'RVZsmrnmi': False,
@@ -181,6 +191,7 @@ def main():
         file.append("../core/cva6.sv")
         file.append("../core/frontend/frontend.sv")
         file.append("../core/frontend/bht.sv")
+        file.append("../core/frontend/bht2lvl.sv")
         file.append("../core/frontend/btb.sv")
         file.append("../core/frontend/ras.sv")
         file.append("../core/frontend/instr_queue.sv")

src_files.yml

@@ -22,6 +22,7 @@ ariane:
     src/ex_stage.sv,
     src/frontend/btb.sv,
     src/frontend/bht.sv,
+    src/frontend/bht2lvl.sv,
     src/frontend/ras.sv,
     src/frontend/instr_scan.sv,
     src/frontend/frontend.sv,

verif/docs/VerifPlans/PMP/VP_IP000.yml

@@ -0,0 +1,358 @@
+!Feature
+next_elt_id: 15
+name: TRISTAN Restrictions
+id: 0
+display_order: 0
+subfeatures: !!omap
+- 000_general: !Subfeature
+    name: 000_general
+    tag: VP_PMP_F000_S000
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F000_S000_I000
+        description: "\nthe verif plan is written for 32bits architecture only"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: ''
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 001_number of harts: !Subfeature
+    name: 001_number of harts
+    tag: VP_PMP_F000_S001
+    next_elt_id: 2
+    display_order: 1
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F000_S001_I000
+        description: "\nthere is only 1 hart in cv32a6"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: ''
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 002_mxlen: !Subfeature
+    name: 002_mxlen
+    tag: VP_PMP_F000_S002
+    next_elt_id: 1
+    display_order: 2
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F000_S002_I000
+        description: "\nMXLEN is always 32bits"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: ''
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 003_xlen: !Subfeature
+    name: 003_xlen
+    tag: VP_PMP_F000_S003
+    next_elt_id: 1
+    display_order: 3
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F000_S003_I000
+        description: "\nXLEN=MXLEN=32, so the PMP address registers are XLEN bits
+          long, so no zero-extension needed"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: ''
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 004_granularity: !Subfeature
+    name: 004_granularity
+    tag: VP_PMP_F000_S004
+    next_elt_id: 1
+    display_order: 4
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F000_S004_I000
+        description: "\nPMP granularity is 8 bytes (G=1), but the verif plan is written
+          to take G=0 into account (NA4)"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: ''
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 005_number of pmp entries: !Subfeature
+    name: 005_number of pmp entries
+    tag: VP_PMP_F000_S005
+    next_elt_id: 1
+    display_order: 5
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F000_S005_I000
+        description: "\nthere are 8 HW implemented PMP entries"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: ''
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 006_hardwired regions: !Subfeature
+    name: 006_hardwired regions
+    tag: VP_PMP_F000_S006
+    next_elt_id: 1
+    display_order: 6
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F000_S006_I000
+        description: "\nnone of the 8 PMP entries is hardwired privileges"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: ''
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 007_virtual memory: !Subfeature
+    name: 007_virtual memory
+    tag: VP_PMP_F000_S007
+    next_elt_id: 1
+    display_order: 7
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F000_S007_I000
+        description: "\nno virtual memory is implemented\nas a consequence no page-based
+          virtual memory is implemented"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: ''
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 008_physical memory regions: !Subfeature
+    name: 008_physical memory regions
+    tag: VP_PMP_F000_S008
+    next_elt_id: 1
+    display_order: 8
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F000_S008_I000
+        description: "\nthe list of all physical memory regions\n - system memory
+          regions\n - I-$\n - D-$\n - I-scratchpad (preload mode)\n - I-scratchpad
+          (functional mode)\n - D-scratchpad\n - ahb_periph"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: ''
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 009_pmp entry disabling: !Subfeature
+    name: 009_pmp entry disabling
+    tag: VP_PMP_F000_S009
+    next_elt_id: 1
+    display_order: 9
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F000_S009_I000
+        description: "\nwe assume an already written PMP entry (i) can be disabled\n\
+          \  - if L=0, by clearing pmpcfg(i)\n  - if L=1, only by hart reset"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: ''
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 010_access-faults (violations): !Subfeature
+    name: 010_access-faults (violations)
+    tag: VP_PMP_F000_S010
+    next_elt_id: 1
+    display_order: 10
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F000_S010_I000
+        description: "\nThe testbench/testcases architecture ensures that:\n - any
+          time there is an access-fault type, we check it matches the related access-type\n
+          - all violations are trapped at the processor\n\n{Page 56 Volume II: RISC-V
+          Privileged Architectures V20211203}\nPMP violations are always trapped precisely
+          at the processor"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: ''
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 011_testcases modularity: !Subfeature
+    name: 011_testcases modularity
+    tag: VP_PMP_F000_S011
+    next_elt_id: 1
+    display_order: 11
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F000_S011_I000
+        description: "\nThe verif plan is written assuming there is a way (like SystemVerilog
+          interaction):\n - to factorize the testcases in code blocks (in particular
+          configuration code block and access code block)\n - to randomize the code
+          blocks data and addresses\n - to randomize the sequence of code blocks"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: ''
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 012_access types: !Subfeature
+    name: 012_access types
+    tag: VP_PMP_F000_S012
+    next_elt_id: 1
+    display_order: 12
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F000_S012_I000
+        description: "at the time of writing,\nthe verif plan makes no distinction
+          between load and load-reserved instructions. they are gathered in the same
+          access type, subtleties unknown\nthe verif plan makes no distinction between
+          store, store-conditional, and AMO instructions. they are gathered in the
+          same access type, subtleties unknown"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: ''
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 013_multiple accesses instructions: !Subfeature
+    name: 013_multiple accesses instructions
+    tag: VP_PMP_F000_S013
+    next_elt_id: 1
+    display_order: 13
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F000_S013_I000
+        description: "\nwe assume there is no added value to test multiple accesses
+          instructions"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: ''
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 014_misaligned instructions: !Subfeature
+    name: 014_misaligned instructions
+    tag: VP_PMP_F000_S014
+    next_elt_id: 1
+    display_order: 14
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F000_S014_I000
+        description: "\nwe assume that instructions are mandatorily aligned"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: ''
+        pfc: -1
+        test_type: -1
+        cov_method: -1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
+io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
+config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
+ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'

verif/docs/VerifPlans/PMP/VP_IP001.yml

@@ -0,0 +1,45 @@
+!Feature
+next_elt_id: 1
+name: PMP granularity
+id: 1
+display_order: 1
+subfeatures: !!omap
+- 000_granularity_check: !Subfeature
+    name: 000_granularity_check
+    tag: VP_PMP_F001_S000
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F001_S000_I000
+        description: "{Page 59 Volume II: RISC-V Privileged Architectures V20211203}\n
+          \nSoftware may determine the PMP granularity by writing zero to pmp0cfg,
+          then writing all ones to pmpaddr0, then reading back pmpaddr0.\nIf G is
+          the index of the least-signicant bit set, the PMP granularity is 2G+2 bytes."
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: '59'
+        ref_section: ''
+        ref_viewer: evince
+        verif_goals: determine the PMP granularity 2^(G+2) bytes by writing zero to
+          pmp(0)cfg, then writing all ones to pmpaddr(0), then reading back pmpaddr(0).
+          G is the index G of the least-significant bit set
+        pfc: 11
+        test_type: 2
+        cov_method: 0
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nFTR07-b\nSoftware may determine the PMP granularity
+          by writing zero to pmp0cfg, then writing all ones to pmpaddr0, then reading
+          back pmpaddr0.\n If G is the index of the least-signicant bit set, the
+          PMP granularity is 2G+2 bytes.\n\n\nTST01 (HIGH-PRIO) => FTR07-b\n[determine
+          the PMP granularity 2^(G+2) bytes by writing zero to pmp(0)cfg, then writing
+          all ones to pmpaddr(0), then reading back pmpaddr(0). G is the index G of
+          the least-significant bit set]"
+vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
+io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
+config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
+ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'

verif/docs/VerifPlans/PMP/VP_IP002.yml

@@ -0,0 +1,159 @@
+!Feature
+next_elt_id: 4
+name: CSRs M-mode only
+id: 2
+display_order: 2
+subfeatures: !!omap
+- 000_configure_1_pmp_entry: !Subfeature
+    name: 000_configure_1_pmp_entry
+    tag: VP_PMP_F002_S001
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F002_S001_I000
+        description: "{Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures
+          V20211203}\n\nPMP CSRs are only accessible to M-mode"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "configure 1 PMP entry (i) (the 1st one),\n  - check for each
+          PMP entry (i) reset value (read zero) by reading in M mode\n  - check for
+          each PMP entry (i) that pmp(i)cfg and pmpaddr(i) are not writable/readable
+          in S or U modes\n  - check for each PMP entry (i) that pmp(i)cfg and pmpaddr(i)
+          are writable/readable in M-mode only\n  - check for each PMP entry (i) that
+          pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST02(group) => FTR02-d\n  [check that all 8 HW implemented
+          PMP entries are writable/readable in M-mode (L=0)]\n  [check that no HW
+          implemented PMP entry are writable/readable in S or U modes (L=0)]\n   \
+          \ - random values may be used\n    - before any configuration (after hart
+          reset), check all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST02-1
+          (HIGH-PRIO)\n[configure 1 PMP entry ([FTR02-b1]: maybe mandatorily the first
+          one): with L=0,\n  - if possible, the PMP entry number is a configurable
+          parameter\n  - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i)
+          are not writable/readable in S or U modes\n  - check for PMP entry (i) where
+          L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only\n\
+          \  - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are
+          not writable/readable in S or U modes]"
+- 001_configure_2_pmp_entries: !Subfeature
+    name: 001_configure_2_pmp_entries
+    tag: VP_PMP_F002_S002
+    next_elt_id: 1
+    display_order: 1
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F002_S002_I000
+        description: "{Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures
+          V20211203}\n\nPMP CSRs are only accessible to M-mode"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "configure 2 PMP entries (the 2 first ones in incrementing order),\n\
+          \  - reuse of VP_PMP_F002_S001_I000 sequence"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST02(group) => FTR02-d\n  [check that all 8 HW implemented
+          PMP entries are writable/readable in M-mode (L=0)]\n  [check that no HW
+          implemented PMP entry are writable/readable in S or U modes (L=0)]\n   \
+          \ - random values may be used\n    - before any configuration (after hart
+          reset), check all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST02-2
+          (LOW-PRIO) = 2 times reuse/call of TST02-1\n[configure 2 PMP entries ([FTR02-b1]:
+          maybe mandatorily the 2 first ones): both with L=0,\n  - check for PMP entry
+          (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in
+          S or U modes\n  - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i)
+          are writable/readable in M-mode only\n  - check for PMP entry (i) where
+          L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes]"
+- 002_configure_N_pmp_entries: !Subfeature
+    name: 002_configure_N_pmp_entries
+    tag: VP_PMP_F002_S003
+    next_elt_id: 1
+    display_order: 2
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F002_S003_I000
+        description: "{Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures
+          V20211203}\n\nPMP CSRs are only accessible to M-mode"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "configure N PMP entries (the N first ones in incrementing order),\n\
+          \  - reuse of VP_PMP_F002_S001_I000 sequence"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST02(group) => FTR02-d\n  [check that all 8 HW implemented
+          PMP entries are writable/readable in M-mode (L=0)]\n  [check that no HW
+          implemented PMP entry are writable/readable in S or U modes (L=0)]\n   \
+          \ - random values may be used\n    - before any configuration (after hart
+          reset), check all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST02-3
+          (LOW-PRIO) = N times reuse/call of TST02-1\n[configure N PMP entries ([FTR02-b1]:
+          maybe mandatorily the N first ones): all with L=0,\n  - check for PMP entry
+          (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in
+          S or U modes\n  - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i)
+          are writable/readable in M-mode only\n  - check for PMP entry (i) where
+          L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes]"
+- 003_configure_8_pmp_entries: !Subfeature
+    name: 003_configure_8_pmp_entries
+    tag: VP_PMP_F002_S004
+    next_elt_id: 1
+    display_order: 3
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F002_S004_I000
+        description: "{Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures
+          V20211203}\n\nPMP CSRs are only accessible to M-mode"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "configure all 8 PMP entries (in incrementing order),\n  - reuse
+          of VP_PMP_F002_S001_I000 sequence"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST02(group) => FTR02-d\n  [check that all 8 HW implemented
+          PMP entries are writable/readable in M-mode (L=0)]\n  [check that no HW
+          implemented PMP entry are writable/readable in S or U modes (L=0)]\n   \
+          \ - random values may be used\n    - before any configuration (after hart
+          reset), check all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST02-4
+          (HIGH-PRIO) = 8 times reuse/call of TST02-1\n[configure 8 PMP entries: all
+          with L=0,\n  - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i)
+          are not writable/readable in S or U modes\n  - check for PMP entry (i) where
+          L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only\n\
+          \  - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are
+          not writable/readable in S or U modes]"
+vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
+io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
+config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
+ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'

verif/docs/VerifPlans/PMP/VP_IP003.yml

@@ -0,0 +1,277 @@
+!Feature
+next_elt_id: 5
+name: CSRs locked access
+id: 3
+display_order: 3
+subfeatures: !!omap
+- 000_configure_1_pmp_entry: !Subfeature
+    name: 000_configure_1_pmp_entry
+    tag: VP_PMP_F003_S001
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F003_S001_I000
+        description: "{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
+          Privileged Architectures V20211203}\n\nThe L bit indicates that the PMP
+          entry is locked, i.e., writes to the configuration register and associated
+          address registers are ignored\nIf PMP entry (i) is locked, writes to pmp(i)cfg
+          and pmpaddr(i) are ignored\nLocked PMP entries remain locked until the hart
+          is reset\n\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II:
+          RISC-V Privileged Architectures V20211203}\n\nSetting the L bit locks the
+          PMP entry even when the A field is set to OFF\n\nAdditionally, if PMP entry
+          (i) is locked and pmp(i)cfg.A is set to TOR, writes to pmpaddr(i-1) are
+          ignored"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "configure 1 PMP entry (the 1st one) with L=1,\n  - write PMP
+          entry (i) with L=1 in M-mode\n  - A is random, should also be tried with
+          A=OFF when L=1 (to cover feature above)\n  - check PMP entry (i) written
+          value in M-mode\n  - check for PMP entry (i) where L=1 that pmp(i)cfg and
+          pmpaddr(i) are effectively locked (M-mode check only)\n  - also check for
+          PMP entry (i) where L=1 and pmp(i)cfg.A=TOR that pmpaddr(i-1) is effectively
+          locked\n  - apply hart reset\n  - check for PMP entry (i) reset value (read
+          zero) by reading in M mode\n  - write PMP entry (i) in M-mode\n  - check
+          PMP entry (i) written value in M-mode\n\nREUSABILITY\n  - if possible, the
+          PMP entry number (i) is a configurable parameter\n  - if possible, (L) value
+          is a configurable parameter\n  - so the same sub-functions are reused with
+          varying (i) and (L) parameters"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST03(group) => FTR08-a and FTR08-b\n  [check that HW
+          implemented PMP entries are not writable/readable in M-mode (L=1)]\n  [check
+          that no HW implemented PMP entry are writable/readable in S or U modes (L=1)]\n\
+          \    - before any configuration, check all pmp(i)cfg and pmpaddr(i) are
+          M-mode read zero\n    - configure PMP entry (i) with L=1 (or 0):  pmp(i)cfg
+          and pmpaddr(i) maybe random values\n    - execute following tests specific
+          checks\n    - check only hart reset unlocks all => FTR08-b\n    - check
+          reset values: all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST03-1
+          (HIGH-PRIO)\n[configure 1 PMP entry ([FTR02-b1]: maybe mandatorily the first
+          one): with L=1,\n  - if possible, the PMP entry number is a configurable
+          parameter\n  - if possible, L value is a configurable parameter\n  - check
+          for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively
+          locked whatever the SW mode => FTR08-a\n  - check for PMP entry (i) where
+          L=1 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes]"
+- 001_configure_2_pmp_entries_L1: !Subfeature
+    name: 001_configure_2_pmp_entries_L1
+    tag: VP_PMP_F003_S002
+    next_elt_id: 1
+    display_order: 1
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F003_S002_I000
+        description: "{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
+          Privileged Architectures V20211203}\n\nThe L bit indicates that the PMP
+          entry is locked, i.e., writes to the configuration register and associated
+          address registers are ignored\nIf PMP entry (i) is locked, writes to pmp(i)cfg
+          and pmpaddr(i) are ignored\nLocked PMP entries remain locked until the hart
+          is reset\n\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II:
+          RISC-V Privileged Architectures V20211203}\n\nSetting the L bit locks the
+          PMP entry even when the A field is set to OFF\n\nAdditionally, if PMP entry
+          (i) is locked and pmp(i)cfg.A is set to TOR, writes to pmpaddr(i-1) are
+          ignored"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "configure 2 PMP entries (the 2 first ones in incrementing order)
+          with L=1,\n  - reuse of VP_PMP_F003_S001_I000 sequence"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST03(group) => FTR08-a and FTR08-b\n  [check that HW
+          implemented PMP entries are not writable/readable in M-mode (L=1)]\n  [check
+          that no HW implemented PMP entry are writable/readable in S or U modes (L=1)]\n\
+          \    - before any configuration, check all pmp(i)cfg and pmpaddr(i) are
+          M-mode read zero\n    - configure PMP entry (i) with L=1 (or 0):  pmp(i)cfg
+          and pmpaddr(i) maybe random values\n    - execute following tests specific
+          checks\n    - check only hart reset unlocks all => FTR08-b\n    - check
+          reset values: all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST03-2
+          (LOW-PRIO) = 2 times reuse/call of TST02-1\n[configure 2 PMP entries ([FTR02-b1]:
+          maybe mandatorily the 2 first ones): both with L=1,\n  - check for PMP entry
+          (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever
+          the SW mode => FTR08-a\n  - check for PMP entry (i) where L=1 that pmp(i)cfg
+          and pmpaddr(i) are not writable/readable in S or U modes]"
+- 002_configure_2_pmp_entries_L0_L1: !Subfeature
+    name: 002_configure_2_pmp_entries_L0_L1
+    tag: VP_PMP_F003_S003
+    next_elt_id: 1
+    display_order: 2
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F003_S003_I000
+        description: "{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
+          Privileged Architectures V20211203}\n\nThe L bit indicates that the PMP
+          entry is locked, i.e., writes to the configuration register and associated
+          address registers are ignored\nIf PMP entry (i) is locked, writes to pmp(i)cfg
+          and pmpaddr(i) are ignored\nLocked PMP entries remain locked until the hart
+          is reset\n\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II:
+          RISC-V Privileged Architectures V20211203}\n\nSetting the L bit locks the
+          PMP entry even when the A field is set to OFF\n\nAdditionally, if PMP entry
+          (i) is locked and pmp(i)cfg.A is set to TOR, writes to pmpaddr(i-1) are
+          ignored"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "configure 2 PMP entries (the 2 first ones in incrementing order)
+          at least one with L=1 and one with L=0,\n  - write PMP entry (i) with L=0/1
+          in M-mode\n  - A is random, should also be tried with A=OFF when L=1 (to
+          cover feature above)\n  - check PMP entry (i) written value in M-mode\n\
+          \  - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are
+          writable in M mode (read back the written value in M mode)\n  - check for
+          PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked
+          (M-mode check only)\n  - also check for PMP entry (i) where L=1 and pmp(i)cfg.A=TOR
+          that pmpaddr(i-1) is effectively locked\n  - apply hart reset\n  - check
+          for PMP entry (i) reset value (read zero) by reading in M mode\n  - write
+          PMP entry (i) in M-mode\n  - check PMP entry (i) written value in M-mode\n\
+          \nREUSABILITY\n  - if possible, the PMP entry number (i) is a configurable
+          parameter\n  - if possible, (L) value is a configurable parameter\n  - so
+          the same sub-functions are reused with varying (i) and (L) parameters"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST03(group) => FTR08-a and FTR08-b\n  [check that HW
+          implemented PMP entries are not writable/readable in M-mode (L=1)]\n  [check
+          that no HW implemented PMP entry are writable/readable in S or U modes (L=1)]\n\
+          \    - before any configuration, check all pmp(i)cfg and pmpaddr(i) are
+          M-mode read zero\n    - configure PMP entry (i) with L=1 (or 0):  pmp(i)cfg
+          and pmpaddr(i) maybe random values\n    - execute following tests specific
+          checks\n    - check only hart reset unlocks all => FTR08-b\n    - check
+          reset values: all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST03-3
+          (HIGH-PRIO) = 2 times reuse/call of TST02-1\n[configure 2 PMP entries ([FTR02-b1]:
+          maybe mandatorily the 2 first ones): one with L=1 and one with L=0,\n  -
+          check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively
+          locked whatever the SW mode => FTR08-a\n  - check for PMP entry (i) where
+          L=1 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes\n\
+          \  - check locked PMP entry (i) has no effect on unlocked PMP entry (j)\n\
+          \  - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are
+          writable/readable in M-mode only\n  - check for PMP entry (i) where L=0
+          that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes]"
+- 003_configure_N_pmp_entries: !Subfeature
+    name: 003_configure_N_pmp_entries
+    tag: VP_PMP_F003_S004
+    next_elt_id: 1
+    display_order: 3
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F003_S004_I000
+        description: "{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
+          Privileged Architectures V20211203}\n\nThe L bit indicates that the PMP
+          entry is locked, i.e., writes to the configuration register and associated
+          address registers are ignored\nIf PMP entry (i) is locked, writes to pmp(i)cfg
+          and pmpaddr(i) are ignored\nLocked PMP entries remain locked until the hart
+          is reset\n\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II:
+          RISC-V Privileged Architectures V20211203}\n\nSetting the L bit locks the
+          PMP entry even when the A field is set to OFF\n\nAdditionally, if PMP entry
+          (i) is locked and pmp(i)cfg.A is set to TOR, writes to pmpaddr(i-1) are
+          ignored"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "configure N PMP entries (the N first ones in incrementing order)
+          at least one with L=1 and one with L=0,\n  - reuse of VP_PMP_F003_S003_I000
+          sequence"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST03(group) => FTR08-a and FTR08-b\n  [check that HW
+          implemented PMP entries are not writable/readable in M-mode (L=1)]\n  [check
+          that no HW implemented PMP entry are writable/readable in S or U modes (L=1)]\n\
+          \    - before any configuration, check all pmp(i)cfg and pmpaddr(i) are
+          M-mode read zero\n    - configure PMP entry (i) with L=1 (or 0):  pmp(i)cfg
+          and pmpaddr(i) maybe random values\n    - execute following tests specific
+          checks\n    - check only hart reset unlocks all => FTR08-b\n    - check
+          reset values: all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST03-4
+          (LOW-PRIO) = N times reuse/call of TST02-1\n[configure N PMP entries ([FTR02-b1]:
+          maybe mandatorily the N first ones): at least one with L=1 and one with
+          L=0,\n  - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i)
+          are effectively locked whatever the SW mode => FTR08-a\n  - check for PMP
+          entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are not writable/readable
+          in S or U modes\n  - check locked PMP entry (i) has no effect on unlocked
+          PMP entry (j)\n  - check for PMP entry (i) where L=0 that pmp(i)cfg and
+          pmpaddr(i) are writable/readable in M-mode only\n  - check for PMP entry
+          (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in
+          S or U modes]"
+- 004_configure_8_pmp_entries: !Subfeature
+    name: 004_configure_8_pmp_entries
+    tag: VP_PMP_F003_S005
+    next_elt_id: 1
+    display_order: 4
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F003_S005_I000
+        description: "{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V
+          Privileged Architectures V20211203}\n\nThe L bit indicates that the PMP
+          entry is locked, i.e., writes to the configuration register and associated
+          address registers are ignored\nIf PMP entry (i) is locked, writes to pmp(i)cfg
+          and pmpaddr(i) are ignored\nLocked PMP entries remain locked until the hart
+          is reset\n\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II:
+          RISC-V Privileged Architectures V20211203}\n\nSetting the L bit locks the
+          PMP entry even when the A field is set to OFF\n\nAdditionally, if PMP entry
+          (i) is locked and pmp(i)cfg.A is set to TOR, writes to pmpaddr(i-1) are
+          ignored"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "configure all 8 PMP entries (in incrementing order) at least
+          one with L=1 and one with L=0,\n  - reuse of VP_PMP_F003_S003_I000 sequence"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST03(group) => FTR08-a and FTR08-b\n  [check that HW
+          implemented PMP entries are not writable/readable in M-mode (L=1)]\n  [check
+          that no HW implemented PMP entry are writable/readable in S or U modes (L=1)]\n\
+          \    - before any configuration, check all pmp(i)cfg and pmpaddr(i) are
+          M-mode read zero\n    - configure PMP entry (i) with L=1 (or 0):  pmp(i)cfg
+          and pmpaddr(i) maybe random values\n    - execute following tests specific
+          checks\n    - check only hart reset unlocks all => FTR08-b\n    - check
+          reset values: all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST03-5
+          (HIGH-PRIO) = 8 times reuse/call of TST02-1\n[configure 8 PMP entries: at
+          least one with L=1 and one with L=0,\n  - check for PMP entry (i) where
+          L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW
+          mode => FTR08-a\n  - check for PMP entry (i) where L=1 that pmp(i)cfg and
+          pmpaddr(i) are not writable/readable in S or U modes\n  - check locked PMP
+          entry (i) has no effect on unlocked PMP entry (j)\n  - check for PMP entry
+          (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode
+          only\n  - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i)
+          are not writable/readable in S or U modes]"
+vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
+io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
+config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
+ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'

verif/docs/VerifPlans/PMP/VP_IP004.yml

@@ -0,0 +1,146 @@
+!Feature
+next_elt_id: 4
+name: CSRs programming order
+id: 4
+display_order: 4
+subfeatures: !!omap
+- 000_configure_1_pmp_entry: !Subfeature
+    name: 000_configure_1_pmp_entry
+    tag: VP_PMP_F004_S001
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F004_S001_I000
+        description: "{Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures
+          V20211203}\n\nthe lowest-numbered PMP CSRs must be implemented first (QUESTION:
+          does it mean programmed first)\nAll PMP CSR fields are WARL and may be read-only
+          zero (QUESTION: does read-only zero mean not implemented?)"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "configure any PMP entry (i), but the first one\n  - reuse of
+          VP_PMP_F003_S003_I000 sequence (Feature: \"CSRs locked access\")"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST04 => FTR02-b1 and FTR02-b2\n  [check if the lowest-numbered
+          PMP CSRs must be programmed first before programming higher-numbered ones]\n
+          \nTST04-1 (LOW-PRIO) extends TST02-1\n[configure any PMP entry, but the
+          first one\n  - check for configured PMP entry (i), pmp(i)cfg and pmpaddr(i)
+          are writable/readable in M-mode only\n  - check for not configured PMP entry
+          (i), pmp(i)cfg and pmpaddr(i) are M-mode read zero]"
+- 001_configure_2_pmp_entries: !Subfeature
+    name: 001_configure_2_pmp_entries
+    tag: VP_PMP_F004_S002
+    next_elt_id: 1
+    display_order: 1
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F004_S002_I000
+        description: "{Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures
+          V20211203}\n\nthe lowest-numbered PMP CSRs must be implemented first (QUESTION:
+          does it mean programmed first)\nAll PMP CSR fields are WARL and may be read-only
+          zero (QUESTION: does read-only zero mean not implemented?)"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "configure 2 non-adjacent PMP entries (highest-numbered ones
+          first) (avoid the first PMP entry)\n  - reuse of VP_PMP_F003_S003_I000 sequence
+          (Feature: \"CSRs locked access\")"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST04 => FTR02-b1 and FTR02-b2\n  [check if the lowest-numbered
+          PMP CSRs must be programmed first before programming higher-numbered ones]\n
+          \nTST04-2 (HIGH-PRIO) extends TST02-2\n[configure 2 non-adjacent PMP entries
+          (highest-numbered ones first) (avoid the first PMP entry)\n  - check for
+          configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are writable/readable
+          in M-mode only\n  - check for not configured PMP entry (i), pmp(i)cfg and
+          pmpaddr(i) are M-mode read zero]"
+- 002_configure_N_pmp_entries: !Subfeature
+    name: 002_configure_N_pmp_entries
+    tag: VP_PMP_F004_S003
+    next_elt_id: 1
+    display_order: 2
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F004_S003_I000
+        description: "{Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures
+          V20211203}\n\nthe lowest-numbered PMP CSRs must be implemented first (QUESTION:
+          does it mean programmed first)\nAll PMP CSR fields are WARL and may be read-only
+          zero (QUESTION: does read-only zero mean not implemented?)"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "configure N PMP entries (highest-numbered ones first) (as non-adjacent
+          as possible, and avoid the first PMP entry)\n  - reuse of VP_PMP_F003_S003_I000
+          sequence (Feature: \"CSRs locked access\")"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST04 => FTR02-b1 and FTR02-b2\n  [check if the lowest-numbered
+          PMP CSRs must be programmed first before programming higher-numbered ones]\n
+          \nTST04-3 (LOW-PRIO) extends TST02-3\n[configure N PMP entries (highest-numbered
+          ones first) (as non-adjacent as possible, and avoid the first PMP entry)\n\
+          \  - check for configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are writable/readable
+          in M-mode only\n  - check for not configured PMP entry (i), pmp(i)cfg and
+          pmpaddr(i) are M-mode read zero]"
+- 003_configure_8_pmp_entries: !Subfeature
+    name: 003_configure_8_pmp_entries
+    tag: VP_PMP_F004_S004
+    next_elt_id: 1
+    display_order: 3
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F004_S004_I000
+        description: "{Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures
+          V20211203}\n\nthe lowest-numbered PMP CSRs must be implemented first (QUESTION:
+          does it mean programmed first)\nAll PMP CSR fields are WARL and may be read-only
+          zero (QUESTION: does read-only zero mean not implemented?)"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "configure all 8 PMP entries (highest-numbered ones first)\n\
+          \  - reuse of VP_PMP_F003_S003_I000 sequence (Feature: \"CSRs locked access\"\
+          )"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST04 => FTR02-b1 and FTR02-b2\n  [check if the lowest-numbered
+          PMP CSRs must be programmed first before programming higher-numbered ones]\n
+          \nTST04-4 (HIGH-PRIO) extends TST02-4\n[configure 8 PMP entries (highest-numbered
+          ones first)\n  - check for configured PMP entry (i), pmp(i)cfg and pmpaddr(i)
+          are writable/readable in M-mode only]"
+vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
+io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
+config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
+ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'

verif/docs/VerifPlans/PMP/VP_IP005.yml

@@ -0,0 +1,90 @@
+!Feature
+next_elt_id: 2
+name: CSRs Hardwired regions
+id: 5
+display_order: 5
+subfeatures: !!omap
+- 000_access with L=0: !Subfeature
+    name: 000_access with L=0
+    tag: VP_PMP_F005_S001
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F005_S001_I000
+        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
+          Certain regions’ privileges can be hardwired: so only ever be visible in
+          machine mode but in no lower-privilege layers.\n\n{Section 3.7.1 Page 57
+          Volume II: RISC-V Privileged Architectures V20211203}\nImplementations may
+          implement zero, 16, or 64 PMP CSRs\n\n{https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/PMP.html}\n
+          A maximum of 16 PMP entries are supported.\nAll PMP CSRs are always implemented,
+          but CSRs (or bitfields of CSRs) related to PMP entries with number CVA6Cfg.NrPMPEntries
+          and above are hardwired to zero.\n\nTRISTAN\n8 PMP entries are implemented"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "configure the first 8 PMP entries with L=0\n  - for each PMP
+          entry (i), check several times that pmp(i)cfg and pmpaddr(i) can be written
+          and can be read back exactly the same (in M-mode)\n\nfor the last 8 PMP
+          entries, check that pmp(i)cfg and pmpaddr(i) always read zero after being
+          written (in M-mode with L=0)"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST05 => FTR01-c and FTR01-c-extended\n  [check all
+          regions are configurable in M-mode to make sure none is hardwired]\n  [regions
+          hardwired privileges might only ever be visible in M-mode]\n\nTST05-1 (HIGH-PRIO)
+          extends TST02-4\n  - check the written pmp(i)cfg and pmpaddr(i) values can
+          be read exactly the same as written"
+- 001_access with L=1: !Subfeature
+    name: 001_access with L=1
+    tag: VP_PMP_F005_S002
+    next_elt_id: 1
+    display_order: 1
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F005_S002_I000
+        description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n
+          Certain regions’ privileges can be hardwired: so only ever be visible in
+          machine mode but in no lower-privilege layers.\n\n{Section 3.7.1 Page 57
+          Volume II: RISC-V Privileged Architectures V20211203}\nImplementations may
+          implement zero, 16, or 64 PMP CSRs\n\n{https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/PMP.html}\n
+          A maximum of 16 PMP entries are supported.\nAll PMP CSRs are always implemented,
+          but CSRs (or bitfields of CSRs) related to PMP entries with number CVA6Cfg.NrPMPEntries
+          and above are hardwired to zero.\n\nTRISTAN\n8 PMP entries are implemented"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "configure the first 8 PMP entries with L=1\n  - for each PMP
+          entry (i), check once that pmp(i)cfg and pmpaddr(i) can be written and can
+          be read back exactly the same (in M-mode)\n  - apply hart reset\n  - for
+          each PMP entry (i), check once that pmp(i)cfg and pmpaddr(i) can be written
+          and can be read back exactly the same (in M-mode)\n\nfor the last 8 PMP
+          entries, check that pmp(i)cfg and pmpaddr(i) always read zero after being
+          written (in M-mode with L=1)"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST05 => FTR01-c and FTR01-c-extended\n  [check all
+          regions are configurable in M-mode to make sure none is hardwired]\n  [regions
+          hardwired privileges might only ever be visible in M-mode]\n\nTST05-2 (LOW-PRIO)
+          extends TST03-5\n  - check the written pmp(i)cfg and pmpaddr(i) values can
+          be read exactly the same as written (before hart reset)"
+vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
+io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
+config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
+ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'

verif/docs/VerifPlans/PMP/VP_IP006.yml

@@ -0,0 +1,82 @@
+!Feature
+next_elt_id: 2
+name: CSRs reserved values
+id: 6
+display_order: 6
+subfeatures: !!omap
+- 000_access with L=0: !Subfeature
+    name: 000_access with L=0
+    tag: VP_PMP_F006_S001
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F006_S001_I000
+        description: "{Page 58 Volume II: RISC-V Privileged Architectures V20211203}\n
+          \nThe R, W, and X fields form a collective WARL field for which the combinations
+          with R=0 and W=1 are reserved."
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "repeat following sequence several times on some PMP entries\n\
+          \  - write totally random values to pmp(i)cfg and pmpaddr(i), but with L=0\n\
+          \  - check all pmp(i)cfg and pmpaddr(i) can be read back exactly the same
+          as written except:\n      - except with the reserved combinations [R=0 and
+          W=1]\n      - except with A=NA4 which must not be selectable as G>0"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST06 => FTR04-a\n[PMP CSR fields are WARL: PMP entry
+          combinations with R=0 and W=1 are reserved/can’t be read]\n[permissions
+          fields could be randomly written; should we try randomization ?]\n\nTST06-1
+          (HIGH-PRIO) extends TST02-4\n  - write totally random values to pmp(i)cfg
+          and pmpaddr(i)\n  - check all pmp(i)cfg and pmpaddr(i) can be read exactly
+          the same as written except for the reserved combinations with R=0 and W=1"
+- 001_access with L=1: !Subfeature
+    name: 001_access with L=1
+    tag: VP_PMP_F006_S002
+    next_elt_id: 1
+    display_order: 1
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F006_S002_I000
+        description: "{Page 58 Volume II: RISC-V Privileged Architectures V20211203}\n
+          \nThe R, W, and X fields form a collective WARL field for which the combinations
+          with R=0 and W=1 are reserved."
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "repeat following sequence several times on some PMP entries\n\
+          \  - write totally random values to pmp(i)cfg and pmpaddr(i), but with L=1\n\
+          \  - check all pmp(i)cfg and pmpaddr(i) can be read back exactly the same
+          as written:\n      - except with the reserved combinations [R=0 and W=1]\n\
+          \      - except with A=NA4 which must not be selectable as G>0\n  - apply
+          hart reset"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST06 => FTR04-a\n[PMP CSR fields are WARL: PMP entry
+          combinations with R=0 and W=1 are reserved/can’t be read]\n[permissions
+          fields could be randomly written; should we try randomization ?]\n\nTST06-2
+          (LOW-PRIO) extends TST03-5\n  - write totally random values to pmp(i)cfg
+          and pmpaddr(i)\n  - check all pmp(i)cfg and pmpaddr(i) can be read exactly
+          the same as written except for the reserved combinations with R=0 and W=1
+          (before hart reset)"
+vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
+io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
+config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
+ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'

verif/docs/VerifPlans/PMP/VP_IP010.yml

@@ -0,0 +1,128 @@
+!Feature
+next_elt_id: 4
+name: no cfg matching/defined
+id: 10
+display_order: 10
+subfeatures: !!omap
+- 000_no matching entry - M mode access: !Subfeature
+    name: 000_no matching entry - M mode access
+    tag: VP_PMP_F010_S001
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F010_S001_I000
+        description: "{Page 60 Section \"Priority and Matching Logic\" Volume II:
+          RISC-V Privileged Architectures V20211203}\n\nIf no PMP entry matches an
+          M-mode access, the access succeeds"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: check M-mode access succeeds if no PMP entry matches
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nFTR09-e\n[If no PMP entry matches an M-mode access,
+          the access succeeds]\n \nTST10-1 (HIGH-PRIO) => FTR09-e\n[check M-mode access
+          succeeds if no PMP entry matches]"
+- 001_no defined entry - M mode access: !Subfeature
+    name: 001_no defined entry - M mode access
+    tag: VP_PMP_F010_S002
+    next_elt_id: 1
+    display_order: 1
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F010_S002_I000
+        description: "{Page 60 Section \"Priority and Matching Logic\" Volume II:
+          RISC-V Privileged Architectures V20211203}\n\nIf no PMP entry matches an
+          M-mode access, the access succeeds\nQUESTION: what happens if no PMP entry
+          is implemented ?\nASSUMPTION: access succeeds"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: check M-mode access succeeds if no PMP entry defined
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nFTR09-e-question\n[what happens if no PMP entry is implemented
+          ?]\n \nTST10-2 (HIGH-PRIO) => FTR09-e-question\n[check M-mode access succeeds
+          if no PMP entry defined]"
+- 002_no matching entry - S/U mode access: !Subfeature
+    name: 002_no matching entry - S/U mode access
+    tag: VP_PMP_F010_S003
+    next_elt_id: 1
+    display_order: 2
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F010_S003_I000
+        description: "{Page 60 Section \"Priority and Matching Logic\" Volume II:
+          RISC-V Privileged Architectures V20211203}\n\nIf no PMP entry matches an
+          S-mode or U-mode access, but at least one PMP entry is implemented, the
+          access fails"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: check S or U mode access fails when no PMP entry matching and
+          at least one PMP entry implemented
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nFTR09-f\n[If no PMP entry matches an S-mode or U-mode
+          access, but at least one PMP entry is implemented, the access fails]\n\n
+          TST10-3 (HIGH-PRIO) => FTR09-f\n[check S or U mode access fails when no
+          PMP entry matching and at least one PMP entry implemented]"
+- 003_no defined entry - S/U mode access: !Subfeature
+    name: 003_no defined entry - S/U mode access
+    tag: VP_PMP_F010_S004
+    next_elt_id: 1
+    display_order: 3
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F010_S004_I000
+        description: "{Page 60 Section \"Priority and Matching Logic\" Volume II:
+          RISC-V Privileged Architectures V20211203}\n\nIf no PMP entry matches an
+          S-mode or U-mode access, but at least one PMP entry is implemented, the
+          access fails\nQUESTION: what happens if no PMP entry is implemented ?\n
+          ASSUMPTION: access fails"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: check S or U mode access fails when no PMP entry implemented
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nFTR09-f-question\n[what happens if no PMP entry is implemented
+          ?]\n \nTST10-4 (HIGH-PRIO) => FTR09-f-question\n[check S or U mode access
+          fails when no PMP entry implemented]"
+vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
+io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
+config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
+ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'

verif/docs/VerifPlans/PMP/VP_IP019.yml

@@ -0,0 +1,525 @@
+!Feature
+next_elt_id: 20
+name: cfg NA4 not selectable
+id: 19
+display_order: 19
+subfeatures: !!omap
+- 000_fetch_L0_X1_addr_hit: !Subfeature
+    name: 000_fetch_L0_X1_addr_hit
+    tag: VP_PMP_F019_S011
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S011_I000
+        description: 'reuse of VP_PMP_F019_S011_I000 feature description (Cf. Feature:
+          "cfg NA4 access S/U")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S011_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access S/U\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)\n\nCHECK UPDATE\n  - check instruction fetch access-fault
+          exception raised"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 001_fetch_L1_X1_addr_hit: !Subfeature
+    name: 001_fetch_L1_X1_addr_hit
+    tag: VP_PMP_F019_S014
+    next_elt_id: 1
+    display_order: 1
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S014_I000
+        description: 'reuse of VP_PMP_F019_S014_I000 feature description (Cf. Feature:
+          "cfg NA4 access S/U")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S014_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access S/U\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)\n\nCHECK UPDATE\n  - check instruction fetch access-fault
+          exception raised"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 002_load_L0_R1_addr_hit: !Subfeature
+    name: 002_load_L0_R1_addr_hit
+    tag: VP_PMP_F019_S021
+    next_elt_id: 1
+    display_order: 2
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S021_I000
+        description: 'reuse of VP_PMP_F019_S021_I000 feature description (Cf. Feature:
+          "cfg NA4 access S/U")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S021_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access S/U\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)\n\nCHECK UPDATE\n  - check load access-fault exception
+          raised"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 003_load_L1_R1_addr_hit: !Subfeature
+    name: 003_load_L1_R1_addr_hit
+    tag: VP_PMP_F019_S024
+    next_elt_id: 1
+    display_order: 3
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S024_I000
+        description: 'reuse of VP_PMP_F019_S024_I000 feature description (Cf. Feature:
+          "cfg NA4 access S/U")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S024_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access S/U\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)\n\nCHECK UPDATE\n  - check load access-fault exception
+          raised"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 004_store_L0_W1_addr_hit: !Subfeature
+    name: 004_store_L0_W1_addr_hit
+    tag: VP_PMP_F019_S031
+    next_elt_id: 1
+    display_order: 4
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S031_I000
+        description: 'reuse of VP_PMP_F019_S031_I000 feature description (Cf. Feature:
+          "cfg NA4 access S/U")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S031_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access S/U\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)\n\nCHECK UPDATE\n  - check store access-fault exception
+          raised"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 005_store_L1_W1_addr_hit: !Subfeature
+    name: 005_store_L1_W1_addr_hit
+    tag: VP_PMP_F019_S034
+    next_elt_id: 1
+    display_order: 5
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S034_I000
+        description: 'reuse of VP_PMP_F019_S034_I000 feature description (Cf. Feature:
+          "cfg NA4 access S/U")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S034_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access S/U\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)\n\nCHECK UPDATE\n  - check store access-fault exception
+          raised"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 006_load_MPP_L0_R1_addr_hit: !Subfeature
+    name: 006_load_MPP_L0_R1_addr_hit
+    tag: VP_PMP_F019_S041
+    next_elt_id: 1
+    display_order: 6
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S041_I000
+        description: 'reuse of VP_PMP_F019_S041_I000 feature description (Cf. Feature:
+          "cfg NA4 access S/U")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S041_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access S/U\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)\n\nCHECK UPDATE\n  - check load access-fault exception
+          raised"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 007_load_MPP_L1_R1_addr_hit: !Subfeature
+    name: 007_load_MPP_L1_R1_addr_hit
+    tag: VP_PMP_F019_S044
+    next_elt_id: 1
+    display_order: 7
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S044_I000
+        description: 'reuse of VP_PMP_F019_S044_I000 feature description (Cf. Feature:
+          "cfg NA4 access S/U")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S044_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access S/U\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)\n\nCHECK UPDATE\n  - check load access-fault exception
+          raised"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 008_store_MPP_L0_W1_addr_hit: !Subfeature
+    name: 008_store_MPP_L0_W1_addr_hit
+    tag: VP_PMP_F019_S051
+    next_elt_id: 1
+    display_order: 8
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S051_I000
+        description: 'reuse of VP_PMP_F019_S051_I000 feature description (Cf. Feature:
+          "cfg NA4 access S/U")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S051_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access S/U\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)\n\nCHECK UPDATE\n  - check store access-fault exception
+          raised"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 009_store_MPP_L1_W1_addr_hit: !Subfeature
+    name: 009_store_MPP_L1_W1_addr_hit
+    tag: VP_PMP_F019_S054
+    next_elt_id: 1
+    display_order: 9
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S054_I000
+        description: 'reuse of VP_PMP_F019_S054_I000 feature description (Cf. Feature:
+          "cfg NA4 access S/U")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S054_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access S/U\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)\n\nCHECK UPDATE\n  - check store access-fault exception
+          raised"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 010_fetch_L0_X1_addr_hit: !Subfeature
+    name: 010_fetch_L0_X1_addr_hit
+    tag: VP_PMP_F019_S011
+    next_elt_id: 1
+    display_order: 10
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S011_I000
+        description: 'reuse of VP_PMP_F019_S011_I000 feature description (Cf. Feature:
+          "cfg NA4 access M")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S011_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access M\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 011_fetch_L1_X1_addr_hit: !Subfeature
+    name: 011_fetch_L1_X1_addr_hit
+    tag: VP_PMP_F019_S014
+    next_elt_id: 1
+    display_order: 11
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S014_I000
+        description: 'reuse of VP_PMP_F019_S014_I000 feature description (Cf. Feature:
+          "cfg NA4 access M")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S014_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access M\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)\n\nCHECK UPDATE\n  - check store access-fault exception
+          raised (TODO: is M mode access prevented by A=OFF)"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 012_load_L0_R1_addr_hit: !Subfeature
+    name: 012_load_L0_R1_addr_hit
+    tag: VP_PMP_F019_S021
+    next_elt_id: 1
+    display_order: 12
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S021_I000
+        description: 'reuse of VP_PMP_F019_S021_I000 feature description (Cf. Feature:
+          "cfg NA4 access M")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S021_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access M\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 013_load_L1_R1_addr_hit: !Subfeature
+    name: 013_load_L1_R1_addr_hit
+    tag: VP_PMP_F019_S024
+    next_elt_id: 1
+    display_order: 13
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S024_I000
+        description: 'reuse of VP_PMP_F019_S024_I000 feature description (Cf. Feature:
+          "cfg NA4 access M")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S024_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access M\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)\n\nCHECK UPDATE\n  - check store access-fault exception
+          raised (TODO: is M mode access prevented by A=OFF)"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 014_store_L0_W1_addr_hit: !Subfeature
+    name: 014_store_L0_W1_addr_hit
+    tag: VP_PMP_F019_S031
+    next_elt_id: 1
+    display_order: 14
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S031_I000
+        description: 'reuse of VP_PMP_F019_S031_I000 feature description (Cf. Feature:
+          "cfg NA4 access M")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S031_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access M\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 015_store_L1_W1_addr_hit: !Subfeature
+    name: 015_store_L1_W1_addr_hit
+    tag: VP_PMP_F019_S034
+    next_elt_id: 1
+    display_order: 15
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S034_I000
+        description: 'reuse of VP_PMP_F019_S034_I000 feature description (Cf. Feature:
+          "cfg NA4 access M")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S034_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access M\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)\n\nCHECK UPDATE\n  - check store access-fault exception
+          raised (TODO: is M mode access prevented by A=OFF)"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 016_load_MPP_L0_R1_addr_hit: !Subfeature
+    name: 016_load_MPP_L0_R1_addr_hit
+    tag: VP_PMP_F019_S041
+    next_elt_id: 1
+    display_order: 16
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S041_I000
+        description: 'reuse of VP_PMP_F019_S041_I000 feature description (Cf. Feature:
+          "cfg NA4 access M")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S041_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access M\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 017_load_MPP_L1_R1_addr_hit: !Subfeature
+    name: 017_load_MPP_L1_R1_addr_hit
+    tag: VP_PMP_F019_S044
+    next_elt_id: 1
+    display_order: 17
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S044_I000
+        description: 'reuse of VP_PMP_F019_S044_I000 feature description (Cf. Feature:
+          "cfg NA4 access M")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S044_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access M\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)\n\nCHECK UPDATE\n  - check store access-fault exception
+          raised (TODO: is M mode access prevented by A=OFF)"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 018_store_MPP_L0_W1_addr_hit: !Subfeature
+    name: 018_store_MPP_L0_W1_addr_hit
+    tag: VP_PMP_F019_S051
+    next_elt_id: 1
+    display_order: 18
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S051_I000
+        description: 'reuse of VP_PMP_F019_S051_I000 feature description (Cf. Feature:
+          "cfg NA4 access M")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S051_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access M\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 019_store_MPP_L1_W1_addr_hit: !Subfeature
+    name: 019_store_MPP_L1_W1_addr_hit
+    tag: VP_PMP_F019_S054
+    next_elt_id: 1
+    display_order: 19
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F019_S054_I000
+        description: 'reuse of VP_PMP_F019_S054_I000 feature description (Cf. Feature:
+          "cfg NA4 access M")'
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "reuse of VP_PMP_F019_S054_I000 verification goals (Cf. Feature:
+          \"cfg NA4 access M\")\n\nCONFIGURATION\n    - check that pmpcfg(i).A=OFF
+          (by reading back)\n\nCHECK UPDATE\n  - check store access-fault exception
+          raised (TODO: is M mode access prevented by A=OFF)"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
+io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
+config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
+ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'

verif/docs/VerifPlans/PMP/VP_IP021.yml

@@ -0,0 +1,376 @@
+!Feature
+next_elt_id: 6
+name: multi entries NA4
+id: 21
+display_order: 21
+subfeatures: !!omap
+- 000_1_entry: !Subfeature
+    name: 000_1_entry
+    tag: VP_PMP_F021_S001
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F021_S001_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose a single PMP entry\n\nCONFIGURATION and ACCESS\n    -
+          for each pmp entry, apply any CONFIGURATION+ACCESS scenario above (Cf. Feature:
+          \"cfg NA4 access S/U/M\")\n    - make sure the pmp entries address ranges
+          are not overlapping/intersecting\n    - NB: obviously, pmp entry configurations
+          with different mstatus.MPRV/MPP values cannot be mixed in same test\n\n\
+          CHECK\n    - for each pmp entry, we should obtain the expected CHECK result\n\
+          \nREUSABILITY\n    - if possible, the number of PMP entries (N) is a configurable
+          parameter\n    - so a single test function can be reused"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST21(group)\n  [create scenarios where PMP entries
+          with A=2 (NA4) and with/without matching permissions\n    - check only NA4
+          defined addresses are matching]\nTST21-1 = extension of (TST11-11, TST11-21,
+          TST11-31, TST11-41, TST11-51,\n                        TST11-12, TST11-22,
+          TST11-32, TST11-42, TST11-52,\n                        TST11-13, TST11-23,
+          TST11-33, TST11-43, TST11-53,\n                        TST11-14, TST11-24,
+          TST11-34, TST11-44, TST11-54,\n                        TST11-15, TST11-25,
+          TST11-35, TST11-45, TST11-55,\n                        TST11-16, TST11-26,
+          TST11-36, TST11-46, TST11-56,\n                        TST12-11, TST12-21,
+          TST12-31, TST12-41, TST12-51,\n                        TST12-12, TST12-22,
+          TST12-32, TST12-42, TST12-52,\n                        TST12-13, TST12-23,
+          TST12-33, TST12-43, TST12-53,\n                        TST12-14, TST12-24,
+          TST12-34, TST12-44, TST12-54,\n                        TST12-15, TST12-25,
+          TST12-35, TST12-45, TST12-55,\n                        TST12-16, TST12-26,
+          TST12-36, TST12-46, TST12-56)\n[configure only one (any, but the first one)
+          PMP entry\n  - use A=NA4 for the PMP entry configuration\n  - execute the
+          chosen kind of access\n  - should be same result]"
+- 001_2_isolated_entries: !Subfeature
+    name: 001_2_isolated_entries
+    tag: VP_PMP_F021_S002
+    next_elt_id: 1
+    display_order: 1
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F021_S002_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any 2 PMP entries\n\nreuse of VP_PMP_F021_S001_I000 feature
+          description (Cf. Feature: \"multi entries NA4\")"
+        pfc: 3
+        test_type: 4
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST21(group)\n  [create scenarios where PMP entries
+          with A=2 (NA4) and with/without matching permissions\n    - check only NA4
+          defined addresses are matching]\nTST21-2 = extension of compatible pair
+          of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51,\n                \
+          \        \t\t\t\t\t\t\t\t\t TST11-12, TST11-22, TST11-32, TST11-42, TST11-52,\n\
+          \                        \t\t\t\t\t\t\t\t\t TST11-13, TST11-23, TST11-33,
+          TST11-43, TST11-53,\n                        \t\t\t\t\t\t\t\t\t TST11-14,
+          TST11-24, TST11-34, TST11-44, TST11-54,\n                        \t\t\t\t
+          \t\t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n         \
+          \               \t\t\t\t \t\t\t\t\t TST11-16, TST11-26, TST11-36, TST11-46,
+          TST11-56,\n                        \t\t\t\t\t\t\t\t\t TST12-11, TST12-21,
+          TST12-31, TST12-41, TST12-51,\n                        \t\t\t\t\t\t\t\t\t
+          TST12-12, TST12-22, TST12-32, TST12-42, TST12-52,\n                    \
+          \    \t\t\t\t\t\t\t\t\t TST12-13, TST12-23, TST12-33, TST12-43, TST12-53,\n\
+          \                        \t\t\t\t\t\t\t\t\t TST12-14, TST12-24, TST12-34,
+          TST12-44, TST12-54,\n                        \t\t\t\t\t\t\t\t\t TST12-15,
+          TST12-25, TST12-35, TST12-45, TST12-55,\n                        \t\t\t\t
+          \t\t\t\t\t TST12-16, TST12-26, TST12-36, TST12-46, TST12-56)\n[configure
+          2 non-adjacent PMP entries (highest-numbered ones first) (avoid the first
+          PMP entry)\n  - use A=NA4 for each PMP entry configuration\n  - execute
+          the 2 kinds of accesses (if possible to chain due to potential access-fault
+          exception)\n  - should be same 2 results]"
+- 002_N_isolated_entries: !Subfeature
+    name: 002_N_isolated_entries
+    tag: VP_PMP_F021_S003
+    next_elt_id: 1
+    display_order: 2
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F021_S003_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any N PMP entries (2<N<8)\n\nreuse of VP_PMP_F021_S001_I000
+          feature description (Cf. Feature: \"multi entries NA4\")"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST21(group)\n  [create scenarios where PMP entries
+          with A=2 (NA4) and with/without matching permissions\n    - check only NA4
+          defined addresses are matching]\nTST21-3 = extension of compatible group(N)
+          of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51,\n                \
+          \        \t\t\t\t \t\t\t\t\t\t\t TST11-12, TST11-22, TST11-32, TST11-42,
+          TST11-52,\n                        \t\t\t\t\t\t\t\t\t\t\t TST11-13, TST11-23,
+          TST11-33, TST11-43, TST11-53,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t TST11-14, TST11-24, TST11-34, TST11-44, TST11-54,\n               \
+          \         \t\t\t\t \t\t\t\t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45,
+          TST11-55,\n                        \t\t\t\t\t\t\t\t\t\t\t TST11-16, TST11-26,
+          TST11-36, TST11-46, TST11-56,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t TST12-11, TST12-21, TST12-31, TST12-41, TST12-51,\n               \
+          \         \t\t\t\t \t\t\t\t\t\t\t TST12-12, TST12-22, TST12-32, TST12-42,
+          TST12-52,\n                        \t\t\t\t\t\t\t\t\t\t\t TST12-13, TST12-23,
+          TST12-33, TST12-43, TST12-53,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t TST12-14, TST12-24, TST12-34, TST12-44, TST12-54,\n               \
+          \         \t\t\t\t \t\t\t\t\t\t\t TST12-15, TST12-25, TST12-35, TST12-45,
+          TST12-55,\n                        \t\t\t\t\t\t\t\t\t\t\t TST12-16, TST12-26,
+          TST12-36, TST12-46, TST12-56)\n[configure N PMP entries (highest-numbered
+          ones first) (as non-adjacent as possible, and avoid the first PMP entry)\n\
+          \  - use A=NA4 for each PMP entry configuration\n  - execute the N kinds
+          of accesses (if possible to chain due to potential access-fault exception)\n\
+          \  - should be same N results]"
+- 003_8_isolated_entries: !Subfeature
+    name: 003_8_isolated_entries
+    tag: VP_PMP_F021_S004
+    next_elt_id: 1
+    display_order: 3
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F021_S004_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose all 8 PMP entries\n\nreuse of VP_PMP_F021_S001_I000 feature
+          description (Cf. Feature: \"multi entries NA4\")"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST21(group)\n  [create scenarios where PMP entries
+          with A=2 (NA4) and with/without matching permissions\n    - check only NA4
+          defined addresses are matching]\nTST21-4 = extension of compatible group(8)
+          of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51,\n                \
+          \        \t\t\t\t \t\t\t\t\t\t\t TST11-12, TST11-22, TST11-32, TST11-42,
+          TST11-52,\n                        \t\t\t\t\t\t\t\t\t\t\t TST11-13, TST11-23,
+          TST11-33, TST11-43, TST11-53,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t TST11-14, TST11-24, TST11-34, TST11-44, TST11-54,\n               \
+          \         \t\t\t\t \t\t\t\t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45,
+          TST11-55,\n                        \t\t\t\t\t\t\t\t\t\t\t TST11-16, TST11-26,
+          TST11-36, TST11-46, TST11-56,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t TST12-11, TST12-21, TST12-31, TST12-41, TST12-51,\n               \
+          \         \t\t\t\t \t\t\t\t\t\t\t TST12-12, TST12-22, TST12-32, TST12-42,
+          TST12-52,\n                        \t\t\t\t\t\t\t\t\t\t\t TST12-13, TST12-23,
+          TST12-33, TST12-43, TST12-53,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t TST12-14, TST12-24, TST12-34, TST12-44, TST12-54,\n               \
+          \         \t\t\t\t \t\t\t\t\t\t\t TST12-15, TST12-25, TST12-35, TST12-45,
+          TST12-55,\n                        \t\t\t\t\t\t\t\t\t\t\t TST12-16, TST12-26,
+          TST12-36, TST12-46, TST12-56)\n[configure 8 PMP entries (highest-numbered
+          ones first)\n  - use A=NA4 for each PMP entry configuration\n  - execute
+          the 8 kinds of accesses (if possible to chain due to potential access-fault
+          exception)\n  - should be same 8 results]"
+- 004_2_intersecting_entries_fail: !Subfeature
+    name: 004_2_intersecting_entries_fail
+    tag: VP_PMP_F021_S005
+    next_elt_id: 1
+    display_order: 4
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F021_S005_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any 2 PMP entries\n\nCONFIGURATION and ACCESS (Cf. Feature:
+          \"cfg NA4 access S/U/M\")\n    - for the least-numbered pmp entry, apply
+          any CONFIGURATION+ACCESS scenario with access-fault\n    - for the highest-numbered
+          pmp entry, apply any CONFIGURATION+ACCESS scenario without access-fault\n\
+          \    - make sure the pmp entries address ranges are overlapping/intersecting
+          (at least at 4 consecutive bytes)\n    - for each pmp entry, execute one
+          access in its associated pmp address region but outside the overlapping/intersecting
+          address range\n    - execute one additional access inside the overlapping/intersecting
+          address range\n    - NB: obviously, pmp entry configurations with different
+          access-modes (S/U vs. M) cannot be easily mixed in same test\n    - NB:
+          obviously, pmp entry configurations with different mstatus.MPRV/MPP values
+          cannot be mixed in same test\n\nCHECK\n    - for each pmp entry, access
+          outside the overlapping/intersecting address range should give the expected
+          CHECK result\n    - access inside the overlapping/intersecting address range
+          should generate the access-type related access-fault\n\nREUSABILITY\n  \
+          \  - if possible, the number of PMP entries (N) is a configurable parameter\n\
+          \    - so a single test function can be reused"
+        pfc: 3
+        test_type: 4
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST51(group) => FTR09-a, FTR09-b and FTR09-c\n  [create
+          scenarios where 2 PMP entries with same pmpaddr\n    - one without matching
+          permissions or with A=OFF\n    - one with matching permissions and A=NA4/NAPOT/TOR\n\
+          \    - any of them can be the lowest-numbered PMP entry]\nTST51-1\n[configure
+          2 PMP entries\n  - configure the lowest-numbered PMP entry with  (TST11-12,
+          TST11-22, TST11-32, TST11-42, TST11-52,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-12, TST12-22,
+          TST12-32, TST12-42, TST12-52,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t TST12-15, TST12-25, TST12-35, TST12-45, TST12-55,\n           \
+          \                                        TST13-12, TST13-22, TST13-32, TST13-42,
+          TST13-52,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST13-15,
+          TST13-25, TST13-35, TST13-45, TST13-55,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST14-12, TST14-22, TST14-32, TST14-42, TST14-52,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-15, TST14-25,
+          TST14-35, TST14-45, TST14-55,\n                                        \
+          \           TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n        \
+          \                \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-15, TST15-25, TST15-35,
+          TST15-45, TST15-55,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t
+          TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n                    \
+          \    \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-15, TST16-25, TST16-35, TST16-45,
+          TST16-55,\n                                                   TST17-12,
+          TST17-22, TST17-32, TST17-42, TST17-52,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST17-15, TST17-25, TST17-35, TST17-45, TST17-55,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST18-12, TST18-22,
+          TST18-32, TST18-42, TST18-52,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t TST18-15, TST18-25, TST18-35, TST18-45, TST18-55)\n  - configure
+          the highest-numbered PMP entry with  (TST11-11, TST11-21, TST11-31, TST11-41,
+          TST11-51,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST11-14,
+          TST11-24, TST11-34, TST11-44, TST11-54,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t  TST12-11, TST12-21, TST12-31, TST12-41, TST12-51,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST12-14, TST12-24,
+          TST12-34, TST12-44, TST12-54,\n                                        \
+          \            TST13-11, TST13-21, TST13-31, TST13-41, TST13-51,\n       \
+          \                 \t\t\t\t\t\t\t\t\t \t\t\t\t\tTST13-14, TST13-24, TST13-34,
+          TST13-44, TST13-54,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t
+          \tTST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n                  \
+          \      \t\t\t\t\t\t\t\t\t \t\t\t\t\tTST14-14, TST14-24, TST14-34, TST14-44,
+          TST14-54,\n                                                    TST15-11,
+          TST15-21, TST15-31, TST15-41, TST15-51,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t  TST15-14, TST15-24, TST15-34, TST15-44, TST15-54,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST16-11, TST16-21,
+          TST16-31, TST16-41, TST16-51,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t  TST16-14, TST16-24, TST16-34, TST16-44, TST16-54)\n  - execute
+          the associated access\n  - check associated access-fault exception raised]"
+- 005_2_intersecting_entries_succeed: !Subfeature
+    name: 005_2_intersecting_entries_succeed
+    tag: VP_PMP_F021_S006
+    next_elt_id: 1
+    display_order: 5
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F021_S006_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any 2 PMP entries\n\nCONFIGURATION and ACCESS (Cf. Feature:
+          \"cfg NA4 access S/U/M\")\n    - for the least-numbered pmp entry, apply
+          any CONFIGURATION+ACCESS scenario without access-fault\n    - for the highest-numbered
+          pmp entry, apply any CONFIGURATION+ACCESS scenario with access-fault\n \
+          \   - make sure the pmp entries address ranges are overlapping/intersecting
+          (at least at 4 consecutive bytes)\n    - for each pmp entry, execute one
+          access in its associated pmp address region but outside the overlapping/intersecting
+          address range\n    - execute one additional access inside the overlapping/intersecting
+          address range\n    - NB: obviously, pmp entry configurations with different
+          access-modes (S/U vs. M) cannot be easily mixed in same test\n    - NB:
+          obviously, pmp entry configurations with different mstatus.MPRV/MPP values
+          cannot be mixed in same test\n\nCHECK\n    - for each pmp entry, access
+          outside the overlapping/intersecting address range should give the expected
+          CHECK result\n    - access inside the overlapping/intersecting address range
+          should not generate any access-fault\n\nREUSABILITY\n    - if possible,
+          the number of PMP entries (N) is a configurable parameter\n    - so a single
+          test function can be reused"
+        pfc: 3
+        test_type: 4
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST51(group) => FTR09-a, FTR09-b and FTR09-c\n  [create
+          scenarios where 2 PMP entries with same pmpaddr\n    - one without matching
+          permissions or with A=OFF\n    - one with matching permissions and A=NA4/NAPOT/TOR\n\
+          \    - any of them can be the lowest-numbered PMP entry]\nTST51-2\n[configure
+          2 PMP entries\n  - configure the lowest-numbered PMP entry with  (TST11-11,
+          TST11-21, TST11-31, TST11-41, TST11-51,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST11-14, TST11-24, TST11-34, TST11-44, TST11-54,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-11, TST12-21,
+          TST12-31, TST12-41, TST12-51,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t TST12-14, TST12-24, TST12-34, TST12-44, TST12-54,\n           \
+          \                                        TST13-11, TST13-21, TST13-31, TST13-41,
+          TST13-51,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST13-14,
+          TST13-24, TST13-34, TST13-44, TST13-54,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-14, TST14-24,
+          TST14-34, TST14-44, TST14-54,\n                                        \
+          \           TST15-11, TST15-21, TST15-31, TST15-41, TST15-51,\n        \
+          \                \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-14, TST15-24, TST15-34,
+          TST15-44, TST15-54,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t
+          TST16-11, TST16-21, TST16-31, TST16-41, TST16-51,\n                    \
+          \    \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-14, TST16-24, TST16-34, TST16-44,
+          TST16-54)\n  - configure the highest-numbered PMP entry with  (TST11-12,
+          TST11-22, TST11-32, TST11-42, TST11-52,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t  TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST12-12, TST12-22,
+          TST12-32, TST12-42, TST12-52,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t  TST12-15, TST12-25, TST12-35, TST12-45, TST12-55,\n          \
+          \                                          TST13-12, TST13-22, TST13-32,
+          TST13-42, TST13-52,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t\
+          \  TST13-15, TST13-25, TST13-35, TST13-45, TST13-55,\n                 \
+          \       \t\t\t\t\t\t\t\t\t \t\t\t\t  TST14-12, TST14-22, TST14-32, TST14-42,
+          TST14-52,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST14-15,
+          TST14-25, TST14-35, TST14-45, TST14-55,\n                              \
+          \                      TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST15-15, TST15-25,
+          TST15-35, TST15-45, TST15-55,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t  TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n          \
+          \              \t\t\t\t\t\t\t\t\t \t\t\t\t  TST16-15, TST16-25, TST16-35,
+          TST16-45, TST16-55,\n                                                  \
+          \  TST17-12, TST17-22, TST17-32, TST17-42, TST17-52,\n                 \
+          \       \t\t\t\t\t\t\t\t\t \t\t\t\t  TST17-15, TST17-25, TST17-35, TST17-45,
+          TST17-55,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST18-12,
+          TST18-22, TST18-32, TST18-42, TST18-52,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t  TST18-15, TST18-25, TST18-35, TST18-45, TST18-55)\n\
+          \  - execute the associated access\n  - check no access-fault exception]"
+vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
+io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
+config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
+ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'

verif/docs/VerifPlans/PMP/VP_IP022.yml

@@ -0,0 +1,376 @@
+!Feature
+next_elt_id: 6
+name: multi entries NAPOT
+id: 22
+display_order: 22
+subfeatures: !!omap
+- 000_1_entry: !Subfeature
+    name: 000_1_entry
+    tag: VP_PMP_F022_S001
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F022_S001_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose a single PMP entry\n\nCONFIGURATION and ACCESS\n    -
+          for each pmp entry, apply any CONFIGURATION+ACCESS scenario above (Cf. Feature:
+          \"cfg NAPOT access S/U/M\")\n    - make sure the pmp entries address ranges
+          are not overlapping/intersecting\n    - NB: obviously, pmp entry configurations
+          with different mstatus.MPRV/MPP values cannot be mixed in same test\n\n\
+          CHECK\n    - for each pmp entry, we should obtain the expected CHECK result\n\
+          \nREUSABILITY\n    - if possible, the number of PMP entries (N) is a configurable
+          parameter\n    - so a single test function can be reused"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST22(group)\n  [create scenarios where PMP entries
+          with A=3 (NAPOT) and with/without matching permissions\n    - check only
+          NAPOT defined addresses are matching]\nTST22-1 = extension of (TST13-11,
+          TST13-21, TST13-31, TST13-41, TST13-51,\n                        TST13-12,
+          TST13-22, TST13-32, TST13-42, TST13-52,\n                        TST13-13,
+          TST13-23, TST13-33, TST13-43, TST13-53,\n                        TST13-14,
+          TST13-24, TST13-34, TST13-44, TST13-54,\n                        TST13-15,
+          TST13-25, TST13-35, TST13-45, TST13-55,\n                        TST13-16,
+          TST13-26, TST13-36, TST13-46, TST13-56,\n                        TST14-11,
+          TST14-21, TST14-31, TST14-41, TST14-51,\n                        TST14-12,
+          TST14-22, TST14-32, TST14-42, TST14-52,\n                        TST14-13,
+          TST14-23, TST14-33, TST14-43, TST14-53,\n                        TST14-14,
+          TST14-24, TST14-34, TST14-44, TST14-54,\n                        TST14-15,
+          TST14-25, TST14-35, TST14-45, TST14-55,\n                        TST14-16,
+          TST14-26, TST14-36, TST14-46, TST14-56)\n[configure only one (any, but the
+          first one) PMP entry\n  - use A=NAPOT for the PMP entry configuration\n\
+          \  - execute the chosen kind of access\n  - should be same result]"
+- 001_2_isolated_entries: !Subfeature
+    name: 001_2_isolated_entries
+    tag: VP_PMP_F022_S002
+    next_elt_id: 1
+    display_order: 1
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F022_S002_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any 2 PMP entries\n\nreuse of VP_PMP_F022_S001_I000 feature
+          description (Cf. Feature: \"multi entries NAPOT\")"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST22(group)\n  [create scenarios where PMP entries
+          with A=3 (NAPOT) and with/without matching permissions\n    - check only
+          NAPOT defined addresses are matching]\nTST22-2 = extension of compatible
+          pair of (TST13-11, TST13-21, TST13-31, TST13-41, TST13-51,\n           \
+          \             \t\t\t\t\t\t\t\t\t TST13-12, TST13-22, TST13-32, TST13-42,
+          TST13-52,\n                        \t\t\t\t\t\t\t\t\t TST13-13, TST13-23,
+          TST13-33, TST13-43, TST13-53,\n                        \t\t\t\t\t\t\t\t\t
+          TST13-14, TST13-24, TST13-34, TST13-44, TST13-54,\n                    \
+          \    \t\t\t\t\t\t\t\t\t TST13-15, TST13-25, TST13-35, TST13-45, TST13-55,\n\
+          \                        \t\t\t\t \t\t\t\t\t TST13-16, TST13-26, TST13-36,
+          TST13-46, TST13-56,\n                        \t\t\t\t\t\t\t\t\t TST14-11,
+          TST14-21, TST14-31, TST14-41, TST14-51,\n                        \t\t\t\t
+          \t\t\t\t\t TST14-12, TST14-22, TST14-32, TST14-42, TST14-52,\n         \
+          \               \t\t\t\t\t\t\t\t\t TST14-13, TST14-23, TST14-33, TST14-43,
+          TST14-53,\n                        \t\t\t\t\t\t\t\t\t TST14-14, TST14-24,
+          TST14-34, TST14-44, TST14-54,\n                        \t\t\t\t\t\t\t\t\t
+          TST14-15, TST14-25, TST14-35, TST14-45, TST14-55,\n                    \
+          \    \t\t\t\t\t\t\t\t\t TST14-16, TST14-26, TST14-36, TST14-46, TST14-56)\n
+          [configure 2 non-adjacent PMP entries (highest-numbered ones first) (avoid
+          the first PMP entry)\n  - use A=NAPOT for each PMP entry configuration\n\
+          \  - execute the 2 kinds of accesses (if possible to chain due to potential
+          access-fault exception)\n  - should be same 2 results]"
+- 002_N_isolated_entries: !Subfeature
+    name: 002_N_isolated_entries
+    tag: VP_PMP_F022_S003
+    next_elt_id: 1
+    display_order: 2
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F022_S003_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any N PMP entries (2<N<8)\n\nreuse of VP_PMP_F022_S001_I000
+          feature description (Cf. Feature: \"multi entries NAPOT\")"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST22(group)\n  [create scenarios where PMP entries
+          with A=3 (NAPOT) and with/without matching permissions\n    - check only
+          NAPOT defined addresses are matching]\nTST22-3 = extension of compatible
+          group(N) of (TST13-11, TST13-21, TST13-31, TST13-41, TST13-51,\n       \
+          \                 \t\t\t\t \t\t\t\t\t\t\t TST13-12, TST13-22, TST13-32,
+          TST13-42, TST13-52,\n                        \t\t\t\t\t\t\t\t\t\t\t TST13-13,
+          TST13-23, TST13-33, TST13-43, TST13-53,\n                        \t\t\t\t
+          \t\t\t\t\t\t\t TST13-14, TST13-24, TST13-34, TST13-44, TST13-54,\n     \
+          \                   \t\t\t\t \t\t\t\t\t\t\t TST13-15, TST13-25, TST13-35,
+          TST13-45, TST13-55,\n                        \t\t\t\t\t\t\t\t\t\t\t TST13-16,
+          TST13-26, TST13-36, TST13-46, TST13-56,\n                        \t\t\t\t
+          \t\t\t\t\t\t\t TST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n     \
+          \                   \t\t\t\t \t\t\t\t\t\t\t TST14-12, TST14-22, TST14-32,
+          TST14-42, TST14-52,\n                        \t\t\t\t\t\t\t\t\t\t\t TST14-13,
+          TST14-23, TST14-33, TST14-43, TST14-53,\n                        \t\t\t\t
+          \t\t\t\t\t\t\t TST14-14, TST14-24, TST14-34, TST14-44, TST14-54,\n     \
+          \                   \t\t\t\t \t\t\t\t\t\t\t TST14-15, TST14-25, TST14-35,
+          TST14-45, TST14-55,\n                        \t\t\t\t\t\t\t\t\t\t\t TST14-16,
+          TST14-26, TST14-36, TST14-46, TST14-56)\n[configure N PMP entries (highest-numbered
+          ones first) (as non-adjacent as possible, and avoid the first PMP entry)\n\
+          \  - use A=NAPOT for each PMP entry configuration\n  - execute the N kinds
+          of accesses (if possible to chain due to potential access-fault exception)\n\
+          \  - should be same N results]"
+- 003_8_isolated_entries: !Subfeature
+    name: 003_8_isolated_entries
+    tag: VP_PMP_F022_S004
+    next_elt_id: 1
+    display_order: 3
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F022_S004_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose all 8 PMP entries\n\nreuse of VP_PMP_F022_S001_I000 feature
+          description (Cf. Feature: \"multi entries NAPOT\")"
+        pfc: 3
+        test_type: 3
+        cov_method: 0
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST22(group)\n  [create scenarios where PMP entries
+          with A=3 (NAPOT) and with/without matching permissions\n    - check only
+          NAPOT defined addresses are matching]\nTST22-4 = extension of compatible
+          group(8) of (TST13-11, TST13-21, TST13-31, TST13-41, TST13-51,\n       \
+          \                 \t\t\t\t \t\t\t\t\t\t\t TST13-12, TST13-22, TST13-32,
+          TST13-42, TST13-52,\n                        \t\t\t\t\t\t\t\t\t\t\t TST13-13,
+          TST13-23, TST13-33, TST13-43, TST13-53,\n                        \t\t\t\t
+          \t\t\t\t\t\t\t TST13-14, TST13-24, TST13-34, TST13-44, TST13-54,\n     \
+          \                   \t\t\t\t \t\t\t\t\t\t\t TST13-15, TST13-25, TST13-35,
+          TST13-45, TST13-55,\n                        \t\t\t\t\t\t\t\t\t\t\t TST13-16,
+          TST13-26, TST13-36, TST13-46, TST13-56,\n                        \t\t\t\t
+          \t\t\t\t\t\t\t TST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n     \
+          \                   \t\t\t\t \t\t\t\t\t\t\t TST14-12, TST14-22, TST14-32,
+          TST14-42, TST14-52,\n                        \t\t\t\t\t\t\t\t\t\t\t TST14-13,
+          TST14-23, TST14-33, TST14-43, TST14-53,\n                        \t\t\t\t
+          \t\t\t\t\t\t\t TST14-14, TST14-24, TST14-34, TST14-44, TST14-54,\n     \
+          \                   \t\t\t\t \t\t\t\t\t\t\t TST14-15, TST14-25, TST14-35,
+          TST14-45, TST14-55,\n                        \t\t\t\t\t\t\t\t\t\t\t TST14-16,
+          TST14-26, TST14-36, TST14-46, TST14-56)\n[configure 8 PMP entries (highest-numbered
+          ones first)\n  - use A=NAPOT for each PMP entry configuration\n  - execute
+          the 8 kinds of accesses (if possible to chain due to potential access-fault
+          exception)\n  - should be same 8 results]"
+- 004_2_intersecting_entries_fail: !Subfeature
+    name: 004_2_intersecting_entries_fail
+    tag: VP_PMP_F022_S005
+    next_elt_id: 1
+    display_order: 4
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F022_S005_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any 2 PMP entries\n\nCONFIGURATION and ACCESS (Cf. Feature:
+          \"cfg NAPOT access S/U/M\")\n    - for the least-numbered pmp entry, apply
+          any CONFIGURATION+ACCESS scenario with access-fault\n    - for the highest-numbered
+          pmp entry, apply any CONFIGURATION+ACCESS scenario without access-fault\n\
+          \    - make sure the pmp entries address ranges are overlapping/intersecting
+          (at least at 4 consecutive bytes)\n    - for each pmp entry, execute one
+          access in its associated pmp address region but outside the overlapping/intersecting
+          address range\n    - execute one additional access inside the overlapping/intersecting
+          address range\n    - NB: obviously, pmp entry configurations with different
+          access-modes (S/U vs. M) cannot be easily mixed in same test\n    - NB:
+          obviously, pmp entry configurations with different mstatus.MPRV/MPP values
+          cannot be mixed in same test\n\nCHECK\n    - for each pmp entry, access
+          outside the overlapping/intersecting address range should give the expected
+          CHECK result\n    - access inside the overlapping/intersecting address range
+          should generate the access-type related access-fault\n\nREUSABILITY\n  \
+          \  - if possible, the number of PMP entries (N) is a configurable parameter\n\
+          \    - so a single test function can be reused"
+        pfc: 3
+        test_type: 4
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST51(group) => FTR09-a, FTR09-b and FTR09-c\n  [create
+          scenarios where 2 PMP entries with same pmpaddr\n    - one without matching
+          permissions or with A=OFF\n    - one with matching permissions and A=NA4/NAPOT/TOR\n\
+          \    - any of them can be the lowest-numbered PMP entry]\nTST51-1\n[configure
+          2 PMP entries\n  - configure the lowest-numbered PMP entry with  (TST11-12,
+          TST11-22, TST11-32, TST11-42, TST11-52,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-12, TST12-22,
+          TST12-32, TST12-42, TST12-52,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t TST12-15, TST12-25, TST12-35, TST12-45, TST12-55,\n           \
+          \                                        TST13-12, TST13-22, TST13-32, TST13-42,
+          TST13-52,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST13-15,
+          TST13-25, TST13-35, TST13-45, TST13-55,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST14-12, TST14-22, TST14-32, TST14-42, TST14-52,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-15, TST14-25,
+          TST14-35, TST14-45, TST14-55,\n                                        \
+          \           TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n        \
+          \                \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-15, TST15-25, TST15-35,
+          TST15-45, TST15-55,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t
+          TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n                    \
+          \    \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-15, TST16-25, TST16-35, TST16-45,
+          TST16-55,\n                                                   TST17-12,
+          TST17-22, TST17-32, TST17-42, TST17-52,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST17-15, TST17-25, TST17-35, TST17-45, TST17-55,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST18-12, TST18-22,
+          TST18-32, TST18-42, TST18-52,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t TST18-15, TST18-25, TST18-35, TST18-45, TST18-55)\n  - configure
+          the highest-numbered PMP entry with  (TST11-11, TST11-21, TST11-31, TST11-41,
+          TST11-51,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST11-14,
+          TST11-24, TST11-34, TST11-44, TST11-54,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t  TST12-11, TST12-21, TST12-31, TST12-41, TST12-51,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST12-14, TST12-24,
+          TST12-34, TST12-44, TST12-54,\n                                        \
+          \            TST13-11, TST13-21, TST13-31, TST13-41, TST13-51,\n       \
+          \                 \t\t\t\t\t\t\t\t\t \t\t\t\t\tTST13-14, TST13-24, TST13-34,
+          TST13-44, TST13-54,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t
+          \tTST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n                  \
+          \      \t\t\t\t\t\t\t\t\t \t\t\t\t\tTST14-14, TST14-24, TST14-34, TST14-44,
+          TST14-54,\n                                                    TST15-11,
+          TST15-21, TST15-31, TST15-41, TST15-51,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t  TST15-14, TST15-24, TST15-34, TST15-44, TST15-54,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST16-11, TST16-21,
+          TST16-31, TST16-41, TST16-51,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t  TST16-14, TST16-24, TST16-34, TST16-44, TST16-54)\n  - execute
+          the associated access\n  - check associated access-fault exception raised]"
+- 005_2_intersecting_entries_succeed: !Subfeature
+    name: 005_2_intersecting_entries_succeed
+    tag: VP_PMP_F022_S006
+    next_elt_id: 1
+    display_order: 5
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F022_S006_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any 2 PMP entries\n\nCONFIGURATION and ACCESS (Cf. Feature:
+          \"cfg NAPOT access S/U/M\")\n    - for the least-numbered pmp entry, apply
+          any CONFIGURATION+ACCESS scenario without access-fault\n    - for the highest-numbered
+          pmp entry, apply any CONFIGURATION+ACCESS scenario with access-fault\n \
+          \   - make sure the pmp entries address ranges are overlapping/intersecting
+          (at least at 4 consecutive bytes)\n    - for each pmp entry, execute one
+          access in its associated pmp address region but outside the overlapping/intersecting
+          address range\n    - execute one additional access inside the overlapping/intersecting
+          address range\n    - NB: obviously, pmp entry configurations with different
+          access-modes (S/U vs. M) cannot be easily mixed in same test\n    - NB:
+          obviously, pmp entry configurations with different mstatus.MPRV/MPP values
+          cannot be mixed in same test\n\nCHECK\n    - for each pmp entry, access
+          outside the overlapping/intersecting address range should give the expected
+          CHECK result\n    - access inside the overlapping/intersecting address range
+          should not generate any access-fault\n\nREUSABILITY\n    - if possible,
+          the number of PMP entries (N) is a configurable parameter\n    - so a single
+          test function can be reused"
+        pfc: 3
+        test_type: 4
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST51(group) => FTR09-a, FTR09-b and FTR09-c\n  [create
+          scenarios where 2 PMP entries with same pmpaddr\n    - one without matching
+          permissions or with A=OFF\n    - one with matching permissions and A=NA4/NAPOT/TOR\n\
+          \    - any of them can be the lowest-numbered PMP entry]\nTST51-2\n[configure
+          2 PMP entries\n  - configure the lowest-numbered PMP entry with  (TST11-11,
+          TST11-21, TST11-31, TST11-41, TST11-51,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST11-14, TST11-24, TST11-34, TST11-44, TST11-54,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-11, TST12-21,
+          TST12-31, TST12-41, TST12-51,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t TST12-14, TST12-24, TST12-34, TST12-44, TST12-54,\n           \
+          \                                        TST13-11, TST13-21, TST13-31, TST13-41,
+          TST13-51,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST13-14,
+          TST13-24, TST13-34, TST13-44, TST13-54,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-14, TST14-24,
+          TST14-34, TST14-44, TST14-54,\n                                        \
+          \           TST15-11, TST15-21, TST15-31, TST15-41, TST15-51,\n        \
+          \                \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-14, TST15-24, TST15-34,
+          TST15-44, TST15-54,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t
+          TST16-11, TST16-21, TST16-31, TST16-41, TST16-51,\n                    \
+          \    \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-14, TST16-24, TST16-34, TST16-44,
+          TST16-54)\n  - configure the highest-numbered PMP entry with  (TST11-12,
+          TST11-22, TST11-32, TST11-42, TST11-52,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t  TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST12-12, TST12-22,
+          TST12-32, TST12-42, TST12-52,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t  TST12-15, TST12-25, TST12-35, TST12-45, TST12-55,\n          \
+          \                                          TST13-12, TST13-22, TST13-32,
+          TST13-42, TST13-52,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t\
+          \  TST13-15, TST13-25, TST13-35, TST13-45, TST13-55,\n                 \
+          \       \t\t\t\t\t\t\t\t\t \t\t\t\t  TST14-12, TST14-22, TST14-32, TST14-42,
+          TST14-52,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST14-15,
+          TST14-25, TST14-35, TST14-45, TST14-55,\n                              \
+          \                      TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST15-15, TST15-25,
+          TST15-35, TST15-45, TST15-55,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t  TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n          \
+          \              \t\t\t\t\t\t\t\t\t \t\t\t\t  TST16-15, TST16-25, TST16-35,
+          TST16-45, TST16-55,\n                                                  \
+          \  TST17-12, TST17-22, TST17-32, TST17-42, TST17-52,\n                 \
+          \       \t\t\t\t\t\t\t\t\t \t\t\t\t  TST17-15, TST17-25, TST17-35, TST17-45,
+          TST17-55,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST18-12,
+          TST18-22, TST18-32, TST18-42, TST18-52,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t  TST18-15, TST18-25, TST18-35, TST18-45, TST18-55)\n\
+          \  - execute the associated access\n  - check no access-fault exception]"
+vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
+io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
+config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
+ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'

verif/docs/VerifPlans/PMP/VP_IP023.yml

@@ -0,0 +1,378 @@
+!Feature
+next_elt_id: 6
+name: multi entries TOR
+id: 23
+display_order: 23
+subfeatures: !!omap
+- 000_1_entry: !Subfeature
+    name: 000_1_entry
+    tag: VP_PMP_F023_S001
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F023_S001_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose a single PMP entry\n\nCONFIGURATION and ACCESS\n    -
+          for each pmp entry, apply any CONFIGURATION+ACCESS scenario above (Cf. Feature:
+          \"cfg TOR access S/U/M\")\n    - make sure the pmp entries address ranges
+          are not overlapping/intersecting\n    - NB: obviously, pmp entry configurations
+          with different mstatus.MPRV/MPP values cannot be mixed in same test\n\n\
+          CHECK\n    - for each pmp entry, we should obtain the expected CHECK result\n\
+          \nREUSABILITY\n    - if possible, the number of PMP entries (N) is a configurable
+          parameter\n    - so a single test function can be reused"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST23(group) => \n  [create scenarios where PMP entries
+          with A=1 (TOR) and with/without matching permissions\n    - pmpaddr(i−1)
+          < pmpaddr(i), pmpcfg(i).A=TOR and pmpcfg(i-1) with/without matching permissions\n\
+          \    - check only TOR defined addresses are matching]\nTST23-1 = extension
+          of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51,\n                \
+          \        TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n           \
+          \             TST15-13, TST15-23, TST15-33, TST15-43, TST15-53,\n      \
+          \                  TST15-14, TST15-24, TST15-34, TST15-44, TST15-54,\n \
+          \                       TST15-15, TST15-25, TST15-35, TST15-45, TST15-55,\n\
+          \                        TST15-16, TST15-26, TST15-36, TST15-46, TST15-56,\n\
+          \                        TST16-11, TST16-21, TST16-31, TST16-41, TST16-51,\n\
+          \                        TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n\
+          \                        TST16-13, TST16-23, TST16-33, TST16-43, TST16-53,\n\
+          \                        TST16-14, TST16-24, TST16-34, TST16-44, TST16-54,\n\
+          \                        TST16-15, TST16-25, TST16-35, TST16-45, TST16-55,\n\
+          \                        TST16-16, TST16-26, TST16-36, TST16-46, TST16-56)\n
+          [configure only one (any, but the first one) PMP entry\n  - execute the
+          chosen kind of access\n  - should be same result]"
+- 001_2_isolated_entries: !Subfeature
+    name: 001_2_isolated_entries
+    tag: VP_PMP_F023_S002
+    next_elt_id: 1
+    display_order: 1
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F023_S002_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any 2 PMP entries\n\nreuse of VP_PMP_F023_S001_I000 feature
+          description (Cf. Feature: \"multi entries TOR\")"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST23(group) => \n  [create scenarios where PMP entries
+          with A=1 (TOR) and with/without matching permissions\n    - pmpaddr(i−1)
+          < pmpaddr(i), pmpcfg(i).A=TOR and pmpcfg(i-1) with/without matching permissions\n\
+          \    - check only TOR defined addresses are matching]\nTST23-2 = extension
+          of compatible pair of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51,\n\
+          \                        \t\t\t\t\t\t\t\t\t TST15-12, TST15-22, TST15-32,
+          TST15-42, TST15-52,\n                        \t\t\t\t\t\t\t\t\t TST15-13,
+          TST15-23, TST15-33, TST15-43, TST15-53,\n                        \t\t\t\t
+          \t\t\t\t\t TST15-14, TST15-24, TST15-34, TST15-44, TST15-54,\n         \
+          \               \t\t\t\t\t\t\t\t\t TST15-15, TST15-25, TST15-35, TST15-45,
+          TST15-55,\n                        \t\t\t\t\t\t\t\t\t TST15-16, TST15-26,
+          TST15-36, TST15-46, TST15-56,\n                        \t\t\t\t\t\t\t\t\t
+          TST16-11, TST16-21, TST16-31, TST16-41, TST16-51,\n                    \
+          \    \t\t\t\t \t\t\t\t\t TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n\
+          \                        \t\t\t\t\t\t\t\t\t TST16-13, TST16-23, TST16-33,
+          TST16-43, TST16-53,\n                        \t\t\t\t\t\t\t\t\t TST16-14,
+          TST16-24, TST16-34, TST16-44, TST16-54,\n                        \t\t\t\t
+          \t\t\t\t\t TST16-15, TST16-25, TST16-35, TST16-45, TST16-55,\n         \
+          \               \t\t\t\t\t\t\t\t\t TST16-16, TST16-26, TST16-36, TST16-46,
+          TST16-56)\n [configure 2 non-adjacent PMP entries (highest-numbered ones
+          first) (avoid the first PMP entry)\n  - execute the 2 kinds of accesses
+          (if possible to chain due to potential access-fault exception)\n  - should
+          be same 2 results]"
+- 002_N_isolated_entries: !Subfeature
+    name: 002_N_isolated_entries
+    tag: VP_PMP_F023_S003
+    next_elt_id: 1
+    display_order: 2
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F023_S003_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any N PMP entries (2<N<8)\n\nreuse of VP_PMP_F023_S001_I000
+          feature description (Cf. Feature: \"multi entries TOR\")"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST23(group) => \n  [create scenarios where PMP entries
+          with A=1 (TOR) and with/without matching permissions\n    - pmpaddr(i−1)
+          < pmpaddr(i), pmpcfg(i).A=TOR and pmpcfg(i-1) with/without matching permissions\n\
+          \    - check only TOR defined addresses are matching]\nTST23-3 = extension
+          of compatible group(N) of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51,\n\
+          \                        \t\t\t\t\t\t\t\t\t\t\t TST15-12, TST15-22, TST15-32,
+          TST15-42, TST15-52,\n                        \t\t\t\t\t\t\t\t\t\t\t TST15-13,
+          TST15-23, TST15-33, TST15-43, TST15-53,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t TST15-14, TST15-24, TST15-34, TST15-44, TST15-54,\n    \
+          \                    \t\t\t\t\t\t\t\t\t\t\t TST15-15, TST15-25, TST15-35,
+          TST15-45, TST15-55,\n                        \t\t\t\t\t\t\t\t\t\t\t TST15-16,
+          TST15-26, TST15-36, TST15-46, TST15-56,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t TST16-11, TST16-21, TST16-31, TST16-41, TST16-51,\n    \
+          \                    \t\t\t\t\t\t\t\t\t\t\t TST16-12, TST16-22, TST16-32,
+          TST16-42, TST16-52,\n                        \t\t\t\t\t\t\t\t\t\t\t TST16-13,
+          TST16-23, TST16-33, TST16-43, TST16-53,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t TST16-14, TST16-24, TST16-34, TST16-44, TST16-54,\n    \
+          \                    \t\t\t\t\t\t\t\t\t\t\t TST16-15, TST16-25, TST16-35,
+          TST16-45, TST16-55,\n                        \t\t\t\t\t\t\t\t\t\t\t TST16-16,
+          TST16-26, TST16-36, TST16-46, TST16-56)\n[configure N PMP entries (highest-numbered
+          ones first) (as non-adjacent as possible, and avoid the first PMP entry)\n\
+          \  - execute the N kinds of accesses (if possible to chain due to potential
+          access-fault exception)\n  - should be same N results]"
+- 003_8_isolated_entries: !Subfeature
+    name: 003_8_isolated_entries
+    tag: VP_PMP_F023_S004
+    next_elt_id: 1
+    display_order: 3
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F023_S004_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose all 8 PMP entries\n\nreuse of VP_PMP_F023_S001_I000 feature
+          description (Cf. Feature: \"multi entries TOR\")"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST23(group) => \n  [create scenarios where PMP entries
+          with A=1 (TOR) and with/without matching permissions\n    - pmpaddr(i−1)
+          < pmpaddr(i), pmpcfg(i).A=TOR and pmpcfg(i-1) with/without matching permissions\n\
+          \    - check only TOR defined addresses are matching]\nTST23-4 = extension
+          of compatible group(8) of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51,\n\
+          \                        \t\t\t\t\t\t\t\t\t\t\t TST15-12, TST15-22, TST15-32,
+          TST15-42, TST15-52,\n                        \t\t\t\t\t\t\t\t\t\t\t TST15-13,
+          TST15-23, TST15-33, TST15-43, TST15-53,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t TST15-14, TST15-24, TST15-34, TST15-44, TST15-54,\n    \
+          \                    \t\t\t\t\t\t\t\t\t\t\t TST15-15, TST15-25, TST15-35,
+          TST15-45, TST15-55,\n                        \t\t\t\t\t\t\t\t\t\t\t TST15-16,
+          TST15-26, TST15-36, TST15-46, TST15-56,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t TST16-11, TST16-21, TST16-31, TST16-41, TST16-51,\n    \
+          \                    \t\t\t\t\t\t\t\t\t\t\t TST16-12, TST16-22, TST16-32,
+          TST16-42, TST16-52,\n                        \t\t\t\t\t\t\t\t\t\t\t TST16-13,
+          TST16-23, TST16-33, TST16-43, TST16-53,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t TST16-14, TST16-24, TST16-34, TST16-44, TST16-54,\n    \
+          \                    \t\t\t\t\t\t\t\t\t\t\t TST16-15, TST16-25, TST16-35,
+          TST16-45, TST16-55,\n                        \t\t\t\t\t\t\t\t\t\t\t TST16-16,
+          TST16-26, TST16-36, TST16-46, TST16-56)\n[configure 8 PMP entries (highest-numbered
+          ones first)\n  - execute the 8 kinds of accesses (if possible to chain due
+          to potential access-fault exception)\n  - should be same 8 results]"
+- 004_2_intersecting_entries_fail: !Subfeature
+    name: 004_2_intersecting_entries_fail
+    tag: VP_PMP_F023_S005
+    next_elt_id: 1
+    display_order: 4
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F023_S005_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any 2 PMP entries\n\nCONFIGURATION and ACCESS (Cf. Feature:
+          \"cfg TOR access S/U/M\")\n    - for the least-numbered pmp entry, apply
+          any CONFIGURATION+ACCESS scenario with access-fault\n    - for the highest-numbered
+          pmp entry, apply any CONFIGURATION+ACCESS scenario without access-fault\n\
+          \    - make sure the pmp entries address ranges are overlapping/intersecting
+          (at least at 4 consecutive bytes)\n    - for each pmp entry, execute one
+          access in its associated pmp address region but outside the overlapping/intersecting
+          address range\n    - execute one additional access inside the overlapping/intersecting
+          address range\n    - NB: obviously, pmp entry configurations with different
+          access-modes (S/U vs. M) cannot be easily mixed in same test\n    - NB:
+          obviously, pmp entry configurations with different mstatus.MPRV/MPP values
+          cannot be mixed in same test\n\nCHECK\n    - for each pmp entry, access
+          outside the overlapping/intersecting address range should give the expected
+          CHECK result\n    - access inside the overlapping/intersecting address range
+          should generate the access-type related access-fault\n\nREUSABILITY\n  \
+          \  - if possible, the number of PMP entries (N) is a configurable parameter\n\
+          \    - so a single test function can be reused"
+        pfc: 3
+        test_type: 4
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST51(group) => FTR09-a, FTR09-b and FTR09-c\n  [create
+          scenarios where 2 PMP entries with same pmpaddr\n    - one without matching
+          permissions or with A=OFF\n    - one with matching permissions and A=NA4/NAPOT/TOR\n\
+          \    - any of them can be the lowest-numbered PMP entry]\nTST51-1\n[configure
+          2 PMP entries\n  - configure the lowest-numbered PMP entry with  (TST11-12,
+          TST11-22, TST11-32, TST11-42, TST11-52,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-12, TST12-22,
+          TST12-32, TST12-42, TST12-52,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t TST12-15, TST12-25, TST12-35, TST12-45, TST12-55,\n           \
+          \                                        TST13-12, TST13-22, TST13-32, TST13-42,
+          TST13-52,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST13-15,
+          TST13-25, TST13-35, TST13-45, TST13-55,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST14-12, TST14-22, TST14-32, TST14-42, TST14-52,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-15, TST14-25,
+          TST14-35, TST14-45, TST14-55,\n                                        \
+          \           TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n        \
+          \                \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-15, TST15-25, TST15-35,
+          TST15-45, TST15-55,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t
+          TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n                    \
+          \    \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-15, TST16-25, TST16-35, TST16-45,
+          TST16-55,\n                                                   TST17-12,
+          TST17-22, TST17-32, TST17-42, TST17-52,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST17-15, TST17-25, TST17-35, TST17-45, TST17-55,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST18-12, TST18-22,
+          TST18-32, TST18-42, TST18-52,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t TST18-15, TST18-25, TST18-35, TST18-45, TST18-55)\n  - configure
+          the highest-numbered PMP entry with  (TST11-11, TST11-21, TST11-31, TST11-41,
+          TST11-51,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST11-14,
+          TST11-24, TST11-34, TST11-44, TST11-54,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t  TST12-11, TST12-21, TST12-31, TST12-41, TST12-51,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST12-14, TST12-24,
+          TST12-34, TST12-44, TST12-54,\n                                        \
+          \            TST13-11, TST13-21, TST13-31, TST13-41, TST13-51,\n       \
+          \                 \t\t\t\t\t\t\t\t\t \t\t\t\t\tTST13-14, TST13-24, TST13-34,
+          TST13-44, TST13-54,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t
+          \tTST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n                  \
+          \      \t\t\t\t\t\t\t\t\t \t\t\t\t\tTST14-14, TST14-24, TST14-34, TST14-44,
+          TST14-54,\n                                                    TST15-11,
+          TST15-21, TST15-31, TST15-41, TST15-51,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t  TST15-14, TST15-24, TST15-34, TST15-44, TST15-54,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST16-11, TST16-21,
+          TST16-31, TST16-41, TST16-51,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t  TST16-14, TST16-24, TST16-34, TST16-44, TST16-54)\n  - execute
+          the associated access\n  - check associated access-fault exception raised]"
+- 005_2_intersecting_entries_succeed: !Subfeature
+    name: 005_2_intersecting_entries_succeed
+    tag: VP_PMP_F023_S006
+    next_elt_id: 1
+    display_order: 5
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F023_S006_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any 2 PMP entries\n\nCONFIGURATION and ACCESS (Cf. Feature:
+          \"cfg TOR access S/U/M\")\n    - for the least-numbered pmp entry, apply
+          any CONFIGURATION+ACCESS scenario without access-fault\n    - for the highest-numbered
+          pmp entry, apply any CONFIGURATION+ACCESS scenario with access-fault\n \
+          \   - make sure the pmp entries address ranges are overlapping/intersecting
+          (at least at 4 consecutive bytes)\n    - for each pmp entry, execute one
+          access in its associated pmp address region but outside the overlapping/intersecting
+          address range\n    - execute one additional access inside the overlapping/intersecting
+          address range\n    - NB: obviously, pmp entry configurations with different
+          access-modes (S/U vs. M) cannot be easily mixed in same test\n    - NB:
+          obviously, pmp entry configurations with different mstatus.MPRV/MPP values
+          cannot be mixed in same test\n\nCHECK\n    - for each pmp entry, access
+          outside the overlapping/intersecting address range should give the expected
+          CHECK result\n    - access inside the overlapping/intersecting address range
+          should not generate any access-fault\n\nREUSABILITY\n    - if possible,
+          the number of PMP entries (N) is a configurable parameter\n    - so a single
+          test function can be reused"
+        pfc: 3
+        test_type: 4
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST51(group) => FTR09-a, FTR09-b and FTR09-c\n  [create
+          scenarios where 2 PMP entries with same pmpaddr\n    - one without matching
+          permissions or with A=OFF\n    - one with matching permissions and A=NA4/NAPOT/TOR\n\
+          \    - any of them can be the lowest-numbered PMP entry]\nTST51-2\n[configure
+          2 PMP entries\n  - configure the lowest-numbered PMP entry with  (TST11-11,
+          TST11-21, TST11-31, TST11-41, TST11-51,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST11-14, TST11-24, TST11-34, TST11-44, TST11-54,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-11, TST12-21,
+          TST12-31, TST12-41, TST12-51,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t TST12-14, TST12-24, TST12-34, TST12-44, TST12-54,\n           \
+          \                                        TST13-11, TST13-21, TST13-31, TST13-41,
+          TST13-51,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST13-14,
+          TST13-24, TST13-34, TST13-44, TST13-54,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-14, TST14-24,
+          TST14-34, TST14-44, TST14-54,\n                                        \
+          \           TST15-11, TST15-21, TST15-31, TST15-41, TST15-51,\n        \
+          \                \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-14, TST15-24, TST15-34,
+          TST15-44, TST15-54,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t
+          TST16-11, TST16-21, TST16-31, TST16-41, TST16-51,\n                    \
+          \    \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-14, TST16-24, TST16-34, TST16-44,
+          TST16-54)\n  - configure the highest-numbered PMP entry with  (TST11-12,
+          TST11-22, TST11-32, TST11-42, TST11-52,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t  TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST12-12, TST12-22,
+          TST12-32, TST12-42, TST12-52,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t  TST12-15, TST12-25, TST12-35, TST12-45, TST12-55,\n          \
+          \                                          TST13-12, TST13-22, TST13-32,
+          TST13-42, TST13-52,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t\
+          \  TST13-15, TST13-25, TST13-35, TST13-45, TST13-55,\n                 \
+          \       \t\t\t\t\t\t\t\t\t \t\t\t\t  TST14-12, TST14-22, TST14-32, TST14-42,
+          TST14-52,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST14-15,
+          TST14-25, TST14-35, TST14-45, TST14-55,\n                              \
+          \                      TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST15-15, TST15-25,
+          TST15-35, TST15-45, TST15-55,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t  TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n          \
+          \              \t\t\t\t\t\t\t\t\t \t\t\t\t  TST16-15, TST16-25, TST16-35,
+          TST16-45, TST16-55,\n                                                  \
+          \  TST17-12, TST17-22, TST17-32, TST17-42, TST17-52,\n                 \
+          \       \t\t\t\t\t\t\t\t\t \t\t\t\t  TST17-15, TST17-25, TST17-35, TST17-45,
+          TST17-55,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST18-12,
+          TST18-22, TST18-32, TST18-42, TST18-52,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t  TST18-15, TST18-25, TST18-35, TST18-45, TST18-55)\n\
+          \  - execute the associated access\n  - check no access-fault exception]"
+vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
+io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
+config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
+ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'

verif/docs/VerifPlans/PMP/VP_IP024.yml

@@ -0,0 +1,200 @@
+!Feature
+next_elt_id: 4
+name: multi entries OFF
+id: 24
+display_order: 24
+subfeatures: !!omap
+- 000_1_entry: !Subfeature
+    name: 000_1_entry
+    tag: VP_PMP_F024_S001
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F024_S001_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose a single PMP entry\n\nCONFIGURATION and ACCESS\n    -
+          for each pmp entry, apply any CONFIGURATION+ACCESS scenario above (Cf. Feature:
+          \"cfg OFF access S/U/M\")\n    - make sure the pmp entries address ranges
+          are not overlapping/intersecting\n    - NB: obviously, pmp entry configurations
+          with different mstatus.MPRV/MPP values cannot be mixed in same test\n\n\
+          CHECK\n    - for each pmp entry, we should obtain the expected CHECK result\n\
+          \nREUSABILITY\n    - if possible, the number of PMP entries (N) is a configurable
+          parameter\n    - so a single test function can be reused"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST24(group) => FTR09-g\n  [create scenarios where PMP
+          entries with A=0 (OFF) and with matching permissions\n    - check no address
+          matching for those PMP entries]\n  [create scenarios where all PMP entries
+          with A=0 (OFF) and with matching permissions\n    - check no address matching
+          for all PMP entries]\n  [check S or U mode access fails when all A=OFF with
+          at least one PMP entry implemented] => FTR09-g\nTST24-1 = extension of (TST17-11,
+          TST17-21, TST17-31, TST17-41, TST17-51,\n                        TST17-13,
+          TST17-23, TST17-33, TST17-43, TST17-53,\n                        TST17-14,
+          TST17-24, TST17-34, TST17-44, TST17-54,\n                        TST17-16,
+          TST17-26, TST17-36, TST17-46, TST17-56,\n                        TST18-14,
+          TST18-24, TST18-34, TST18-44, TST18-54, //TODO: M-mode may not raise an
+          exception\n                        TST18-16, TST18-26, TST18-36, TST18-46,
+          TST18-56) //TODO: M-mode may not raise an exception\n                  \
+          \      //TODO: SHOULD WE ADD (TST18-11, TST18-21, TST18-31, TST18-41, TST18-51,\n\
+          \                                               TST18-13, TST18-23, TST18-33,
+          TST18-43, TST18-53) ?\n[configure only one (any, but the first one) PMP
+          entry\n  - execute the chosen kind of access\n  - check appropriate access-fault
+          exception raised]"
+- 001_2_isolated_entries: !Subfeature
+    name: 001_2_isolated_entries
+    tag: VP_PMP_F024_S002
+    next_elt_id: 1
+    display_order: 1
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F024_S002_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any 2 PMP entries\n\nreuse of VP_PMP_F024_S001_I000 feature
+          description (Cf. Feature: \"multi entries OFF\")"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST24(group) => FTR09-g\n  [create scenarios where PMP
+          entries with A=0 (OFF) and with matching permissions\n    - check no address
+          matching for those PMP entries]\n  [create scenarios where all PMP entries
+          with A=0 (OFF) and with matching permissions\n    - check no address matching
+          for all PMP entries]\n  [check S or U mode access fails when all A=OFF with
+          at least one PMP entry implemented] => FTR09-g\nTST24-2 = extension of compatible
+          pair of (TST17-11, TST17-21, TST17-31, TST17-41, TST17-51,\n           \
+          \              \t\t\t\t\t\t\t\t\t TST17-13, TST17-23, TST17-33, TST17-43,
+          TST17-53,\n                         \t\t\t\t\t\t\t\t\t TST17-14, TST17-24,
+          TST17-34, TST17-44, TST17-54,\n                         \t\t\t\t\t\t\t\t
+          \t TST17-16, TST17-26, TST17-36, TST17-46, TST17-56,\n                 \
+          \        \t\t\t\t\t\t\t\t\t TST18-14, TST18-24, TST18-34, TST18-44, TST18-54,
+          //TODO: M-mode may not raise an exception\n                         \t\t
+          \t\t\t\t\t\t\t TST18-16, TST18-26, TST18-36, TST18-46, TST18-56) //TODO:
+          M-mode may not raise an exception\n                        //TODO: SHOULD
+          WE ADD (TST18-11, TST18-21, TST18-31, TST18-41, TST18-51,\n            \
+          \                                   TST18-13, TST18-23, TST18-33, TST18-43,
+          TST18-53) ?\n[configure 2 non-adjacent PMP entries (highest-numbered ones
+          first) (avoid the first PMP entry)\n  - execute the 2 kinds of accesses
+          (if possible to chain due to access-fault)\n  - check 2 appropriate access-fault
+          exceptions raised]"
+- 002_N_isolated_entries: !Subfeature
+    name: 002_N_isolated_entries
+    tag: VP_PMP_F024_S003
+    next_elt_id: 1
+    display_order: 2
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F024_S003_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any N PMP entries (2<N<8)\n\nreuse of VP_PMP_F024_S001_I000
+          feature description (Cf. Feature: \"multi entries OFF\")"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST24(group) => FTR09-g\n  [create scenarios where PMP
+          entries with A=0 (OFF) and with matching permissions\n    - check no address
+          matching for those PMP entries]\n  [create scenarios where all PMP entries
+          with A=0 (OFF) and with matching permissions\n    - check no address matching
+          for all PMP entries]\n  [check S or U mode access fails when all A=OFF with
+          at least one PMP entry implemented] => FTR09-g\nTST24-3 = extension of compatible
+          group(N) of (TST17-11, TST17-21, TST17-31, TST17-41, TST17-51,\n       \
+          \                   \t\t\t\t\t\t\t\t\t\t TST17-13, TST17-23, TST17-33, TST17-43,
+          TST17-53,\n                          \t\t\t\t\t\t\t\t\t\t TST17-14, TST17-24,
+          TST17-34, TST17-44, TST17-54,\n                          \t\t\t\t\t\t\t\t
+          \t\t TST17-16, TST17-26, TST17-36, TST17-46, TST17-56,\n               \
+          \           \t\t\t\t\t\t\t\t\t\t TST18-14, TST18-24, TST18-34, TST18-44,
+          TST18-54, //TODO: M-mode may not raise an exception\n                  \
+          \        \t\t\t\t\t\t\t\t\t\t TST18-16, TST18-26, TST18-36, TST18-46, TST18-56)
+          //TODO: M-mode may not raise an exception\n                        //TODO:
+          SHOULD WE ADD (TST18-11, TST18-21, TST18-31, TST18-41, TST18-51,\n     \
+          \                                          TST18-13, TST18-23, TST18-33,
+          TST18-43, TST18-53) ?\n[configure N PMP entries (highest-numbered ones first)
+          (as non-adjacent as possible, and avoid the first PMP entry)\n  - execute
+          the N kinds of accesses (if possible to chain due to access-fault)\n  -
+          check N appropriate access-fault exceptions raised]"
+- 003_8_isolated_entries: !Subfeature
+    name: 003_8_isolated_entries
+    tag: VP_PMP_F024_S004
+    next_elt_id: 1
+    display_order: 3
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F024_S004_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose all 8 PMP entries\n\nreuse of VP_PMP_F024_S001_I000 feature
+          description (Cf. Feature: \"multi entries OFF\")"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST24(group) => FTR09-g\n  [create scenarios where PMP
+          entries with A=0 (OFF) and with matching permissions\n    - check no address
+          matching for those PMP entries]\n  [create scenarios where all PMP entries
+          with A=0 (OFF) and with matching permissions\n    - check no address matching
+          for all PMP entries]\n  [check S or U mode access fails when all A=OFF with
+          at least one PMP entry implemented] => FTR09-g\nTST24-4 = extension of compatible
+          group(8) of (TST17-11, TST17-21, TST17-31, TST17-41, TST17-51,\n       \
+          \                 \t\t\t\t\t\t\t\t\t\t\t TST17-13, TST17-23, TST17-33, TST17-43,
+          TST17-53,\n                        \t\t\t\t\t\t\t\t\t\t\t TST17-14, TST17-24,
+          TST17-34, TST17-44, TST17-54,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t TST17-16, TST17-26, TST17-36, TST17-46, TST17-56,\n               \
+          \         \t\t\t\t\t\t\t\t\t\t\t TST18-14, TST18-24, TST18-34, TST18-44,
+          TST18-54, //TODO: M-mode may not raise an exception\n                  \
+          \      \t\t\t\t\t\t\t\t\t\t\t TST18-16, TST18-26, TST18-36, TST18-46, TST18-56)
+          //TODO: M-mode may not raise an exception\n                        //TODO:
+          SHOULD WE ADD (TST18-11, TST18-21, TST18-31, TST18-41, TST18-51,\n     \
+          \                                          TST18-13, TST18-23, TST18-33,
+          TST18-43, TST18-53) ?\n[configure 8 PMP entries (highest-numbered ones first)\n\
+          \  - execute the 8 kinds of accesses (if possible to chain due to access-fault)\n\
+          \  - check 8 appropriate access-fault exceptions raised]"
+vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
+io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
+config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
+ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'

verif/docs/VerifPlans/PMP/VP_IP025.yml

@@ -0,0 +1,290 @@
+!Feature
+next_elt_id: 6
+name: multi entries ALL
+id: 25
+display_order: 25
+subfeatures: !!omap
+- 000_1_entry: !Subfeature
+    name: 000_1_entry
+    tag: VP_PMP_F025_S001
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F025_S001_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose a single PMP entry\n\nCONFIGURATION and ACCESS\n    -
+          for each pmp entry, apply any CONFIGURATION+ACCESS scenario above (Cf. Feature:
+          \"cfg NA4/NAPOT/TOR/OFF access S/U/M\")\n    - make sure the pmp entries
+          address ranges are not overlapping/intersecting\n    - NB: obviously, pmp
+          entry configurations with different mstatus.MPRV/MPP values cannot be mixed
+          in same test\n\nCHECK\n    - for each pmp entry, we should obtain the expected
+          CHECK result\n\nREUSABILITY\n    - if possible, the number of PMP entries
+          (N) is a configurable parameter\n    - so a single test function can be
+          reused"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 001_2_isolated_entries: !Subfeature
+    name: 001_2_isolated_entries
+    tag: VP_PMP_F025_S002
+    next_elt_id: 1
+    display_order: 1
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F025_S002_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any 2 PMP entries\n\nreuse of VP_PMP_F025_S001_I000 feature
+          description (Cf. Feature: \"multi entries ALL\")"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 002_N_isolated_entries: !Subfeature
+    name: 002_N_isolated_entries
+    tag: VP_PMP_F025_S003
+    next_elt_id: 1
+    display_order: 2
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F025_S003_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any N PMP entries (2<N<8)\n\nreuse of VP_PMP_F025_S001_I000
+          feature description (Cf. Feature: \"multi entries ALL\")"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 003_8_isolated_entries: !Subfeature
+    name: 003_8_isolated_entries
+    tag: VP_PMP_F025_S004
+    next_elt_id: 1
+    display_order: 3
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F025_S004_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose all 8 PMP entries\n\nreuse of VP_PMP_F025_S001_I000 feature
+          description (Cf. Feature: \"multi entries ALL\")"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+- 004_2_intersecting_entries_fail: !Subfeature
+    name: 004_2_intersecting_entries_fail
+    tag: VP_PMP_F025_S005
+    next_elt_id: 1
+    display_order: 4
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F025_S005_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any 2 PMP entries\n\nCONFIGURATION and ACCESS (Cf. Feature:
+          \"cfg NA4/NAPOT/TOR/OFF access S/U/M\")\n    - for the least-numbered pmp
+          entry, apply any CONFIGURATION+ACCESS scenario with access-fault\n    -
+          for the highest-numbered pmp entry, apply any CONFIGURATION+ACCESS scenario
+          without access-fault\n    - make sure the pmp entries address ranges are
+          overlapping/intersecting (at least at 4 consecutive bytes)\n    - for each
+          pmp entry, execute one access in its associated pmp address region but outside
+          the overlapping/intersecting address range\n    - execute one additional
+          access inside the overlapping/intersecting address range\n    - NB: obviously,
+          pmp entry configurations with different access-modes (S/U vs. M) cannot
+          be easily mixed in same test\n    - NB: obviously, pmp entry configurations
+          with different mstatus.MPRV/MPP values cannot be mixed in same test\n\n\
+          CHECK\n    - for each pmp entry, access outside the overlapping/intersecting
+          address range should give the expected CHECK result\n    - access inside
+          the overlapping/intersecting address range should generate the access-type
+          related access-fault\n\nREUSABILITY\n    - if possible, the number of PMP
+          entries (N) is a configurable parameter\n    - so a single test function
+          can be reused"
+        pfc: 3
+        test_type: 4
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST51(group) => FTR09-a, FTR09-b and FTR09-c\n  [create
+          scenarios where 2 PMP entries with same pmpaddr\n    - one without matching
+          permissions or with A=OFF\n    - one with matching permissions and A=NA4/NAPOT/TOR\n\
+          \    - any of them can be the lowest-numbered PMP entry]\nTST51-1\n[configure
+          2 PMP entries\n  - configure the lowest-numbered PMP entry with  (TST11-12,
+          TST11-22, TST11-32, TST11-42, TST11-52,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-12, TST12-22,
+          TST12-32, TST12-42, TST12-52,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t TST12-15, TST12-25, TST12-35, TST12-45, TST12-55,\n           \
+          \                                        TST13-12, TST13-22, TST13-32, TST13-42,
+          TST13-52,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST13-15,
+          TST13-25, TST13-35, TST13-45, TST13-55,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST14-12, TST14-22, TST14-32, TST14-42, TST14-52,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-15, TST14-25,
+          TST14-35, TST14-45, TST14-55,\n                                        \
+          \           TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n        \
+          \                \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-15, TST15-25, TST15-35,
+          TST15-45, TST15-55,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t
+          TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n                    \
+          \    \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-15, TST16-25, TST16-35, TST16-45,
+          TST16-55,\n                                                   TST17-12,
+          TST17-22, TST17-32, TST17-42, TST17-52,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST17-15, TST17-25, TST17-35, TST17-45, TST17-55,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST18-12, TST18-22,
+          TST18-32, TST18-42, TST18-52,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t TST18-15, TST18-25, TST18-35, TST18-45, TST18-55)\n  - configure
+          the highest-numbered PMP entry with  (TST11-11, TST11-21, TST11-31, TST11-41,
+          TST11-51,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST11-14,
+          TST11-24, TST11-34, TST11-44, TST11-54,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t  TST12-11, TST12-21, TST12-31, TST12-41, TST12-51,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST12-14, TST12-24,
+          TST12-34, TST12-44, TST12-54,\n                                        \
+          \            TST13-11, TST13-21, TST13-31, TST13-41, TST13-51,\n       \
+          \                 \t\t\t\t\t\t\t\t\t \t\t\t\t\tTST13-14, TST13-24, TST13-34,
+          TST13-44, TST13-54,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t
+          \tTST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n                  \
+          \      \t\t\t\t\t\t\t\t\t \t\t\t\t\tTST14-14, TST14-24, TST14-34, TST14-44,
+          TST14-54,\n                                                    TST15-11,
+          TST15-21, TST15-31, TST15-41, TST15-51,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t  TST15-14, TST15-24, TST15-34, TST15-44, TST15-54,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST16-11, TST16-21,
+          TST16-31, TST16-41, TST16-51,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t  TST16-14, TST16-24, TST16-34, TST16-44, TST16-54)\n  - execute
+          the associated access\n  - check associated access-fault exception raised]"
+- 005_2_intersecting_entries_succeed: !Subfeature
+    name: 005_2_intersecting_entries_succeed
+    tag: VP_PMP_F025_S006
+    next_elt_id: 1
+    display_order: 5
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F025_S006_I000
+        description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume
+          II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are
+          supported"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "choose any 2 PMP entries\n\nCONFIGURATION and ACCESS (Cf. Feature:
+          \"cfg NA4/NAPOT/TOR/OFF access S/U/M\")\n    - for the least-numbered pmp
+          entry, apply any CONFIGURATION+ACCESS scenario without access-fault\n  \
+          \  - for the highest-numbered pmp entry, apply any CONFIGURATION+ACCESS
+          scenario with access-fault\n    - make sure the pmp entries address ranges
+          are overlapping/intersecting (at least at 4 consecutive bytes)\n    - for
+          each pmp entry, execute one access in its associated pmp address region
+          but outside the overlapping/intersecting address range\n    - execute one
+          additional access inside the overlapping/intersecting address range\n  \
+          \  - NB: obviously, pmp entry configurations with different access-modes
+          (S/U vs. M) cannot be easily mixed in same test\n    - NB: obviously, pmp
+          entry configurations with different mstatus.MPRV/MPP values cannot be mixed
+          in same test\n\nCHECK\n    - for each pmp entry, access outside the overlapping/intersecting
+          address range should give the expected CHECK result\n    - access inside
+          the overlapping/intersecting address range should not generate any access-fault\n\
+          \nREUSABILITY\n    - if possible, the number of PMP entries (N) is a configurable
+          parameter\n    - so a single test function can be reused"
+        pfc: 3
+        test_type: 4
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt
+          files (not up-to-date) : reading below not mandatory but may help for better
+          understanding >>\n\nTST51(group) => FTR09-a, FTR09-b and FTR09-c\n  [create
+          scenarios where 2 PMP entries with same pmpaddr\n    - one without matching
+          permissions or with A=OFF\n    - one with matching permissions and A=NA4/NAPOT/TOR\n\
+          \    - any of them can be the lowest-numbered PMP entry]\nTST51-2\n[configure
+          2 PMP entries\n  - configure the lowest-numbered PMP entry with  (TST11-11,
+          TST11-21, TST11-31, TST11-41, TST11-51,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST11-14, TST11-24, TST11-34, TST11-44, TST11-54,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-11, TST12-21,
+          TST12-31, TST12-41, TST12-51,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t TST12-14, TST12-24, TST12-34, TST12-44, TST12-54,\n           \
+          \                                        TST13-11, TST13-21, TST13-31, TST13-41,
+          TST13-51,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST13-14,
+          TST13-24, TST13-34, TST13-44, TST13-54,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t TST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-14, TST14-24,
+          TST14-34, TST14-44, TST14-54,\n                                        \
+          \           TST15-11, TST15-21, TST15-31, TST15-41, TST15-51,\n        \
+          \                \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-14, TST15-24, TST15-34,
+          TST15-44, TST15-54,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t
+          TST16-11, TST16-21, TST16-31, TST16-41, TST16-51,\n                    \
+          \    \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-14, TST16-24, TST16-34, TST16-44,
+          TST16-54)\n  - configure the highest-numbered PMP entry with  (TST11-12,
+          TST11-22, TST11-32, TST11-42, TST11-52,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t  TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST12-12, TST12-22,
+          TST12-32, TST12-42, TST12-52,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t  TST12-15, TST12-25, TST12-35, TST12-45, TST12-55,\n          \
+          \                                          TST13-12, TST13-22, TST13-32,
+          TST13-42, TST13-52,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t\
+          \  TST13-15, TST13-25, TST13-35, TST13-45, TST13-55,\n                 \
+          \       \t\t\t\t\t\t\t\t\t \t\t\t\t  TST14-12, TST14-22, TST14-32, TST14-42,
+          TST14-52,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST14-15,
+          TST14-25, TST14-35, TST14-45, TST14-55,\n                              \
+          \                      TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n\
+          \                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST15-15, TST15-25,
+          TST15-35, TST15-45, TST15-55,\n                        \t\t\t\t\t\t\t\t\t
+          \t\t\t\t  TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n          \
+          \              \t\t\t\t\t\t\t\t\t \t\t\t\t  TST16-15, TST16-25, TST16-35,
+          TST16-45, TST16-55,\n                                                  \
+          \  TST17-12, TST17-22, TST17-32, TST17-42, TST17-52,\n                 \
+          \       \t\t\t\t\t\t\t\t\t \t\t\t\t  TST17-15, TST17-25, TST17-35, TST17-45,
+          TST17-55,\n                        \t\t\t\t\t\t\t\t\t \t\t\t\t  TST18-12,
+          TST18-22, TST18-32, TST18-42, TST18-52,\n                        \t\t\t\t
+          \t\t\t\t\t \t\t\t\t  TST18-15, TST18-25, TST18-35, TST18-45, TST18-55)\n\
+          \  - execute the associated access\n  - check no access-fault exception]"
+vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
+io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
+config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
+ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'

verif/docs/VerifPlans/PMP/VP_IP031.yml

@@ -0,0 +1,51 @@
+!Feature
+next_elt_id: 1
+name: entry reconfiguration
+id: 31
+display_order: 31
+subfeatures: !!omap
+- 000_reconfigure_N_pmp_entries: !Subfeature
+    name: 000_reconfigure_N_pmp_entries
+    tag: VP_PMP_F031_S001
+    next_elt_id: 1
+    display_order: 0
+    items: !!omap
+    - '000': !VerifItem
+        name: '000'
+        tag: VP_PMP_F031_S001_I000
+        description: "reuse of feature descriptions (Cf. Feature: \"cfg NA4/NAPOT/TOR/OFF
+          access S/U/M\")\nreuse of feature descriptions (Cf. Feature: \"CSRs M-mode
+          only\")\nreuse of feature descriptions (Cf. Feature: \"CSRs locked access\"\
+          )\nreuse of feature descriptions (Cf. Feature: \"multi entries NA4/NAPOT/TOR/OFF\"\
+          )"
+        reqt_doc: ''
+        ref_mode: page
+        ref_page: ''
+        ref_section: ''
+        ref_viewer: firefox
+        verif_goals: "configure any N PMP entries, possibly some with L=1\n\nCONFIGURATION
+          and ACCESS\n    - for each pmp entry, apply any CONFIGURATION+ACCESS scenario
+          above (Cf. Feature: \"cfg NA4/NAPOT/TOR/OFF access S/U/M\")\n    - make
+          sure the pmp entries address ranges are not overlapping/intersecting\n \
+          \   - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP
+          values cannot be mixed in same test\n\nRECONFIGURATION and ACCESS\n    -
+          for each pmp entry with L=0, apply any other CONFIGURATION+ACCESS scenario
+          above (Cf. Feature: \"cfg NA4/NAPOT/TOR/OFF access S/U/M\")\n    - make
+          sure the pmp entries address ranges are not overlapping/intersecting\n \
+          \   - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP
+          values cannot be mixed in same test\n\nRESET\n    - if there is any pmp
+          entry with L=1, apply hart reset (or only PMP reset if possible)\n    -
+          and restart with CONFIGURATION and RESET\n\nCHECK\n    - for each pmp entry,
+          we should obtain the expected CHECK result\n\nREUSABILITY\n    - if possible,
+          the number of PMP entries (N) is a configurable parameter\n    - so a single
+          test function can be reused"
+        pfc: 3
+        test_type: 3
+        cov_method: 1
+        cores: -1
+        coverage_loc: ''
+        comments: ''
+vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $'
+io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $'
+config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $'
+ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $'

verif/docs/VerifPlans/PMP/pmp_verif_plan_features.txt

@@ -0,0 +1,224 @@
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+-19-FTR01
+
+FTR01-a
+[PMP allows physical memory access privileges (read, write, execute) to be specified for each physical memory region]
+
+FTR01-b
+[the standard PMP encoding supports regions as small as four bytes.]
+
+FTR01-c
+[Certain regions’ privileges can be hardwired: so only ever be visible in machine mode but in no lower-privilege layers.]
+FTR01-c-extended
+[PMP regions hardwired privileges can only be observed in M-mode]
+
+FTR01-d
+[PMP checks are applied to all accesses whose effective privilege mode is S or U]
+
+FTR01-e
+[PMP checks are also applied to page-table accesses for virtual-address translation, for which the effective privilege mode is S]
+
+FTR01-f (refers to FTR08-e1)
+[PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset]
+
+FTR01-g1
+[by default (PMP entry not yet configured), S and U modes have no PMP permissions]
+FTR01-g2
+[by default (PMP entry not yet configured), M-mode has full permissions.]
+
+FTR01-h
+[PMP violations are always trapped precisely at the processor]
+
+////////////////////////////
+-21-FTR02
+
+FTR02-a
+[Up to 64 PMP entries are supported]
+
+FTR02-b1
+[the lowest-numbered PMP CSRs must be implemented first (does it mean programmed first)]
+FTR02-b2
+[All PMP CSR fields are WARL and may be read-only zero (does read-only zero mean not implemented?)]
+
+FTR02-d
+[PMP CSRs are only accessible to M-mode]
+
+FTR02-e
+[2 CSRs, pmpcfg0–pmpcfg1, hold the configurations pmp0cfg–pmp7cfg for the 8 PMP entries]
+
+
+////////////////////////////
+-23-FTR03
+
+FTR03-a
+[Each PMP address register encodes bits 33–2 of a 34-bit physical address]
+
+FTR03-b (NOT TOTALLY UNDERSTOOD!!!)
+[Not all physical address bits may be implemented, and so the pmpaddr registers are WARL]
+
+////////////////////////////
+-25-FTR04
+
+FTR04-a
+[The R, W, and X fields form a collective WARL field for which the combinations with R=0 and W=1 are reserved.]
+
+FTR04-b
+[Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception]
+
+FTR04-c
+[Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception]
+
+FTR04-d
+[Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception]
+
+FTR04-e
+[if MXLEN is changed, the contents of the pmp(x)cfg fields are preserved, but appear in the pmpcfg(y) CSR prescribed by the new setting of MXLEN]
+FTR04-e-assumption
+[we assume MXLEN is always 32bits]
+
+////////////////////////////
+-27-FTR05
+
+FTR05-a
+[The A field in a PMP entry’s configuration register encodes the address-matching mode of the associated PMP address register]
+[When A=OFF, this PMP entry is disabled and matches no addresses]
+[When A=TOR, top boundary of an arbitrary range]
+[When A=NA4, naturally aligned four-byte regions]
+[When A=NAPOT, naturally aligned power-of-2 regions]
+[These modes support four-bytes granularity]
+
+////////////////////////////
+-28-FTR06
+
+FTR06-a
+[If PMP entry i’s A field is set to TOR, the entry matches any address y such that pmpaddr(i−1) ≤ y < pmpaddr(i) (irrespective of the value of pmpcfg(i−1))]
+
+FTR06-b
+[If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr(0)]
+
+FTR06-c
+[If pmpaddr(i−1) ≥ pmpaddr(i) and pmpcfg(i).A=TOR, then PMP entry i matches no addresses]
+
+////////////////////////////
+-30-FTR07
+
+FTR07-a
+[Although the PMP mechanism supports regions as small as 4 bytes, platforms may specify coarser PMP regions]
+[the PMP grain is 2^(G+2) bytes and must be the same across all PMP regions]
+
+FTR07-b
+[Software may determine the PMP granularity by writing zero to pmp(0)cfg, then writing all ones to pmpaddr(0), then reading back pmpaddr(0). If G is the index of the least-significant bit set, the PMP granularity is 2^(G+2) bytes]
+
+FTR07-c
+[If the current XLEN is greater than MXLEN, the PMP address registers are zero-extended from MXLEN to XLEN bits for the purposes of address matching]
+FTR07-c-assumption
+[we assume XLEN=MXLEN=32 bits]
+
+////////////////////////////
+-32-FTR08
+
+FTR08-a
+[The L bit indicates that the PMP entry is locked, i.e., writes to the configuration register and associated address registers are ignored]
+[If PMP entry (i) is locked, writes to pmp(i)cfg and pmpaddr(i) are ignored]
+
+FTR08-b
+[Locked PMP entries remain locked until the hart is reset]
+
+FTR08-c
+[if PMP entry (i) is locked and pmp(i)cfg.A is set to TOR, writes to pmpaddr(i-1) are ignored]
+
+FTR08-d
+[Setting the L bit locks the PMP entry even when the A field is set to OFF]
+
+FTR08-e
+[L bit indicates whether the R/W/X permissions are enforced on M-mode accesses]
+FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)
+[When the L bit is set, these permissions are enforced for all privilege modes]
+FTR08-e2-1 (refers to  FTR09-d1)
+[When the L bit is clear, any M-mode access matching the PMP entry will succeed]
+FTR08-e2-2 (refers to FTR09-d2-2)
+[When the L bit is clear, the R/W/X permissions apply only to S and U modes]
+
+////////////////////////////
+-34-FTR09
+
+FTR09-a
+[PMP entries are statically prioritized]
+[The lowest-numbered PMP entry that matches any byte of an access determines whether that access succeeds or fails]
+
+FTR09-b
+[The matching PMP entry must match all bytes of an access, or the access fails, irrespective of the L, R, W, and X bits]
+
+FTR09-c
+[If a PMP entry matches all bytes of an access, then the L, R, W, and X bits determine whether the access succeeds or fails]
+
+FTR09-d1 (refers to FTR08-e2-1)
+[If the L bit is clear and the privilege mode of the access is M, the access succeeds]
+FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)
+[if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set]
+FTR09-d2-2 (L=0 refers to FTR08-e2-2)
+[if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set]
+
+FTR09-e
+[If no PMP entry matches an M-mode access, the access succeeds]
+FTR09-e-question
+[what happens if no PMP entry is implemented ?]
+
+FTR09-f
+[If no PMP entry matches an S-mode or U-mode access, but at least one PMP entry is implemented, the access fails]
+FTR09-f-question
+[what happens if no PMP entry is implemented ?]
+
+FTR09-g
+[If at least one PMP entry is implemented, but all PMP entries’ A fields are set to OFF, then all S-mode and U-mode memory accesses will fail]
+FTR09-g-question (same as FTR09-f-question if 'memory access' is no different matter)
+[what happens if no PMP entry is implemented ?]
+
+question are the pmpaddr(i) aligned to 4bytes ?
+ - NA4: naturally aligned four-byte regions
+ - NAPOT: naturally aligned power-of-2 regions
+ - TOR:
+ These modes support four-byte granularity
+ Each PMP address register encodes bits 33–2 of a 34-bit physical address for RV32
+
+////////////////////////////
+-36-FTR10
+
+FTR10-a
+[An access-fault exception is generated if at least one access generated by an instruction fails, though other accesses generated by that instruction may succeed with visible side effects]
+
+FTR10-b
+[instructions that reference virtual memory are decomposed into multiple accesses]
+FTR10-b-assumption
+[we assume no virtual memory is implemented]
+[we assume page-based virtual memory is not implemented]
+
+FTR10-c
+[misaligned loads, stores, and instruction fetches may also be decomposed into multiple accesses, some of which may succeed before an access-fault exception occurs]
+
+////////////////////////////
+-38-FTR11
+FTR11-assumption
+[we assume no virtual memory is implemented]
+[we assume page-based virtual memory is not implemented]
+
+FTR11-a
+[instructions that access virtual memory may result in multiple physical-memory accesses, including implicit references to the page tables. The PMP checks apply to all of these accesses]
+
+FTR11-b
+[The effective privilege mode for implicit page-table accesses is S]
+
+FTR11-c
+[The PMP settings for the resulting physical address may be checked (and possibly cached) at any point between the address
+translation and the explicit memory access]
+
+FTR11-d
+[when the PMP settings are modified, M-mode software must synchronize the PMP settings with the virtual memory system and any PMP or address-translation caches]
+
+FTR11-e
+[If page-based virtual memory is not implemented, memory accesses check the PMP settings synchronously, so no SFENCE.VMA is needed]
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

verif/docs/VerifPlans/PMP/runme.sh

@@ -0,0 +1,34 @@
+#############################################################################
+# Copyright (C) 2022 Thales DIS France SAS
+#
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0.
+#
+# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com)
+#############################################################################
+#!/bin/sh
+
+# Location of project-specific directories
+ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")`
+
+# Set up platform location.  It can be anywhere but should contain
+# a valid `vp_config.py` file in `vptool` directory.
+# Here we use the verification tree from the example directory.
+export PLATFORM_TOP_DIR="$ROOTDIR"
+
+# Set the printable name for the project that will be used
+# in the human-readable documentation.
+export PROJECT_NAME="PMP"
+
+# Set the alphanumerical identifier of the project that
+# will be used to construct file names etc.
+export PROJECT_IDENT="PMP"
+
+# Set the destination directory of Markdown files for this project.
+# Since it will be used by VPTOOL, it shall NOT be a relative path.
+export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"`
+
+# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'.
+# FIXME: Introduce a suitably named shell variable that points to the root
+# directory of the tool set (TOOL_TOP etc.)
+# FORNOW use a hardcoded relative path.
+sh $ROOTDIR/../../../core-v-verif/tools/vptool/vptool.sh $*

verif/regress/pmp_cv32a60x_tests.sh

@@ -0,0 +1,41 @@
+##-----------------------------------------------------------------------------
+## Copyright 2024 Robert Bosch GmbH
+##
+## SPDX-License-Identifier: SHL-0.51
+##
+## Original Author: Konstantinos Leventos - Robert Bosch France SAS
+##-----------------------------------------------------------------------------
+
+# Where the tools are
+if ! [ -n "$RISCV" ]; then
+  echo "Error: RISCV variable undefined"
+  return
+fi
+
+# Install the required tools
+source ./verif/regress/install-spike.sh
+
+# Setup sim env
+source ./verif/sim/setup-env.sh
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+  DV_SIMULATORS=vcs-uvm
+fi
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+    UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+export DV_TARGET=cv32a60x
+
+make clean
+cd verif/sim/
+make clean_all
+
+python3 cva6.py --testlist=../tests/testlist_pmp-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/cv32a60x/linker/link.ld
+
+make clean_all
+cd -
+make clean

verif/tests/custom/pmp/decreasing_entries_test.S

@@ -0,0 +1,98 @@
+# ------------------------------------------------------------------------------
+#   Copyright 2024 Robert Bosch GmbH
+#
+#   SPDX-License-Identifier: SHL-0.51
+#
+#   Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+#   decreasing_entries_test.S (TST04-4)
+# ------------------------------------------------------------------------------
+
+    .text
+    .globl main
+main:
+
+    # Configure PMP using decreasing entries of TOR.
+
+    # From 0xB000_0000 to 0xC000_0000 Read-Write-Execute.
+    li t0, 0x30000000
+    csrw pmpaddr7, t0
+
+    # From 0xA000_0000 to 0xB000_0000 Read-Write-Execute.
+    li t0, 0x2c000000
+    csrw pmpaddr6, t0
+
+    # From 0x9000_0000 to 0xA000_0000 Read-Write-Execute.
+    li t0, 0x28000000
+    csrw pmpaddr5, t0
+
+    # From 0x8000_0000 to 0x9000_0000 Read-Write-Execute.
+    li t0, 0x24000000
+    csrw pmpaddr4, t0
+
+    # From 0x0002_0000 to 0x8000_0000 no Permissions.
+    li t0, 0x20000000
+    csrw pmpaddr3, t0
+
+    # From 0x0001_0000 to 0x0002_0000 only Execute.
+    li t0, 0x00008000
+    csrw pmpaddr2, t0
+
+    # From 0x0000_1000 to 0x0001_0000 no Permissions.
+    li t0, 0x00004000
+    csrw pmpaddr1, t0
+
+    # From 0x0000_0000 to 0x0000_1000 only Execute.
+    li t0, 0x00000400
+    csrw pmpaddr0, t0
+
+
+    # Addr 4-7 configs, written in cfg1, with LOCK OFF, and TOR.
+    li t0, 0x0f0f0f0f
+    csrw pmpcfg1, t0
+
+    # Addr 0-3 configs, written in cfg0, with LOCK OFF, and TOR.
+    li t0, 0x080c080c
+    csrw pmpcfg0, t0
+
+
+    # Do the READ-WRITE test.
+
+    # Check 1 read-write test, at 0x8800_0000.
+    li t1, 0x88000000
+    li t2, 0xEFFACED1
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+    # Check 2 read-write test, at 0x9800_0000.
+    li t1, 0x98000000
+    li t2, 0xACCEDED2
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+    # Check 3 read-write test, at 0xA800_0000.
+    li t1, 0xA8000000
+    li t2, 0xDEFACED3
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+    # Check 4 read-write test, at 0xB800_0000.
+    li t1, 0xB8000000
+    li t2, 0xDEC0DED4
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+
+pass:
+    # Success post-processing
+    li a0, 0x0;
+    jal exit;
+
+fail:
+    # Failure post-processing
+    li a0, 0x1;
+    jal exit;

verif/tests/custom/pmp/defined_matches_test.S

@@ -0,0 +1,48 @@
+# ------------------------------------------------------------------------------
+#   Copyright 2024 Robert Bosch GmbH
+#
+#   SPDX-License-Identifier: SHL-0.51
+#
+#   Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+#   defined_matches_test.S (TST10-1, TST10-2)
+# ------------------------------------------------------------------------------
+
+    .text
+    .globl main
+main:
+
+    # Check a Memory Access succeeds if no PMP entry is defined.
+    li t1, 0x90000000
+    li t2, 0xC0D1F1ED
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+    # Set up a PMP entry using NAPOT, from 0x8000_0000 to 0xA0000_0000, Read-Write-Execute. 
+    li t0, 0x0000001f
+    csrw pmpcfg0, t0
+    csrr t1, pmpcfg0
+    bne t0, t1, fail
+    li t0, 0x23ffffff
+    csrw pmpaddr0, t0
+    csrr t1, pmpaddr0
+    bne t0, t1, fail
+
+    # Check a memory access succeeds if no PMP entry matches.
+    li t1, 0xB0000000
+    li t2, 0xCA5CADED
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+
+pass:
+    # Success post-processing
+    li a0, 0x0;
+    jal exit;
+
+fail:
+    # Failure post-processing
+    li a0, 0x1;
+    jal exit;

verif/tests/custom/pmp/double_entries_test.S

@@ -0,0 +1,72 @@
+# ------------------------------------------------------------------------------
+#   Copyright 2024 Robert Bosch GmbH
+#
+#   SPDX-License-Identifier: SHL-0.51
+#
+#   Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+#   double_entries_test.S (TST04-2)
+# ------------------------------------------------------------------------------
+
+    .text
+    .globl main
+main:
+
+    # Set up PMP using NAPOT, from 0xB000_0000 to 0xC000_0000, Read-Write.
+    li t0, 0x001b0000
+    csrw pmpcfg1, t0
+    csrr t1, pmpcfg1
+    bne t0, t1, fail
+    li t0, 0x2dffffff
+    csrw pmpaddr6, t0
+    csrr t1, pmpaddr6
+    bne t0, t1, fail
+
+    # Set up PMP using NAPOT, from 0x8000_0000 to 0x9000_0000, Read-Write.
+    li t0, 0x001b0000
+    csrw pmpcfg0, t0
+    csrr t1, pmpcfg0
+    bne t0, t1, fail
+    li t0, 0x21ffffff
+    csrw pmpaddr2, t0
+    csrr t1, pmpaddr2
+    bne t0, t1, fail
+
+    # Read-Write check in 0xB800_0000.
+    li t1, 0xB8000000
+    li t2, 0xC0D1F1ED
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+    # Read-Write check in 0x8800_0000.
+    li t1, 0x88000000
+    li t2, 0xCA5CADED
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+    # Check that all other addr / cfg are zero.
+    csrr t0, pmpaddr0
+    bne t0, zero, fail
+    csrr t0, pmpaddr1
+    bne t0, zero, fail
+    csrr t0, pmpaddr3
+    bne t0, zero, fail
+    csrr t0, pmpaddr4
+    bne t0, zero, fail
+    csrr t0, pmpaddr5
+    bne t0, zero, fail
+    csrr t0, pmpaddr7
+    bne t0, zero, fail
+
+
+pass:
+    # Success post-processing
+    li a0, 0x0;
+    jal exit;
+
+fail:
+    # Failure post-processing
+    li a0, 0x1;
+    jal exit;

verif/tests/custom/pmp/exact_csrr_test.S

@@ -0,0 +1,99 @@
+# ------------------------------------------------------------------------------
+#   Copyright 2024 Robert Bosch GmbH
+#
+#   SPDX-License-Identifier: SHL-0.51
+#
+#   Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+#   exact_csrr_test.S (TST05-1)
+# ------------------------------------------------------------------------------
+
+    .text
+    .globl main
+main:
+
+    # Write in addresses and check what is written.
+
+    # Checking PMP ADDR 0
+    li t0, 0xFACADE00
+    csrw pmpaddr0, t0
+    csrr t1, pmpaddr0
+    bne t0, t1, fail
+    csrw pmpaddr0, zero
+
+    # Checking PMP ADDR 1
+    li t0, 0xFACADE02
+    csrw pmpaddr1, t0
+    csrr t1, pmpaddr1
+    bne t0, t1, fail
+    csrw pmpaddr1, zero
+
+    # Checking PMP ADDR 2
+    li t0, 0xFACADE04
+    csrw pmpaddr2, t0
+    csrr t1, pmpaddr2
+    bne t0, t1, fail
+    csrw pmpaddr2, zero
+
+    # Checking PMP ADDR 3
+    li t0, 0xFACADE06
+    csrw pmpaddr3, t0
+    csrr t1, pmpaddr3
+    bne t0, t1, fail
+    csrw pmpaddr3, zero
+
+    # Checking PMP ADDR 4
+    li t0, 0xFACADE08
+    csrw pmpaddr4, t0
+    csrr t1, pmpaddr4
+    bne t0, t1, fail
+    csrw pmpaddr4, zero
+
+    # Checking PMP ADDR 5
+    li t0, 0xFACADE0A
+    csrw pmpaddr5, t0
+    csrr t1, pmpaddr5
+    bne t0, t1, fail
+    csrw pmpaddr5, zero
+
+    # Checking PMP ADDR 6
+    li t0, 0xFACADE0C
+    csrw pmpaddr6, t0
+    csrr t1, pmpaddr6
+    bne t0, t1, fail
+    csrw pmpaddr6, zero
+
+    # Checking PMP ADDR 7
+    li t0, 0xFACADE0E
+    csrw pmpaddr7, t0
+    csrr t1, pmpaddr7
+    bne t0, t1, fail
+    csrw pmpaddr7, zero
+
+
+    # Write in configurations and check what is written, except for the reserved combinations with R=0 and W=1.
+
+    # Checking PMP CFG 0
+    li t0, 0x01030304
+    csrw pmpcfg0, t0
+    csrr t1, pmpcfg0
+    bne t0, t1, fail
+    csrw pmpcfg0, zero
+
+    # Checking PMP CFG 1
+    li t0, 0x04050507
+    csrw pmpcfg1, t0
+    csrr t1, pmpcfg1
+    bne t0, t1, fail
+    csrw pmpcfg1, zero
+
+
+pass:
+    # Success post-processing
+    li a0, 0x0;
+    jal exit;
+
+fail:
+    # Failure post-processing
+    li a0, 0x1;
+    jal exit;

verif/tests/custom/pmp/granularity_test.S

@@ -0,0 +1,44 @@
+# ------------------------------------------------------------------------------
+#   Copyright 2024 Robert Bosch GmbH
+#
+#   SPDX-License-Identifier: SHL-0.51
+#
+#   Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+#   granularity_test.S (TST01)
+# ------------------------------------------------------------------------------
+
+    .text
+    .globl main
+main:
+
+    # Configure PMP to find its granularity.
+
+    # Write all zeroes in cfg0.
+    li t0, 0
+    csrw pmpcfg0, t0
+
+    # Write all ones in addr0.
+    li t1, -1
+    csrw pmpaddr0, t1
+
+    # Read the value back.
+    csrr t2, pmpaddr0
+
+    # Check for granularity 8 = 2^(1+2) <=> G = 1.
+    # As per: https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/PMP.html
+    # Which states: The PMP grain is 2**G+2. Only a PMP granularity of 8 bytes (G=1) is supported in CVA6.
+    # And from the RISC-V Spec: G is the index of the least-significant bit set, the PMP granularity is 2^(G+2) bytes.
+    li t3, 0xFFFFFFFE
+    bne t2, t3, fail
+
+
+pass:
+    # Success post-processing
+    li a0, 0x0;
+    jal exit;
+
+fail:
+    # Failure post-processing
+    li a0, 0x1;
+    jal exit;

verif/tests/custom/pmp/locked_outside_napot_test.S

@@ -0,0 +1,45 @@
+# ------------------------------------------------------------------------------
+#   Copyright 2024 Robert Bosch GmbH
+#
+#   SPDX-License-Identifier: SHL-0.51
+#
+#   Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+#   locked_outside_napot_test.S (TST14-26, TST14-36)
+# ------------------------------------------------------------------------------
+
+    .text
+    .globl main
+main:
+
+    # Set up PMP using NAPOT, from 0x8000_0000 to 0xB000_0000.
+    li t2, 0x25ffffff
+    csrw pmpaddr0, t2
+
+    # Configure it with LOCK ON, Read-Write-Execute.
+    li t0, 0x0000009f
+    csrw pmpcfg0, t0
+    csrr t1, pmpcfg0
+    bne t0, t1, fail
+
+    # Check pmpaddr after switching to NAPOT (and lock)
+    csrr t0, pmpaddr0
+    bne t0, t2, fail
+
+    # Check a memory access succeeds when outside the LOCKED entry.
+    li t1, 0xB8000000
+    li t2, 0xC0D1F1ED
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+
+pass:
+    # Success post-processing
+    li a0, 0x0;
+    jal exit;
+
+fail:
+    # Failure post-processing
+    li a0, 0x1;
+    jal exit;

verif/tests/custom/pmp/locked_outside_tor_test.S

@@ -0,0 +1,61 @@
+# ------------------------------------------------------------------------------
+#   Copyright 2024 Robert Bosch GmbH
+#
+#   SPDX-License-Identifier: SHL-0.51
+#
+#   Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+#   locked_outside_tor_test.S (TST16-26, TST16-36)
+# ------------------------------------------------------------------------------
+
+    .text
+    .globl main
+main:
+
+    # From 0x0000_0000 to 0x0000_1000 only Execute.
+    li t0, 0x00000400
+    csrw pmpaddr0, t0
+
+    # From 0x0000_1000 to 0x0001_0000 no Permissions.
+    li t0, 0x00004000
+    csrw pmpaddr1, t0
+
+    # From 0x0001_0000 to 0x0002_0000 only Execute.
+    li t0, 0x00008000
+    csrw pmpaddr2, t0
+
+    # From 0x0002_0000 to 0x8000_0000 no Permissions.
+    li t0, 0x20000000
+    csrw pmpaddr3, t0
+
+    # From 0x8000_0000 to 0xB000_0000 Read-Write-Execute.
+    li t0, 0x2C000000
+    csrw pmpaddr4, t0
+
+    # Configure the TOR areas with LOCK ON.
+    li t0, 0x888c888c
+    csrw pmpcfg0, t0
+    csrr t1, pmpcfg0
+    bne t0, t1, fail
+    li t0, 0x0000008f
+    csrw pmpcfg1, t0
+    csrr t1, pmpcfg1
+    bne t0, t1, fail
+
+    # Check a memory access succeeds when outside the LOCKED entry.
+    li t1, 0xB8000000
+    li t2, 0xC0D1F1ED
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+
+pass:
+    # Success post-processing
+    li a0, 0x0;
+    jal exit;
+
+fail:
+    # Failure post-processing
+    li a0, 0x1;
+    jal exit;

verif/tests/custom/pmp/lsu_napot_test.S

@@ -0,0 +1,111 @@
+# ------------------------------------------------------------------------------
+#   Copyright 2024 Robert Bosch GmbH
+#
+#   SPDX-License-Identifier: SHL-0.51
+#
+#   Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+#   lsu_napot_test.S (TST14-11, TST14-21, TST14-31)
+# ------------------------------------------------------------------------------
+
+    .text
+    .globl main
+main:
+
+    # Configure PMP using NAPOT.
+
+    # From 0x0000_0000 to 0x0000_1000 only Execute.
+    li t0, 0x000001ff
+    csrw pmpaddr0, t0
+
+    # From 0x0001_0000 to 0x0002_0000 only Execute.
+    li t0, 0x00005fff
+    csrw pmpaddr1, t0
+
+    # From 0x8000_0000 to 0xC000_0000 Read-Write-Execute.
+    li t0, 0x27ffffff
+    csrw pmpaddr2, t0
+
+
+    # Addr 0-2 configs, written in cfg0, with LOCK OFF, and NAPOT.
+    li t0, 0x001f1c1c
+    csrw pmpcfg0, t0
+    csrr t1, pmpcfg0
+    bne t0, t1, fail
+
+
+    # Do the READ-WRITE test.
+
+    # Check 1 read-write test, at 0x8000_0000.
+    li t1, 0x80000000
+    li t2, 0xEFFACED1
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+    # Check 2 read-write test, at 0x9000_0000.
+    li t1, 0x90000000
+    li t2, 0xACCEDED2
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+    # Check 3 read-write test, at 0xA000_0000.
+    li t1, 0xA0000000
+    li t2, 0xDEFACED3
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+    # Check 4 read-write test, at 0xB000_0000.
+    li t1, 0xB0000000
+    li t2, 0xDEC0DED4
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+
+    # Do the EXEC "RET" test.
+
+    # Exec test 1, at 0x0000_0800.
+    li t0, 0x00000800
+    li t1, 0x8082
+    sw t1, 0(t0)
+    lw t2, 0(t0)
+    bne t1, t2, fail
+    jalr t0
+
+    # Exec test 2, at 0x0001_8000.
+    li t0, 0x00018000
+    li t1, 0x8082
+    sw t1, 0(t0)
+    lw t2, 0(t0)
+    bne t1, t2, fail
+    jalr t0
+
+    # Exec test 3, at 0x9800_0000.
+    li t0, 0x98000000
+    li t1, 0x8082
+    sw t1, 0(t0)
+    lw t2, 0(t0)
+    bne t1, t2, fail
+    jalr t0
+
+    # Exec test 4, at 0xA800_0000.
+    li t0, 0xA8000000
+    li t1, 0x8082
+    sw t1, 0(t0)
+    lw t2, 0(t0)
+    bne t1, t2, fail
+    jalr t0
+
+
+pass:
+    # Success post-processing
+    li a0, 0x0;
+    jal exit;
+
+fail:
+    # Failure post-processing
+    li a0, 0x1;
+    jal exit;

verif/tests/custom/pmp/lsu_tor_test.S

@@ -0,0 +1,125 @@
+# ------------------------------------------------------------------------------
+#   Copyright 2024 Robert Bosch GmbH
+#
+#   SPDX-License-Identifier: SHL-0.51
+#
+#   Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+#   lsu_tor_test.S (TST16-11, TST16-21, TST16-31)
+# ------------------------------------------------------------------------------
+
+    .text
+    .globl main
+main:
+
+    # Configure PMP using TOR.
+
+    # From 0x0000_0000 to 0x0000_1000 only Execute.
+    li t0, 0x00000400
+    csrw pmpaddr0, t0
+
+    # From 0x0000_1000 to 0x0001_0000 no Permissions.
+    li t0, 0x00004000
+    csrw pmpaddr1, t0
+
+    # From 0x0001_0000 to 0x0002_0000 only Execute.
+    li t0, 0x00008000
+    csrw pmpaddr2, t0
+
+    # From 0x0002_0000 to 0x8000_0000 no Permissions.
+    li t0, 0x20000000
+    csrw pmpaddr3, t0
+
+    # From 0x8000_0000 to 0xC000_0000 Read-Write-Execute.
+    li t0, 0x30000000
+    csrw pmpaddr4, t0
+
+
+    # Addr 0-3 configs, written in cfg0, with LOCK OFF, and TOR.
+    li t0, 0x080c080c
+    csrw pmpcfg0, t0
+    csrr t1, pmpcfg0
+    bne t0, t1, fail
+
+    # Addr 4 config, written in cfg1, with LOCK OFF, and TOR.
+    li t0, 0x0000000f
+    csrw pmpcfg1, t0
+    csrr t1, pmpcfg1
+    bne t0, t1, fail
+
+
+    # Do the READ-WRITE test.
+
+    # Check 1 read-write test, at 0x8000_0000.
+    li t1, 0x80000000
+    li t2, 0xEFFACED1
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+    # Check 2 read-write test, at 0x9000_0000.
+    li t1, 0x90000000
+    li t2, 0xACCEDED2
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+    # Check 3 read-write test, at 0xA000_0000.
+    li t1, 0xA0000000
+    li t2, 0xDEFACED3
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+    # Check 4 read-write test, at 0xB000_0000.
+    li t1, 0xB0000000
+    li t2, 0xDEC0DED4
+    sw t2, 0(t1)
+    lw t3, 0(t1)
+    bne t2, t3, fail
+
+
+    # Do the EXEC "RET" test.
+
+    # Exec test 1, at 0x0000_0800.
+    li t0, 0xA0000800
+    li t1, 0x8082
+    sw t1, 0(t0)
+    lw t2, 0(t0)
+    bne t1, t2, fail
+    jalr t0
+
+    # Exec test 2, at 0x0001_8000.
+    li t0, 0xB0018000
+    li t1, 0x8082
+    sw t1, 0(t0)
+    lw t2, 0(t0)
+    bne t1, t2, fail
+    jalr t0
+
+    # Exec test 3, at 0x9800_0000.
+    li t0, 0x98000000
+    li t1, 0x8082
+    sw t1, 0(t0)
+    lw t2, 0(t0)
+    bne t1, t2, fail
+    jalr t0
+
+    # Exec test 4, at 0xA800_0000.
+    li t0, 0xA8000000
+    li t1, 0x8082
+    sw t1, 0(t0)
+    lw t2, 0(t0)
+    bne t1, t2, fail
+    jalr t0
+    
+
+pass:
+    # Success post-processing
+    li a0, 0x0;
+    jal exit;
+
+fail:
+    # Failure post-processing
+    li a0, 0x1;
+    jal exit;

verif/tests/testlist_pmp-cv32a60x.yaml

@@ -0,0 +1,77 @@
+# Copyright 2025 Thales CDI
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https:#solderpad.org/licenses/
+#
+# Original Author: Valentin Thomazic (valentin.thomazic@thalesgroup.com)
+
+# ================================================================================
+#                  Regression test list format
+# --------------------------------------------------------------------------------
+# testlist        : Assembly test list
+# test            : Assembly test name
+# description     : Description of this test
+# gen_opts        : Instruction generator options
+# iterations      : Number of iterations of this test
+# no_iss          : Enable/disable ISS simulator (Optional)
+# gen_test        : Test name used by the instruction generator
+# asm_tests       : Path to directed, hand-coded assembly test file or directory
+# rtl_test        : RTL simulation test name
+# cmp_opts        : Compile options passed to the instruction generator
+# sim_opts        : Simulation options passed to the instruction generator
+# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional)
+# compare_opts    : Options for the RTL & ISS trace comparison
+# gcc_opts        : gcc compile options
+# --------------------------------------------------------------------------------
+
+common_test_config: &common_test_config
+  path_var: TESTS_PATH
+  gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -lgcc"
+
+testlist:
+  - test: decreasing_entries_test
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/custom/pmp/decreasing_entries_test.S
+
+  - test: defined_matches
+    <<: *common_test_config
+    iterations: 0
+    asm_tests: <path_var>/custom/pmp/defined_matches.S
+
+  - test: double_entries_test
+    <<: *common_test_config
+    iterations: 0
+    asm_tests: <path_var>/custom/pmp/double_entries_test.S
+
+  - test: exact_csrr_test
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/custom/pmp/exact_csrr_test.S
+
+  - test: granularity_test
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/custom/pmp/granularity_test.S
+
+  - test: locked_outside_napot_test
+    <<: *common_test_config
+    iterations: 0
+    asm_tests: <path_var>/custom/pmp/locked_outside_napot_test.S
+
+  - test: locked_outside_tor_test
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/custom/pmp/locked_outside_tor_test.S
+
+  - test: lsu_napot_test
+    <<: *common_test_config
+    iterations: 0
+    asm_tests: <path_var>/custom/pmp/lsu_napot_test.S
+
+  - test: lsu_tor_test
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/custom/pmp/lsu_tor_test.S