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Misc majurity fixes (#125)

Browse source 
* Fix latch and timing loop in debu_req

* Fix unconnected IPI signals in CLINT, and unconnected regs in CSR_REGFILE

* Fix several issues with AXI IDs in axi_adapter, add AXI ID width parameter, and assertions testing for invalid read/write data

* Eliminate sim, simc make targets for Questa. Tests can be directly invoked via typing name and optionally specifying the gui-mode.

* Initialize instruction traced shadow regfile to zero at start of simulation

Fix progbuf offsets and tie unsupported counters to zero to avoid propagation of X

Fix printouts of assertions

Modify bootrom to prevent assignment of X to output

* Make separate CI target for AMO tests

* Bump fpga-support version

* Add AMO tests list

* Fix FPU submodule version

* Change core_id + cluster_id into hart_id

* Rename gitlab CI tests

* Replace all SYNTHESIS macros with pragma translate_off

* Update readme, bump common cells, benderize

* Fix torture make target

* Remove unneeded signal
This commit is contained in:
msfschaffner 2018-10-17 11:54:10 +02:00 • committed by Florian Zaruba
parent aa47e4a8be
commit 8468544156
No known key found for this signature in database
GPG key ID: E742FFE8EC38A792
39 changed files with 991 additions and 876 deletions
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62
.gitlab-ci.yml
View file

@ -23,7 +23,8 @@ variables:
stages:
- build
- test_std
- standard
- serpent
# prepare
build:
@ -37,24 +38,63 @@ build:
paths:
- tmp
# rv64ui-p-* and rv64ui-v-* tests
run-asm-tests-questa:
stage: test_std
asm-quest:
stage: standard
script:
- make -j${NUM_JOBS} run-asm-tests
- make -j${NUM_JOBS} run-asm-tests batch-mode=1
dependencies:
- build
run-benchmarks-questa:
stage: test_std
amo-quest:
stage: standard
script:
- make -j${NUM_JOBS} run-benchmarks
- make -j${NUM_JOBS} run-amo-tests batch-mode=1
dependencies:
- build
bench-quest:
stage: standard
script:
- make -j${NUM_JOBS} run-benchmarks batch-mode=1
dependencies:
- build
torture:
stage: test_std
# rv64ui-p-* tests
asm1-ver:
stage: standard
script:
- make torture-rtest
- make -j${NUM_JOBS} run-asm-tests1-verilator
dependencies:
- build
# rv64ui-v-* tests
asm2-ver:
stage: standard
script:
- make -j${NUM_JOBS} run-asm-tests2-verilator
dependencies:
- build
# atomics
amo-ver:
stage: standard
script:
- make -j${NUM_JOBS} run-amo-verilator
dependencies:
- build
bench-ver:
stage: standard
script:
- make -j${NUM_JOBS} run-benchmarks-verilator
dependencies:
- build
torture:
stage: standard
script:
- make torture-rtest
- make torture-rtest-verilator
dependencies:
- build

8
.gitmodules vendored
View file

@ -4,15 +4,12 @@
[submodule "src/axi_node"]
path = src/axi_node
url = https://github.com/pulp-platform/axi_node.git
[submodule "src/fpu"]
path = src/fpu
url = https://github.com/pulp-platform/fpnew.git
[submodule "src/fpga-support"]
path = src/fpga-support
url = https://github.com/pulp-platform/fpga-support.git
[submodule "src/common_cells"]
path = src/common_cells
url = https://github.com/pulp-platform/common_cells.git
url = https://github.com/pulp-platform/common_cells.git
[submodule "src/axi"]
path = src/axi
url = https://github.com/pulp-platform/axi.git
@ -22,3 +19,6 @@
[submodule "src/tech_cells_generic"]
path = src/tech_cells_generic
url = https://github.com/pulp-platform/tech_cells_generic.git
[submodule "src/fpu"]
path = src/fpu
url = https://github.com/pulp-platform/fpnew.git

6
.travis.yml
View file

@ -88,6 +88,12 @@ jobs:
script:
- ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-asm-tests2-verilator
# amo tests
- stage: test
name: run amo tests
script:
- ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-amo-verilator
- stage: test
name: run torture
script:

2
Bender.yml
View file

@ -7,7 +7,7 @@ dependencies:
axi_mem_if: { git: "https://github.com/pulp-platform/axi_mem_if.git", version: 0.2.0 }
axi_node: { git: "https://github.com/pulp-platform/axi_node.git", version: 1.1.1 }
tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.1.1 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.7.5 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.8.0 }
fpga-support: { git: "https://github.com/pulp-platform/fpga-support.git", version: 0.3.2 }
sources:

5
CHANGELOG.md
View file

@ -10,6 +10,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- Commit log feature
- Support for A-Extension
- Preliminary FP support
### Changed
- core_id / cluster_id inputs have been merged to hard_id input
### 3.0.0

119
Makefile
View file

@ -25,7 +25,7 @@ defines ?=
# test name for torture runs (binary name)
test-location ?= output/test
# set to either nothing or -log
torture-logs := -log
torture-logs := -log
# Sources
# Package files -> compile first
@ -99,21 +99,30 @@ root-dir := $(shell pwd)
tbs := tb/ariane_tb.sv tb/ariane_testharness.sv
# RISCV asm tests and benchmark setup (used for CI)
# there is a definesd test-list with selected CI tests
riscv-test-dir := tmp/riscv-tests/build/isa/
riscv-benchmarks-dir := tmp/riscv-tests/build/benchmarks/
riscv-asm-tests-list := ci/riscv-asm-tests.list
riscv-benchmarks-list := ci/riscv-benchmarks.list
riscv-asm-tests := $(shell xargs printf '\n%s' < $(riscv-asm-tests-list) | cut -b 1-)
riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)
# preset which runs a single test
riscv-test ?= rv64ui-p-add
riscv-test-dir := tmp/riscv-tests/build/isa/
riscv-benchmarks-dir := tmp/riscv-tests/build/benchmarks/
riscv-asm-tests-list := ci/riscv-asm-tests.list
riscv-amo-tests-list := ci/riscv-amo-tests.list
riscv-benchmarks-list := ci/riscv-benchmarks.list
riscv-asm-tests := $(shell xargs printf '\n%s' < $(riscv-asm-tests-list) | cut -b 1-)
riscv-amo-tests := $(shell xargs printf '\n%s' < $(riscv-amo-tests-list) | cut -b 1-)
riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)
# Search here for include files (e.g.: non-standalone components)
incdir :=
# Compile and sim flags
compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+$(defines)
compile_flag_vhd += -64 -nologo -quiet -2008
uvm-flags += +UVM_NO_RELNOTES
uvm-flags += +UVM_NO_RELNOTES +UVM_VERBOSITY=LOW
questa-flags += -t 1ns -64 -coverage -classdebug $(gui-sim)
# if defined, calls the questa targets in batch mode
ifdef batch-mode
questa-flags += -c
questa-cmd := -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]"
else
questa-cmd := -do " log -r /*; run -all;"
endif
# Iterate over all include directories and write them with +incdir+ prefixed
# +incdir+ works for Verilator and QuestaSim
list_incdir := $(foreach dir, ${incdir}, +incdir+$(dir))
@ -144,7 +153,7 @@ $(library)/.build-tb: $(dpi) $(tbs)
touch $(library)/.build-tb
$(library):
vlib${questa_version} ${library}
vlib${questa_version} $(library)
# compile DPIs
$(dpi-library)/%.o: tb/dpi/%.cc $(dpi_hdr)
@ -156,50 +165,37 @@ $(dpi-library)/ariane_dpi.so: $(dpi)
# Compile C-code and generate .so file
$(CXX) -shared -m64 -o $(dpi-library)/ariane_dpi.so $? -lfesvr
sim: build
vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
$(QUESTASIM_FLAGS) \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi -do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; log -r /*; run -all; exit" \
${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options)
simc: build
vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
$(QUESTASIM_FLAGS) \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi -do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all; exit" \
${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options)
simc-log: build
vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
$(QUESTASIM_FLAGS) \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi -do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; log -r /*; run -all; exit" \
${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options)
# single test runs on Questa can be started by calling make <testname>, e.g. make towers.riscv
# the test names are defined in ci/riscv-asm-tests.list, and in ci/riscv-benchmarks.list
# if you want to run in batch mode, use make <testname> batch-mode=1
$(riscv-asm-tests): build
vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
$(QUESTASIM_FLAGS) \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
-do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-asm-tests-$@.log
$(riscv-amo-tests): build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-amo-tests-$@.log
$(riscv-benchmarks): build
vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
$(QUESTASIM_FLAGS) \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
-do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized +permissive-off ++$(riscv-benchmarks-dir)/$@ ++$(target-options) | tee tmp/riscv-benchmarks-$@.log
# can use -jX to run ci tests in parallel using X processes
run-asm-tests: $(riscv-asm-tests)
$(MAKE) check-asm-tests
run-amo-tests: $(riscv-amo-tests)
make check-amo-tests
check-asm-tests:
ci/check-tests.sh tmp/riscv-asm-tests- $(shell wc -l $(riscv-asm-tests-list) | awk -F " " '{ print $1 }')
check-amo-tests:
ci/check-tests.sh tmp/riscv-amo-tests- $(shell wc -l $(riscv-amo-tests-list) | awk -F " " '{ print $1 }')
# can use -jX to run ci tests in parallel using X processes
run-benchmarks: $(riscv-benchmarks)
$(MAKE) check-benchmarks
@ -239,16 +235,21 @@ verilate:
$(addsuffix -verilator,$(riscv-asm-tests)): verilate
$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests))
$(addsuffix -verilator,$(riscv-amo-tests)): verilate
$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
$(addsuffix -verilator,$(riscv-benchmarks)): verilate
$(ver-library)/Variane_testharness $(riscv-benchmarks-dir)/$(subst -verilator,,$@)
run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests)) $(addsuffix -verilator, $(riscv-amo-tests))
# split into two halfs for travis jobs (otherwise they will time out)
run-asm-tests1-verilator: $(addsuffix -verilator, $(filter rv64ui-v-% ,$(riscv-asm-tests)))
run-asm-tests2-verilator: $(addsuffix -verilator, $(filter-out rv64ui-v-% ,$(riscv-asm-tests)))
$(addsuffix -verilator,$(riscv-benchmarks)): verilate
$(ver-library)/Variane_testharness $(riscv-benchmarks-dir)/$(subst -verilator,,$@)
run-amo-verilator: $(addsuffix -verilator, $(riscv-amo-tests))
run-benchmarks-verilator: $(addsuffix -verilator,$(riscv-benchmarks))
@ -278,25 +279,19 @@ torture-rtest-verilator: verilate
$(MAKE) check-torture
run-torture: build
vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles)+UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-torture-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
$(QUESTASIM_FLAGS) \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
-do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
${top_level}_optimized +permissive-off \
+signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options)
vsim${questa_version} +permissive $(questa-flags) -c -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-torture-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
-do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
${top_level}_optimized +permissive-off +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options)
run-torture-log: build
vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles)+UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-torture-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
$(QUESTASIM_FLAGS) \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
-do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; coverage save -onexit tmp/$@.ucdb; log -r /*; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
${top_level}_optimized +permissive-off \
+signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options)
vsim${questa_version} +permissive $(questa-flags) -c -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-torture-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
-do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; coverage save -onexit tmp/$@.ucdb; log -r /*; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
${top_level}_optimized +permissive-off +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options)
cp vsim.wlf $(riscv-torture-dir)/$(test-location).wlf
cp trace_core_00_0.log $(riscv-torture-dir)/$(test-location).trace
cp trace_core_00_0_commit.log $(riscv-torture-dir)/$(test-location).commit
cp trace_hart_0000.log $(riscv-torture-dir)/$(test-location).trace
cp trace_hart_0000_commit.log $(riscv-torture-dir)/$(test-location).commit
cp transcript $(riscv-torture-dir)/$(test-location).transcript
run-torture-verilator: verilate

BIN
bootrom/bootrom.img
View file

Binary file not shown.

164
bootrom/bootrom.sv
View file

@ -1,10 +1,10 @@
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the “License”); you may not use this file except in
* License, Version 0.51 (the "License"); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
* this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
@ -20,152 +20,150 @@ module bootrom (
input logic [63:0] addr_i,
output logic [63:0] rdata_o
);
localparam int RomSize = 143;
localparam int RomSize = 141;
const logic [RomSize-1:0][63:0] mem = {
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64'h00000000_4B000000,
64'h10000000_03000000,
64'h00007972_6f6d656d,
64'h3f000000_07000000,
64'h00007972_6F6D656D,
64'h3F000000_07000000,
64'h03000000_00303030,
64'h30303030_38407972,
64'h6f6d656d_01000000,
64'h6F6D656D_01000000,
64'h02000000_02000000,
64'h02000000_01000000,
64'ha5000000_04000000,
64'h03000000_01000000,
64'h9f000000_04000000,
64'h9F000000_04000000,
64'h03000000_00006374,
64'h6e692d75_70632c76,
64'h63736972_1b000000,
64'h0f000000_03000000,
64'h8a000000_00000000,
64'h6E692D75_70632C76,
64'h63736972_1B000000,
64'h0F000000_03000000,
64'h8A000000_00000000,
64'h03000000_01000000,
64'h79000000_04000000,
64'h03000000_00000000,
64'h72656c6c_6f72746e,
64'h6f632d74_70757272,
64'h65746e69_01000000,
64'h00ca9a3b_69000000,
64'h72656C6C_6F72746E,
64'h6F632D74_70757272,
64'h65746E69_01000000,
64'h00CA9A3B_69000000,
64'h04000000_03000000,
64'h00003933_76732c76,
64'h00003933_76732C76,
64'h63736972_60000000,
64'h0b000000_03000000,
64'h00636d69_34367672,
64'h0B000000_03000000,
64'h00636D69_34367672,
64'h56000000_08000000,
64'h03000000_00000076,
64'h63736972_1b000000,
64'h63736972_1B000000,
64'h06000000_03000000,
64'h00000000_79616b6f,
64'h4f000000_05000000,
64'h00000000_79616B6F,
64'h4F000000_05000000,
64'h03000000_00000000,
64'h4b000000_04000000,
64'h4B000000_04000000,
64'h03000000_00757063,
64'h3f000000_04000000,
64'h3F000000_04000000,
64'h03000000_00000030,
64'h40757063_01000000,
64'h80969800_2c000000,
64'h80969800_2C000000,
64'h04000000_03000000,
64'h00000000_0f000000,
64'h00000000_0F000000,
64'h04000000_03000000,
64'h01000000_00000000,
64'h04000000_03000000,
64'h00000000_73757063,
64'h01000000_00657261,
64'h622d656e_61697261,
64'h2c687465_26000000,
64'h622D656E_61697261,
64'h2C687465_26000000,
64'h10000000_03000000,
64'h00766564_2d657261,
64'h622d656e_61697261,
64'h2c687465_1b000000,
64'h00766564_2D657261,
64'h622D656E_61697261,
64'h2C687465_1B000000,
64'h14000000_03000000,
64'h02000000_0f000000,
64'h02000000_0F000000,
64'h04000000_03000000,
64'h02000000_00000000,
64'h04000000_03000000,
64'h00000000_01000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'hf8020000_c8000000,
64'hE8020000_C2000000,
64'h00000000_10000000,
64'h11000000_28000000,
64'h30030000_38000000,
64'hf8030000_edfe0dd0,
64'h20030000_38000000,
64'hE2030000_EDFE0DD0,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_0000bff5,
64'h10500073_03c58593,
64'h00000597_f1402573,
64'h00000000_0000BFF5,
64'h10500073_03C58593,
64'h00000597_F1402573,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00008402_07458593,
64'h00000597_f1402573,
64'h01f41413_0010041b
64'h00000597_F1402573,
64'h01F41413_0010041B
};
logic [$clog2(RomSize)-1:0] addr_q;
@ -176,5 +174,7 @@ module bootrom (
end
end
assign rdata_o = mem[addr_q];
// this prevents spurious Xes from propagating into
// the speculative fetch stage of the core
assign rdata_o = (addr_q<RomSize) ? mem[addr_q] : '0;
endmodule

12
bootrom/gen_rom.py
View file

@ -22,11 +22,11 @@ filename = os.path.splitext(file)[0]
license = """\
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the “License”); you may not use this file except in
* License, Version 0.51 (the "License"); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
* this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
@ -59,7 +59,9 @@ module $filename (
end
end
assign rdata_o = mem[addr_q];
// this prevents spurious Xes from propagating into
// the speculative fetch stage of the core
assign rdata_o = (addr_q<RomSize) ? mem[addr_q] : '0;
endmodule
"""
@ -75,11 +77,11 @@ with open(filename + ".img", "rb") as f:
if i == 4:
word = "_" + word
if byte:
word = byte.hex() + word
word = ("%02X" % int.from_bytes(byte, "little")) + word
# fill up with zeros if unaligned
else:
pass
# word += "00";
word = "00" + word;
if word != "_":
word = "64'h" + word

2
ci/check-tests.sh
View file

@ -2,7 +2,7 @@
# check simulation output (only for questasim flow)
#
# $1 simulation output file basename
# $2 list file containing the test names
# $2 number of tests to check
#
ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)

2
ci/default.config
View file

@ -1,4 +1,4 @@
torture.generator.nseqs 1000
torture.generator.nseqs 200
torture.generator.memsize 1024
torture.generator.fprnd 0
torture.generator.amo true

8
ci/gitlab-ci-emul.sh
View file

@ -46,7 +46,7 @@ make -j${NUM_JOBS} run-benchmarks-verilator
make -j${NUM_JOBS} torture-rtest-verilator
# run asm tests on questa
make -j${NUM_JOBS} build
make -j${NUM_JOBS} run-asm-tests
make -j${NUM_JOBS} run-benchmarks
make -j${NUM_JOBS} torture-rtest
make -j${NUM_JOBS} build batch-mode=1
make -j${NUM_JOBS} run-asm-tests batch-mode=1
make -j${NUM_JOBS} run-benchmarks batch-mode=1
make -j${NUM_JOBS} torture-rtest batch-mode=1

2
ci/path-setup.sh
View file

@ -5,7 +5,7 @@ export CI_BUILD_DIR=$TOP/ariane-repo
#customize this to your setup
export QUESTASIM_HOME=
export QUESTASIM_VERSION=
export QUESTASIM_FLAGS=
export QUESTASIM_FLAGS=-noautoldlibpath
export CXX=g++-7 CC=gcc-7
# where to install the tools

38
ci/riscv-amo-tests.list Normal file
View file

@ -0,0 +1,38 @@
rv64ua-p-amoadd_d
rv64ua-p-amoadd_w
rv64ua-p-amoor_d
rv64ua-p-amoor_w
rv64ua-p-amoand_d
rv64ua-p-amoand_w
rv64ua-p-amoswap_d
rv64ua-p-amoswap_w
rv64ua-p-amoxor_d
rv64ua-p-amoxor_w
rv64ua-p-amomax_d
rv64ua-p-amomaxu_d
rv64ua-p-amomaxu_w
rv64ua-p-amomax_w
rv64ua-p-amomin_d
rv64ua-p-amomin_w
rv64ua-p-amominu_d
rv64ua-p-amominu_w
rv64ua-p-lrsc
rv64ua-v-amoadd_d
rv64ua-v-amoadd_w
rv64ua-v-amoor_d
rv64ua-v-amoor_w
rv64ua-v-amoand_d
rv64ua-v-amoand_w
rv64ua-v-amoswap_d
rv64ua-v-amoswap_w
rv64ua-v-amoxor_d
rv64ua-v-amoxor_w
rv64ua-v-amomax_d
rv64ua-v-amomaxu_d
rv64ua-v-amomaxu_w
rv64ua-v-amomax_w
rv64ua-v-amomin_d
rv64ua-v-amomin_w
rv64ua-v-amominu_d
rv64ua-v-amominu_w
rv64ua-v-lrsc

38
ci/riscv-asm-tests.list
View file

@ -127,41 +127,3 @@ rv64um-v-divw
rv64um-v-divuw
rv64um-v-remw
rv64um-v-remuw
rv64ua-p-amoadd_d
rv64ua-p-amoadd_w
rv64ua-p-amoor_d
rv64ua-p-amoor_w
rv64ua-p-amoand_d
rv64ua-p-amoand_w
rv64ua-p-amoswap_d
rv64ua-p-amoswap_w
rv64ua-p-amoxor_d
rv64ua-p-amoxor_w
rv64ua-p-amomax_d
rv64ua-p-amomaxu_d
rv64ua-p-amomaxu_w
rv64ua-p-amomax_w
rv64ua-p-amomin_d
rv64ua-p-amomin_w
rv64ua-p-amominu_d
rv64ua-p-amominu_w
rv64ua-p-lrsc
rv64ua-v-amoadd_d
rv64ua-v-amoadd_w
rv64ua-v-amoor_d
rv64ua-v-amoor_w
rv64ua-v-amoand_d
rv64ua-v-amoand_w
rv64ua-v-amoswap_d
rv64ua-v-amoswap_w
rv64ua-v-amoxor_d
rv64ua-v-amoxor_w
rv64ua-v-amomax_d
rv64ua-v-amomaxu_d
rv64ua-v-amomaxu_w
rv64ua-v-amomax_w
rv64ua-v-amomin_d
rv64ua-v-amomin_w
rv64ua-v-amominu_d
rv64ua-v-amominu_w
rv64ua-v-lrsc

31
src/ariane.sv
View file

@ -13,11 +13,11 @@
// Description: Ariane Top-level module
import ariane_pkg::*;
`ifndef verilator
`ifndef SYNTHESIS
//pragma translate_off
`ifndef VERILATOR
import instruction_tracer_pkg::*;
`endif
`endif
//pragma translate_on
module ariane #(
parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000, // address on which to decide whether the request is cache-able or not
@ -28,9 +28,8 @@ module ariane #(
input logic rst_ni,
// Core ID, Cluster ID and boot address are considered more or less static
input logic [63:0] boot_addr_i, // reset boot address
input logic [ 3:0] core_id_i, // core id in a multicore environment (reflected in a CSR)
input logic [ 5:0] cluster_id_i, // PULP specific if core is used in a clustered environment
// Instruction memory interface
input logic [63:0] hart_id_i, // hart id in a multicore environment (reflected in a CSR)
// Instruction memory interface
AXI_BUS.Master instr_if,
// Data memory interface
AXI_BUS.Master data_if, // data cache refill port
@ -593,8 +592,8 @@ module ariane #(
// -------------------
// Instruction Tracer
// -------------------
`ifndef SYNTHESIS
`ifndef verilator
//pragma translate_off
`ifndef VERILATOR
instruction_tracer_if tracer_if (clk_i);
// assign instruction tracer interface
// control signals
@ -631,23 +630,18 @@ module ariane #(
// assign current privilege level
assign tracer_if.priv_lvl = priv_lvl;
assign tracer_if.debug_mode = debug_mode;
instr_tracer instr_tracer_i (tracer_if, cluster_id_i, core_id_i);
`endif
`endif
instr_tracer instr_tracer_i (tracer_if, hart_id_i);
`ifndef SYNTHESIS
`ifndef verilator
program instr_tracer (
instruction_tracer_if tracer_if,
input logic [5:0] cluster_id_i,
input logic [3:0] core_id_i
input logic [63:0] hart_id_i
);
instruction_tracer it = new (tracer_if, 1'b0);
initial begin
#15ns;
it.create_file(cluster_id_i, core_id_i);
it.create_file(hart_id_i);
it.trace();
end
@ -662,7 +656,7 @@ module ariane #(
logic [63:0] cycles;
initial begin
f = $fopen("trace_core_00_0.dasm", "w");
f = $fopen("trace_hart_00.dasm", "w");
end
always_ff @(posedge clk_i or negedge rst_ni) begin
@ -701,6 +695,7 @@ module ariane #(
$fclose(f);
end
`endif
`endif
//pragma translate_on
endmodule // ariane

57
src/axi_adapter.sv
View file

@ -100,7 +100,7 @@ module axi_adapter #(
axi.r_ready = 1'b0;
gnt_o = 1'b0;
gnt_id_o = '0;
gnt_id_o = id_i;
valid_o = 1'b0;
id_o = axi.r_id;
@ -134,18 +134,15 @@ module axi_adapter #(
axi.w_last = 1'b1;
// single req can be granted here
gnt_o = axi.aw_ready & axi.w_ready;
gnt_id_o = id_i;
case ({axi.aw_ready, axi.w_ready})
2'b11: state_d = WAIT_B_VALID;
2'b01: state_d = WAIT_AW_READY;
2'b10: state_d = WAIT_LAST_W_READY;
default: state_d = IDLE;
endcase
id_d = axi.aw_id;
// its a request for the whole cache line
end else begin
axi.aw_len = BURST_SIZE; // number of bursts to do
axi.w_last = 1'b0;
axi.w_data = wdata_i[0];
axi.w_strb = be_i[0];
@ -160,8 +157,6 @@ module axi_adapter #(
2'b10: state_d = WAIT_LAST_W_READY;
default:;
endcase
// save id
id_d = axi.aw_id;
end
// read
@ -169,8 +164,7 @@ module axi_adapter #(
axi.ar_valid = 1'b1;
gnt_o = axi.ar_ready;
gnt_id_o = id_i;
if (type_i != SINGLE_REQ) begin
axi.ar_len = BURST_SIZE;
cnt_d = BURST_SIZE;
@ -179,20 +173,19 @@ module axi_adapter #(
if (axi.ar_ready) begin
state_d = (type_i == SINGLE_REQ) ? WAIT_R_VALID : WAIT_R_VALID_MULTIPLE;
addr_offset_d = addr_i[ADDR_INDEX-1+3:3];
// save id
id_d = axi.ar_id;
end
end
end
end
// ~> from single write, write request has already been granted
// ~> from single write
WAIT_AW_READY: begin
axi.aw_valid = 1'b1;
axi.aw_len = 8'b0;
if (axi.aw_ready)
if (axi.aw_ready) begin
gnt_o = 1'b1;
state_d = WAIT_B_VALID;
end
end
@ -200,7 +193,7 @@ module axi_adapter #(
WAIT_LAST_W_READY_AW_READY: begin
axi.w_valid = 1'b1;
axi.w_last = (cnt_q == '0) ? 1'b1 : 1'b0;
axi.w_last = (cnt_q == '0);
if (type_i == SINGLE_REQ) begin
axi.w_data = wdata_i[0];
axi.w_strb = be_i[0];
@ -225,9 +218,8 @@ module axi_adapter #(
2'b11: begin
// we are finished
if (cnt_q == 0) begin
state_d = WAIT_B_VALID;
gnt_o = 1'b1;
gnt_id_o = id_q;
state_d = WAIT_B_VALID;
gnt_o = 1'b1;
// there are outstanding transactions
end else begin
state_d = WAIT_LAST_W_READY;
@ -245,35 +237,29 @@ module axi_adapter #(
axi.aw_len = BURST_SIZE;
if (axi.aw_ready) begin
state_d = WAIT_B_VALID;
gnt_o = 1'b1;
gnt_id_o = id_q;
state_d = WAIT_B_VALID;
gnt_o = 1'b1;
end
end
// ~> from write, there is an outstanding write
WAIT_LAST_W_READY: begin
axi.w_valid = 1'b1;
if (type_i == SINGLE_REQ) begin
axi.w_data = wdata_i[0];
axi.w_strb = be_i[0];
end else begin
if (type_i != SINGLE_REQ) begin
axi.w_data = wdata_i[BURST_SIZE-cnt_q];
axi.w_strb = be_i[BURST_SIZE-cnt_q];
end
// this is the last write
axi.w_last = (cnt_q == '0) ? 1'b1 : 1'b0;
if (axi.w_ready) begin
// last write -> go to WAIT_B_VALID
if (cnt_q == '0) begin
state_d = WAIT_B_VALID;
gnt_o = (cnt_q == '0);
gnt_id_o = id_q;
end else begin
cnt_d = cnt_q - 1;
if (cnt_q == '0) begin
axi.w_last = 1'b1;
if (axi.w_ready) begin
state_d = WAIT_B_VALID;
gnt_o = 1'b1;
end
end else if (axi.w_ready) begin
cnt_d = cnt_q - 1;
end
end
@ -316,6 +302,7 @@ module axi_adapter #(
// this is the last read
if (axi.r_last) begin
id_d = axi.r_id;
state_d = COMPLETE_READ;
end

6
src/cache_subsystem/cache_ctrl.sv
View file

@ -422,8 +422,8 @@ module cache_ctrl #(
end
end
`ifndef SYNTHESIS
`ifndef verilator
//pragma translate_off
`ifndef VERILATOR
initial begin
assert (DCACHE_LINE_WIDTH == 128) else $error ("Cacheline width has to be 128 for the moment. But only small changes required in data select logic");
end
@ -432,5 +432,5 @@ module cache_ctrl #(
// there should never be a valid answer when the MSHR matches
no_valid_on_mshr_match: assert property(@(posedge clk_i) disable iff (rst_ni !== 1'b0) mshr_addr_matches_i -> !req_port_o.data_rvalid) else $fatal ("rvalid_o should not be set on MSHR match");
`endif
`endif
//pragma translate_on
endmodule

12
src/cache_subsystem/miss_handler.sv
View file

@ -492,13 +492,13 @@ module miss_handler #(
end
end
`ifndef SYNTHESIS
//pragma translate_off
`ifndef VERILATOR
// assert that cache only hits on one way
assert property (
@(posedge clk_i) $onehot0(evict_way_q)) else $warning("Evict-way should be one-hot encoded");
`endif
`endif
//pragma translate_on
// ----------------------
// Bypass Arbiter
// ----------------------
@ -632,11 +632,11 @@ module miss_handler #(
end
end
`ifndef SYNTHESIS
//pragma translate_off
initial begin
assert (AXI_ID_WIDTH >= $clog2(NR_PORTS)) else $fatal (1, "AXI ID Width needs to be larger than number of requestors");
end
`endif
//pragma translate_on
endmodule
@ -762,7 +762,7 @@ module arbiter #(
// Assertions
// ------------
`ifndef SYNTHESIS
//pragma translate_off
`ifndef VERILATOR
// make sure that we eventually get an rvalid after we received a grant
assert property (@(posedge clk_i) data_gnt_i |-> ##[1:$] data_rvalid_i )
@ -775,5 +775,5 @@ module arbiter #(
else begin $error("address contains X when request is set"); $stop(); end
`endif
`endif
//pragma translate_on
endmodule

35
src/cache_subsystem/std_cache_subsystem.sv
View file

@ -22,7 +22,8 @@ import ariane_pkg::*;
import std_cache_pkg::*;
module std_cache_subsystem #(
parameter logic [63:0] CACHE_START_ADDR = 64'h4000_0000
parameter int unsigned AXI_ID_WIDTH = 10,
parameter logic [63:0] CACHE_START_ADDR = 64'h4000_0000
)(
input logic clk_i,
input logic rst_ni,
@ -73,6 +74,7 @@ module std_cache_subsystem #(
// Port 1: Load Unit
// Port 2: Store Unit
std_nbdcache #(
.AXI_ID_WIDTH ( AXI_ID_WIDTH ),
.CACHE_START_ADDR ( CACHE_START_ADDR )
) i_nbdcache (
.clk_i ( clk_i ),
@ -89,4 +91,35 @@ module std_cache_subsystem #(
.amo_resp_o ( amo_resp_o )
);
///////////////////////////////////////////////////////
// assertions
///////////////////////////////////////////////////////
//pragma translate_off
`ifndef VERILATOR
a_invalid_instruction_fetch: assert property (
@(posedge clk_i) disable iff (~rst_ni) icache_dreq_o.valid |-> (|icache_dreq_o.data) !== 1'hX)
else $warning(1,"[l1 dcache] reading invalid instructions: vaddr=%08X, data=%08X",
icache_dreq_o.vaddr, icache_dreq_o.data);
a_invalid_write_data: assert property (
@(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_i[2].data_req |-> |dcache_req_ports_i[2].data_be |-> (|dcache_req_ports_i[2].data_wdata) !== 1'hX)
else $warning(1,"[l1 dcache] writing invalid data: paddr=%016X, be=%02X, data=%016X",
{dcache_req_ports_i[2].address_tag, dcache_req_ports_i[2].address_index}, dcache_req_ports_i[2].data_be, dcache_req_ports_i[2].data_wdata);
generate
for(genvar j=0; j<2; j++) begin
a_invalid_read_data: assert property (
@(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_o[j].data_rvalid |-> (|dcache_req_ports_o[j].data_rdata) !== 1'hX)
else $warning(1,"[l1 dcache] reading invalid data on port %01d: data=%016X",
j, dcache_req_ports_o[j].data_rdata);
end
endgenerate
`endif
//pragma translate_on
endmodule // std_cache_subsystem

14
src/cache_subsystem/std_nbdcache.sv
View file

@ -16,6 +16,7 @@ import ariane_pkg::*;
import std_cache_pkg::*;
module std_nbdcache #(
parameter int unsigned AXI_ID_WIDTH = 10,
parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000
)(
input logic clk_i, // Clock
@ -125,6 +126,7 @@ module std_nbdcache #(
// Miss Handling Unit
// ------------------
miss_handler #(
.AXI_ID_WIDTH ( AXI_ID_WIDTH ),
.NR_PORTS ( 3 )
) i_miss_handler (
.flush_i ( flush_i ),
@ -248,12 +250,12 @@ module std_nbdcache #(
);
`ifndef SYNTHESIS
//pragma translate_off
initial begin
assert ($bits(data_if.aw_addr) == 64) else $fatal(1, "Ariane needs a 64-bit bus");
assert (DCACHE_LINE_WIDTH/64 inside {2, 4, 8, 16}) else $fatal(1, "Cache line size needs to be a power of two multiple of 64");
end
`endif
//pragma translate_on
endmodule
// --------------
@ -332,13 +334,13 @@ module tag_cmp #(
break;
end
`ifndef SYNTHESIS
`ifndef VERILATOR
//pragma translate_off
`ifndef VERILATOR
// assert that cache only hits on one way
assert property (
@(posedge clk_i) $onehot0(hit_way_o)) else begin $error("Hit should be one-hot encoded"); $stop(); end
`endif
`endif
`endif
//pragma translate_on
end
always_ff @(posedge clk_i or negedge rst_ni) begin

16
src/clint/axi_lite_interface.sv
View file

@ -156,14 +156,14 @@ module axi_lite_interface #(
// Assertions
// ------------------------
// Listen for illegal transactions
`ifndef SYNTHESIS
//pragma translate_off
`ifndef VERILATOR
// check that burst length is just one
assert property (@(posedge clk_i) slave.ar_valid |-> ((slave.ar_len == 8'b0)))
else begin $error("AXI Lite does not support bursts larger than 1 or byte length unequal to the native bus size"); $stop(); end
// do the same for the write channel
assert property (@(posedge clk_i) slave.aw_valid |-> ((slave.aw_len == 8'b0)))
else begin $error("AXI Lite does not support bursts larger than 1 or byte length unequal to the native bus size"); $stop(); end
`endif
// check that burst length is just one
assert property (@(posedge clk_i) slave.ar_valid |-> ((slave.ar_len == 8'b0)))
else begin $error("AXI Lite does not support bursts larger than 1 or byte length unequal to the native bus size"); $stop(); end
// do the same for the write channel
assert property (@(posedge clk_i) slave.aw_valid |-> ((slave.aw_len == 8'b0)))
else begin $error("AXI Lite does not support bursts larger than 1 or byte length unequal to the native bus size"); $stop(); end
`endif
//pragma translate_on
endmodule

8
src/clint/clint.sv
View file

@ -52,6 +52,9 @@ module clint #(
// increase the timer
logic increase_timer;
// currently not implemented
assign ipi_o = '0;
// -----------------------------
// AXI Interface Logic
// -----------------------------
@ -170,12 +173,13 @@ module clint #(
// -------------
// Assertions
// --------------
`ifndef SYNTHESIS
//pragma translate_off
`ifndef VERILATOR
// Static assertion check for appropriate bus width
initial begin
assert (AXI_DATA_WIDTH == 64) else $fatal("Timer needs to interface with a 64 bit bus, everything else is not supported");
end
`endif
`endif
//pragma translate_on
endmodule

18
src/csr_regfile.sv
View file

@ -28,9 +28,8 @@ module csr_regfile #(
input scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_i, // the instruction we want to commit
input logic [NR_COMMIT_PORTS-1:0] commit_ack_i, // Commit acknowledged a instruction -> increase instret CSR
// Core and Cluster ID
input logic [3:0] core_id_i, // Core ID is considered static
input logic [5:0] cluster_id_i, // Cluster ID is considered static
input logic [63:0] boot_addr_i, // Address from which to start booting, mtvec is set to the same address
input logic [63:0] hart_id_i, // Hart id in a multicore environment (reflected in a CSR)
// we are taking an exception
input exception_t ex_i, // We've got an exception from the commit stage, take its
@ -230,7 +229,7 @@ module csr_regfile #(
riscv::CSR_MVENDORID: csr_rdata = 64'b0; // not implemented
riscv::CSR_MARCHID: csr_rdata = ARIANE_MARCHID;
riscv::CSR_MIMPID: csr_rdata = 64'b0; // not implemented
riscv::CSR_MHARTID: csr_rdata = {53'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]};
riscv::CSR_MHARTID: csr_rdata = hart_id_i;
riscv::CSR_MCYCLE: csr_rdata = cycle_q;
riscv::CSR_MINSTRET: csr_rdata = instret_q;
// custom (non RISC-V) cache control
@ -321,6 +320,9 @@ module csr_regfile #(
en_ld_st_translation_d = en_ld_st_translation_q;
dirty_fp_state_csr = 1'b0;
pmpcfg0_d = pmpcfg0_q;
pmpaddr0_d = pmpaddr0_q;
// check for correct access rights and that we are writing
if (csr_we) begin
case (csr_addr.address)
@ -952,6 +954,9 @@ module csr_regfile #(
dscratch0_q <= 64'b0;
// machine mode registers
mstatus_q <= 64'b0;
// m-mode protection
pmpcfg0_q <= '0;
pmpaddr0_q <= '0;
// set to boot address + direct mode + 4 byte offset which is the initial trap
mtvec_rst_load_q <= 1'b1;
mtvec_q <= '0;
@ -1002,6 +1007,9 @@ module csr_regfile #(
mtval_q <= mtval_d;
dcache_q <= dcache_d;
icache_q <= icache_d;
// m-mode protection
pmpcfg0_q <= pmpcfg0_d;
pmpaddr0_q <= pmpaddr0_d;
// supervisor mode registers
sepc_q <= sepc_d;
scause_q <= scause_d;
@ -1022,12 +1030,12 @@ module csr_regfile #(
//-------------
// Assertions
//-------------
`ifndef SYNTHESIS
//pragma translate_off
`ifndef VERILATOR
// check that eret and ex are never valid together
assert property (
@(posedge clk_i) !(eret_o && ex_i.valid))
else begin $error("eret and exception should never be valid at the same time"); $stop(); end
`endif
`endif
//pragma translate_on
endmodule

29
src/debug/debug_rom/debug_rom.sv
View file

@ -1,10 +1,10 @@
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the “License”); you may not use this file except in
* License, Version 0.51 (the "License"); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
* this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
@ -20,21 +20,22 @@ module debug_rom (
input logic [63:0] addr_i,
output logic [63:0] rdata_o
);
localparam int RomSize = 12;
localparam int RomSize = 13;
const logic [RomSize-1:0][63:0] mem = {
64'h7b200073_7b202473,
64'h10802423_f1402473,
64'h00000000_00000000,
64'h7B200073_7B202473,
64'h10802423_F1402473,
64'h30000067_10002223,
64'h7b202473_00100073,
64'h10002623_fddff06f,
64'hfc0418e3_00247413,
64'h40044403_f1402473,
64'h7B202473_00100073,
64'h10002623_FDDFF06F,
64'hFC0418E3_00247413,
64'h40044403_F1402473,
64'h02041063_00147413,
64'h40044403_10802023,
64'hf1402473_7b241073,
64'h0ff0000f_0340006f,
64'h04c0006f_00c0006f
64'hF1402473_7B241073,
64'h0FF0000F_0340006F,
64'h04C0006F_00C0006F
};
logic [$clog2(RomSize)-1:0] addr_q;
@ -45,5 +46,7 @@ module debug_rom (
end
end
assign rdata_o = mem[addr_q];
// this prevents spurious Xes from propagating into
// the speculative fetch stage of the core
assign rdata_o = (addr_q<RomSize) ? mem[addr_q] : '0;
endmodule

37
src/debug/dm_csrs.sv
View file

@ -90,6 +90,11 @@ module dm_csrs #(
logic [31:0] haltsum0, haltsum1, haltsum2, haltsum3;
// TODO(zarubaf) Need an elegant way to calculate haltsums
// remove assertions below when implemented...
assign haltsum0 = '0;
assign haltsum1 = '0;
assign haltsum2 = '0;
assign haltsum3 = '0;
for (genvar i = 0; i < 32; i++) begin
// assign haltsum0[i] = halted_i[i];
// TODO(zarubaf) Implement correct haltsum logic
@ -201,7 +206,7 @@ module dm_csrs #(
end
if (!cmdbusy_i) begin
// check whether we need to re-execute the command (just give a cmd_valid)
cmd_valid_o = abstractauto_q.autoexecdata[dmi_req_i.addr[3:0] - dm::Data0];
cmd_valid_o = abstractauto_q.autoexecdata[dmi_req_i.addr[3:0] - int'(dm::Data0)];
end
end
dm::DMControl: resp_queue_data = dmcontrol_q;
@ -215,7 +220,8 @@ module dm_csrs #(
resp_queue_data = progbuf_q[dmi_req_i.addr[4:0]];
if (!cmdbusy_i) begin
// check whether we need to re-execute the command (just give a cmd_valid)
cmd_valid_o = abstractauto_q.autoexecprogbuf[dmi_req_i.addr[3:0]];
// TODO(zarubaf): check if offset is correct - without it this may assign Xes
cmd_valid_o = abstractauto_q.autoexecprogbuf[dmi_req_i.addr[3:0]+16];
end
end
dm::HaltSum0: resp_queue_data = haltsum0;
@ -272,7 +278,7 @@ module dm_csrs #(
if (!cmdbusy_i && dm::DataCount > 0) begin
data_d[dmi_req_i.addr[4:0]] = dmi_req_i.data;
// check whether we need to re-execute the command (just give a cmd_valid)
cmd_valid_o = abstractauto_q.autoexecdata[dmi_req_i.addr[3:0] - dm::Data0];
cmd_valid_o = abstractauto_q.autoexecdata[dmi_req_i.addr[3:0] - int'(dm::Data0)];
end
end
dm::DMControl: begin
@ -327,7 +333,8 @@ module dm_csrs #(
progbuf_d[dmi_req_i.addr[4:0]] = dmi_req_i.data;
// check whether we need to re-execute the command (just give a cmd_valid)
// this should probably throw an error if executed during another command was busy
cmd_valid_o = abstractauto_q.autoexecprogbuf[dmi_req_i.addr[3:0]];
// TODO(zarubaf): check if offset is correct - without it this may assign Xes
cmd_valid_o = abstractauto_q.autoexecprogbuf[dmi_req_i.addr[3:0]+16];
end
end
dm::SBCS: begin
@ -529,4 +536,24 @@ module dm_csrs #(
end
end
end
endmodule
///////////////////////////////////////////////////////
// assertions
///////////////////////////////////////////////////////
//pragma translate_off
`ifndef VERILATOR
haltsum: assert property (
@(posedge clk_i) disable iff (~rst_ni) (dmi_req_ready_o && dmi_req_valid_i && dtm_op == dm::DTM_READ) |->
!({1'b0, dmi_req_i.addr} inside {dm::HaltSum0, dm::HaltSum1, dm::HaltSum2, dm::HaltSum3}))
else $warning("Haltsums are not implemented yet and always return 0.");
`endif
//pragma translate_on
endmodule

6
src/debug/dm_sba.sv
View file

@ -154,11 +154,11 @@ module dm_sba (
);
`ifndef SYNTHESIS
`ifndef verilator
//pragma translate_off
`ifndef VERILATOR
// maybe bump severity to $error if not handled at runtime
dm_sba_access_size: assert property(@(posedge clk_i) disable iff (dmactive_i !== 1'b0) (state_d != Idle) |-> (sbaccess_i < 4)) else $warning ("accesses > 8 byte not supported at the moment");
`endif
`endif
//pragma translate_on
endmodule

2
src/debug/dm_top.sv
View file

@ -48,7 +48,7 @@ module dm_top #(
// Debug CSRs
dm::hartinfo_t [NrHarts-1:0] hartinfo;
logic [NrHarts-1:0] halted;
logic [NrHarts-1:0] running;
// logic [NrHarts-1:0] running;
logic [NrHarts-1:0] resumeack;
logic [NrHarts-1:0] haltreq;
logic [NrHarts-1:0] resumereq;

2
src/fpga-support

@ -1 +1 @@
Subproject commit 3e925e169bd02ebf26e3d4ab65cd1832319cf580
Subproject commit 20cccce06886ef21f263e63dbb38b008ff87419e

1063
src/fpu_wrap.sv
View file

File diff suppressed because it is too large Load diff

6
src/issue_read_operands.sv
View file

@ -437,8 +437,8 @@ module issue_read_operands #(
end
end
`ifndef SYNTHESIS
`ifndef verilator
//pragma translate_off
`ifndef VERILATOR
assert property (
@(posedge clk_i) (branch_valid_q) |-> (!$isunknown(operand_a_q) && !$isunknown(operand_b_q)))
else $warning ("Got unknown value in one of the operands");
@ -447,7 +447,7 @@ module issue_read_operands #(
assert (NR_COMMIT_PORTS == 2) else $error("Only two commit ports are supported at the moment!");
end
`endif
`endif
//pragma translate_on
endmodule

5
src/lsu_arbiter.sv
View file

@ -120,7 +120,7 @@ module lsu_arbiter (
);
`ifndef SYNTHESIS
//pragma translate_off
`ifndef VERILATOR
// check fifo control signals
assert property (@(posedge clk_i) disable iff (~rst_ni) ld_full |-> !ld_valid_i) else $fatal ("cannot write full ld_fifo");
@ -128,7 +128,6 @@ module lsu_arbiter (
assert property (@(posedge clk_i) disable iff (~rst_ni) ld_empty |-> !ld_ren) else $fatal ("cannot read empty ld_fifo");
assert property (@(posedge clk_i) disable iff (~rst_ni) st_empty |-> !st_ren) else $fatal ("cannot read empty st_fifo");
`endif
`endif
//pragma translate_on
endmodule

20
src/mult.sv
View file

@ -409,11 +409,11 @@ module serial_divider #(
// ------------
// Assertions
// ------------
`ifndef SYNTHESIS
//pragma translate_off
initial begin : p_assertions
assert (C_LOG_WIDTH == $clog2(C_WIDTH+1)) else $error("C_LOG_WIDTH must be $clog2(C_WIDTH+1)");
end
`endif
//pragma translate_on
endmodule
@ -473,21 +473,21 @@ module mul (
end
end
// single stage version
assign mult_result_d = $signed({operand_a_i[63] & sign_a, operand_a_i}) *
// single stage version
assign mult_result_d = $signed({operand_a_i[63] & sign_a, operand_a_i}) *
$signed({operand_b_i[63] & sign_b, operand_b_i});
assign operator_d = operator_i;
assign operator_d = operator_i;
always_comb begin : p_selmux
unique case (operator_q)
MULH, MULHU, MULHSU: result_o = mult_result_q[127:64];
MULH, MULHU, MULHSU: result_o = mult_result_q[127:64];
MULW: result_o = sext32(mult_result_q[31:0]);
// MUL performs an XLEN-bit×XLEN-bit multiplication and places the lower XLEN bits in the destination register
default: result_o = mult_result_q[63:0];// including MUL
default: result_o = mult_result_q[63:0];// including MUL
endcase
end
end
// -----------------------
// Output pipeline register

7
src/scoreboard.sv
View file

@ -276,8 +276,9 @@ module scoreboard #(
commit_pointer_q <= commit_pointer_n;
end
end
`ifndef SYNTHESIS
`ifndef verilator
//pragma translate_off
`ifndef VERILATOR
initial begin
assert (NR_ENTRIES == 2**BITS_ENTRIES) else $fatal("Scoreboard size needs to be a power of two.");
end
@ -310,5 +311,5 @@ module scoreboard #(
end
end
`endif
`endif
//pragma translate_on
endmodule

4
src/tlb.sv
View file

@ -217,7 +217,7 @@ module tlb #(
// Sanity checks
//--------------
`ifndef SYNTHESIS
//pragma translate_off
`ifndef VERILATOR
initial begin : p_assertions
@ -242,6 +242,6 @@ module tlb #(
else begin $error("More then one TLB entry selected for next replace!"); $stop(); end
`endif
`endif
//pragma translate_on
endmodule

8
src/util/instruction_tracer.svh
View file

@ -47,10 +47,10 @@ class instruction_tracer;
endfunction : new
function void create_file(logic [5:0] cluster_id, logic [3:0] core_id);
function void create_file(logic [63:0] hart_id);
string fn, fn_commit_log;
$sformat(fn, "trace_core_%h_%h.log", cluster_id, core_id);
$sformat(fn_commit_log, "trace_core_%h_%h_commit.log", cluster_id, core_id);
$sformat(fn, "trace_hart_%04h.log", hart_id);
$sformat(fn_commit_log, "trace_hart_%04h_commit.log", hart_id);
$display("[TRACER] Output filename is: %s", fn);
this.f = $fopen(fn,"w");
@ -61,7 +61,7 @@ class instruction_tracer;
logic [31:0] decode_instruction, issue_instruction, issue_commit_instruction;
scoreboard_entry_t commit_instruction;
// initialize register 0
gp_reg_file [0] = 0;
gp_reg_file = '{default:0};
forever begin
automatic branchpredict_t bp_instruction = '0;

5
src/util/instruction_tracer_if.sv
View file

@ -53,13 +53,14 @@ interface instruction_tracer_if (
riscv::priv_lvl_t priv_lvl;
logic debug_mode;
// the tracer just has a passive interface we do not drive anything with it
`ifndef SYNTHESIS
//pragma translate_off
clocking pck @(posedge clk);
input rstn, flush_unissued, flush, instruction, fetch_valid, fetch_ack, issue_ack, issue_sbe, waddr,
st_valid, st_paddr, ld_valid, ld_kill, ld_paddr, resolve_branch,
wdata, we_gpr, we_fpr, commit_instr, commit_ack, exception, priv_lvl, debug_mode;
endclocking
`endif
//pragma translate_on
endinterface
`endif

5
src/util/instruction_tracer_pkg.sv
View file

@ -15,12 +15,13 @@
package instruction_tracer_pkg;
import ariane_pkg::*;
`ifndef SYNTHESIS
//pragma translate_off
import uvm_pkg::*;
`include "uvm_macros.svh"
`include "instruction_tracer_defines.svh"
`include "instruction_trace_item.svh"
`include "exception_trace_item.svh"
`include "instruction_tracer.svh"
`endif
//pragma translate_on
endpackage

3
tb/ariane_testharness.sv
View file

@ -319,8 +319,7 @@ module ariane_testharness #(
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.boot_addr_i ( 64'h10000 ), // start fetching from ROM
.core_id_i ( '0 ),
.cluster_id_i ( '0 ),
.hart_id_i ( '0 ),
.irq_i ( '0 ), // we do not specify other interrupts in this TB
.ipi_i ( ipi ),
.time_irq_i ( timer_irq ),