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[DOC] Adding legal values to MIP, MIE, SIP and SIE registers (#1326)
Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
This commit is contained in:
Mohamed Aziz Frikha
GitHub
parent
dd65886ac0
commit
853fb4bee5
4 changed files with 538 additions and 48 deletions
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@ -62,12 +62,15 @@ The ``sstatus`` register is a subset of the ``mstatus`` register.
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The ``sie`` is the register containing supervisor interrupt enable bits.
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| BIT | NAME | displayName | RIGHT | Description |
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| --- | ----------- | ------------ | ------ | -------------------------------------------------------------------- |
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| 14:10 | Reserved_10 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.|
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| 9 | SEIE | Supervisor-level external interrupt enable | read-write,WARL | SEIE is the interrupt\-enable bit for supervisor\-level external interrupts\.|
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| 8 | UEIE | | read-write,WARL | User\-level external interrupts are disabled when the UEIE bit in the sie register is clear\.|
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| 8 | UEIE | | read-write,WARL | User\-level external interrupts are disabled when the UEIE bit in the sie register is clear\.``Legal Values:``0\.|
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| 7:6 | Reserved_6 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.|
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| 5 | STIE | Supervisor-level timer interrupt enable | read-write,WARL | STIE is the interrupt\-enable bit for supervisor\-level timer interrupts\.|
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| 4 | UTIE | | read-write,WARL | User\-level timer interrupts are disabled when the UTIE bit in the sie register is clear\.|
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| 4 | UTIE | | read-write,WARL | User\-level timer interrupts are disabled when the UTIE bit in the sie register is clear\.``Legal Values:``0\.|
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| 3:2 | Reserved_2 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.|
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| 1 | SSIE | Supervisor-level software interrupt enable | read-write,WARL | SSIE is the interrupt\-enable bit for supervisor\-level software interrupts\.|
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| 0 | USIE | | read-write,WARL | User\-level software interrupts are disabled when the USIE bit in the sie register is clear|
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| 0 | USIE | | read-write,WARL | User\-level software interrupts are disabled when the USIE bit in the sie register is clear\.``Legal Values:``0\.|
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## Supervisor Trap Vector Base Address Register
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### *AddressOffset*: 'h105
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@ -160,12 +163,15 @@ When a trap is taken into S-mode, ``stval`` is written with exception-specific i
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The ``sip`` register contains information on pending interrupts.
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| BIT | NAME | displayName | RIGHT | Description |
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| --- | ----------- | ------------ | ------ | -------------------------------------------------------------------- |
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| 14:10 | Reserved_10 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.|
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| 9 | SEIP | Supervisor-level external interrupt pending | read-only,WARL | SEIP is the interrupt\-pending bit for supervisor\-level external interrupts\.|
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| 8 | UEIP | | read-write,WARL | UEIP may be written by S\-mode software to indicate to U\-mode that an external interrupt is pending\.|
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| 8 | UEIP | | read-write,WARL | UEIP may be written by S\-mode software to indicate to U\-mode that an external interrupt is pending\.``Legal Values:``0\.|
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| 7:6 | Reserved_6 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.|
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| 5 | STIP | Supervisor-level timer interrupt pending | read-only,WARL | SEIP is the interrupt\-pending bit for supervisor\-level timer interrupts\.|
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| 4 | UTIP | | read-write,WARL | A user\-level timer interrupt is pending if the UTIP bit in the sip register is set|
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| 4 | UTIP | | read-write,WARL | A user\-level timer interrupt is pending if the UTIP bit in the sip register is set\.``Legal Values:``0\.|
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| 3:2 | Reserved_2 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.|
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| 1 | SSIP | Supervisor-level software interrupt pending | read-only,WARL | SSIP is the interrupt\-pending bit for supervisor\-level software interrupts\.|
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| 0 | USIP | | read-write,WARL | A user\-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt\-pending \(USIP\) bit|
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| 0 | USIP | | read-write,WARL | A user\-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt\-pending \(USIP\) bit\.``Legal Values:``0\.|
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## Supervisor Address Translation and Protection Register
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### *AddressOffset*: 'h180
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@ -241,15 +247,19 @@ Provides individual read/write bits to indicate that certain interrupts should b
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This register contains machine interrupt enable bits.
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| BIT | NAME | displayName | RIGHT | Description |
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| --- | ----------- | ------------ | ------ | -------------------------------------------------------------------- |
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| 15:12 | Reserved_12 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.|
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| 11 | MEIE | M-mode external interrupt enable | read-write,WARL | Enables machine mode external interrupts\.|
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| 10 | Reserved_10 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.|
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| 9 | SEIE | S-mode external interrupt enable | read-write,WARL | Enables supervisor mode external interrupts\.|
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| 8 | UEIE | | read-write,WARL | enables U\-mode external interrupts|
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| 8 | UEIE | | read-write,WARL | enables U\-mode external interrupts\.``Legal Values:``0\.|
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| 7 | MTIE | M-mode timer interrupt enable | read-write,WARL | Enables machine mode timer interrupts\.|
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| 6 | Reserved_6 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.|
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| 5 | STIE | S-mode timer interrupt enable | read-write,WARL | Enables supervisor mode timer interrupts\.|
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| 4 | UTIE | | read-write,WARL | timer interrupt\-enable bit for U\-mode|
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| 4 | UTIE | | read-write,WARL | timer interrupt\-enable bit for U\-mode\.``Legal Values:``0\.|
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| 3 | MSIE | M-mode software interrupt enable | read-write | Enables machine mode software interrupts\.|
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| 2 | Reserved_2 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.|
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| 1 | SSIE | S-mode software interrupt enable | read-write,WARL | Enables supervisor mode software interrupts\.|
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| 0 | USIE | | read-write,WARL | enable U\-mode software interrrupts|
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| 0 | USIE | | read-write,WARL | enable U\-mode software interrrupts\.``Legal Values:``0\.|
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## Machine Trap Vector Register
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### *AddressOffset*: 'h305
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@ -350,15 +360,19 @@ When a trap is taken into M-mode, mtval is either set to zero or written with ex
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This register contains machine interrupt pending bits.
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| BIT | NAME | displayName | RIGHT | Description |
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| --- | ----------- | ------------ | ------ | -------------------------------------------------------------------- |
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| 15:12 | Reserved_12 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.|
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| 11 | MEIP | M-mode external interrupt pending | read-only | The interrupt\-pending bit for machine\-level external interrupts\.|
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| 10 | Reserved_10 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.|
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| 9 | SEIP | S-mode external interrupt pending | read-write | The interrupt\-pending bit for supervisor\-level external interrupts\.|
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| 8 | UEIP | | read-write | enables external interrupts|
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| 8 | UEIP | | read-write | enables external interrupts\.``Legal Values:``0\.|
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| 7 | MTIP | M-mode timer interrupt pending | read-only | The interrupt\-pending bit for machine\-level timer interrupts\.|
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| 6 | Reserved_6 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.|
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| 5 | STIP | S-mode timer interrupt pending | read-write | The interrupt\-pending bit for supervisor\-level timer interrupts\.|
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| 4 | UTIP | | read-write | Correspond to timer interrupt\-pending bits for user interrupt|
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| 4 | UTIP | | read-write | Correspond to timer interrupt\-pending bits for user interrupt\.``Legal Values:``0\.|
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| 3 | MSIP | M-mode software interrupt pending | read-only | The interrupt\-pending bit for machine\-level software interrupts\.|
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| 2 | Reserved_2 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.|
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| 1 | SSIP | S-mode software interrupt pending | read-write | The interrupt\-pending bit for supervisor\-level software interrupts\.|
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| 0 | USIP | | read-write | A hart to directly write its own USIP bits when running in the appropriate mode|
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| 0 | USIP | | read-write | A hart to directly write its own USIP bits when running in the appropriate mode\.``Legal Values:``0\.|
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## Physical Memory Protection Config 0 Register
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### *AddressOffset*: 'h3A0
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@ -206,6 +206,11 @@ The ``sie`` is the register containing supervisor interrupt enable bits.
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- **displayName**
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- **RIGHT**
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- **Description**
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* - 14:10
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- Reserved_10
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- Reserved
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- read-write,WARL
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- Reserved\.``Legal Values:``0\.
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* - 9
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- SEIE
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- Supervisor-level external interrupt enable
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@ -215,7 +220,12 @@ The ``sie`` is the register containing supervisor interrupt enable bits.
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- UEIE
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-
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- read-write,WARL
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- User\-level external interrupts are disabled when the UEIE bit in the sie register is clear\.
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- User\-level external interrupts are disabled when the UEIE bit in the sie register is clear\.``Legal Values:``0\.
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* - 7:6
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- Reserved_6
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- Reserved
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- read-write,WARL
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- Reserved\.``Legal Values:``0\.
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* - 5
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- STIE
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- Supervisor-level timer interrupt enable
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@ -225,7 +235,12 @@ The ``sie`` is the register containing supervisor interrupt enable bits.
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- UTIE
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-
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- read-write,WARL
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- User\-level timer interrupts are disabled when the UTIE bit in the sie register is clear\.
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- User\-level timer interrupts are disabled when the UTIE bit in the sie register is clear\.``Legal Values:``0\.
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* - 3:2
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- Reserved_2
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- Reserved
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- read-write,WARL
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- Reserved\.``Legal Values:``0\.
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* - 1
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- SSIE
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- Supervisor-level software interrupt enable
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@ -235,7 +250,7 @@ The ``sie`` is the register containing supervisor interrupt enable bits.
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- USIE
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-
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- read-write,WARL
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- User\-level software interrupts are disabled when the USIE bit in the sie register is clear
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- User\-level software interrupts are disabled when the USIE bit in the sie register is clear\.``Legal Values:``0\.
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Supervisor Trap Vector Base Address Register
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--------------------------
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@ -511,6 +526,11 @@ The ``sip`` register contains information on pending interrupts.
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- **displayName**
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- **RIGHT**
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- **Description**
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* - 14:10
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- Reserved_10
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- Reserved
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- read-write,WARL
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- Reserved\.``Legal Values:``0\.
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* - 9
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- SEIP
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- Supervisor-level external interrupt pending
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@ -520,7 +540,12 @@ The ``sip`` register contains information on pending interrupts.
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- UEIP
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-
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- read-write,WARL
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- UEIP may be written by S\-mode software to indicate to U\-mode that an external interrupt is pending\.
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- UEIP may be written by S\-mode software to indicate to U\-mode that an external interrupt is pending\.``Legal Values:``0\.
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* - 7:6
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- Reserved_6
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- Reserved
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- read-write,WARL
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- Reserved\.``Legal Values:``0\.
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* - 5
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- STIP
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- Supervisor-level timer interrupt pending
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@ -530,7 +555,12 @@ The ``sip`` register contains information on pending interrupts.
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- UTIP
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-
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- read-write,WARL
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- A user\-level timer interrupt is pending if the UTIP bit in the sip register is set
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- A user\-level timer interrupt is pending if the UTIP bit in the sip register is set\.``Legal Values:``0\.
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* - 3:2
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- Reserved_2
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- Reserved
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- read-write,WARL
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- Reserved\.``Legal Values:``0\.
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* - 1
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- SSIP
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- Supervisor-level software interrupt pending
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@ -540,7 +570,7 @@ The ``sip`` register contains information on pending interrupts.
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- USIP
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-
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- read-write,WARL
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- A user\-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt\-pending \(USIP\) bit
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- A user\-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt\-pending \(USIP\) bit\.``Legal Values:``0\.
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Supervisor Address Translation and Protection Register
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--------------------------
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@ -794,11 +824,21 @@ This register contains machine interrupt enable bits.
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- **displayName**
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- **RIGHT**
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- **Description**
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* - 15:12
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- Reserved_12
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- Reserved
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- read-write,WARL
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- Reserved\.``Legal Values:``0\.
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* - 11
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- MEIE
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- M-mode external interrupt enable
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- read-write,WARL
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- Enables machine mode external interrupts\.
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* - 10
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- Reserved_10
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- Reserved
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- read-write,WARL
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- Reserved\.``Legal Values:``0\.
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* - 9
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- SEIE
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- S-mode external interrupt enable
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@ -808,12 +848,17 @@ This register contains machine interrupt enable bits.
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- UEIE
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-
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- read-write,WARL
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- enables U\-mode external interrupts
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- enables U\-mode external interrupts\.``Legal Values:``0\.
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* - 7
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- MTIE
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- M-mode timer interrupt enable
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- read-write,WARL
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- Enables machine mode timer interrupts\.
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* - 6
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- Reserved_6
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- Reserved
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- read-write,WARL
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- Reserved\.``Legal Values:``0\.
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* - 5
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- STIE
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- S-mode timer interrupt enable
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@ -823,12 +868,17 @@ This register contains machine interrupt enable bits.
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- UTIE
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-
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- read-write,WARL
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- timer interrupt\-enable bit for U\-mode
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- timer interrupt\-enable bit for U\-mode\.``Legal Values:``0\.
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* - 3
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- MSIE
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- M-mode software interrupt enable
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- read-write
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- Enables machine mode software interrupts\.
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* - 2
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- Reserved_2
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- Reserved
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- read-write,WARL
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- Reserved\.``Legal Values:``0\.
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* - 1
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- SSIE
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- S-mode software interrupt enable
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@ -838,7 +888,7 @@ This register contains machine interrupt enable bits.
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- USIE
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-
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- read-write,WARL
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- enable U\-mode software interrrupts
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- enable U\-mode software interrrupts\.``Legal Values:``0\.
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Machine Trap Vector Register
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--------------------------
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@ -1137,11 +1187,21 @@ This register contains machine interrupt pending bits.
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- **displayName**
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- **RIGHT**
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- **Description**
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* - 15:12
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- Reserved_12
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- Reserved
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- read-write,WARL
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- Reserved\.``Legal Values:``0\.
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* - 11
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- MEIP
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- M-mode external interrupt pending
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- read-only
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- The interrupt\-pending bit for machine\-level external interrupts\.
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* - 10
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- Reserved_10
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- Reserved
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- read-write,WARL
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- Reserved\.``Legal Values:``0\.
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* - 9
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- SEIP
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- S-mode external interrupt pending
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@ -1151,12 +1211,17 @@ This register contains machine interrupt pending bits.
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- UEIP
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-
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- read-write
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- enables external interrupts
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- enables external interrupts\.``Legal Values:``0\.
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* - 7
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- MTIP
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- M-mode timer interrupt pending
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- read-only
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- The interrupt\-pending bit for machine\-level timer interrupts\.
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* - 6
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- Reserved_6
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- Reserved
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- read-write,WARL
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- Reserved\.``Legal Values:``0\.
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* - 5
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- STIP
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- S-mode timer interrupt pending
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@ -1166,12 +1231,17 @@ This register contains machine interrupt pending bits.
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- UTIP
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-
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- read-write
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- Correspond to timer interrupt\-pending bits for user interrupt
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- Correspond to timer interrupt\-pending bits for user interrupt\.``Legal Values:``0\.
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* - 3
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- MSIP
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- M-mode software interrupt pending
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- read-only
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- The interrupt\-pending bit for machine\-level software interrupts\.
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* - 2
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- Reserved_2
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- Reserved
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- read-write,WARL
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- Reserved\.``Legal Values:``0\.
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* - 1
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- SSIP
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- S-mode software interrupt pending
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@ -1181,7 +1251,7 @@ This register contains machine interrupt pending bits.
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- USIP
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-
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- read-write
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- A hart to directly write its own USIP bits when running in the appropriate mode
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- A hart to directly write its own USIP bits when running in the appropriate mode\.``Legal Values:``0\.
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Physical Memory Protection Config 0 Register
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--------------------------
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@ -531,6 +531,23 @@ an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1.</ipx
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<ipxact:addressOffset>'h104</ipxact:addressOffset>
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<ipxact:size>32</ipxact:size>
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<ipxact:access>read-write</ipxact:access>
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<ipxact:field>
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<ipxact:name>Reserved_10</ipxact:name>
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<ipxact:displayName>Reserved</ipxact:displayName>
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<ipxact:description>Reserved.``Legal Values:``0.</ipxact:description>
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<ipxact:bitOffset>10</ipxact:bitOffset>
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<ipxact:resets>
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<ipxact:reset>
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<ipxact:value>0x0</ipxact:value>
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<ipxact:mask>0x1</ipxact:mask>
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</ipxact:reset>
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</ipxact:resets>
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<ipxact:bitWidth>5</ipxact:bitWidth>
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<ipxact:access>read-write</ipxact:access>
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<ipxact:vendorExtensions>
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<RISCV_behavior>WARL</RISCV_behavior>
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</ipxact:vendorExtensions>
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</ipxact:field>
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<ipxact:field>
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<ipxact:name>SEIE</ipxact:name>
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<ipxact:displayName>Supervisor-level External Interrupt Enable</ipxact:displayName>
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@ -550,7 +567,7 @@ an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1.</ipx
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</ipxact:field>
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<ipxact:field>
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<ipxact:name>UEIE</ipxact:name>
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<ipxact:description>User-level external interrupts are disabled when the UEIE bit in the sie register is clear.</ipxact:description>
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<ipxact:description>User-level external interrupts are disabled when the UEIE bit in the sie register is clear.``Legal Values:``0.</ipxact:description>
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<ipxact:bitOffset>8</ipxact:bitOffset>
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<ipxact:resets>
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<ipxact:reset>
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@ -564,6 +581,23 @@ an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1.</ipx
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<RISCV_behavior>WARL</RISCV_behavior>
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</ipxact:vendorExtensions>
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</ipxact:field>
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<ipxact:field>
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<ipxact:name>Reserved_6</ipxact:name>
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<ipxact:displayName>Reserved</ipxact:displayName>
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<ipxact:description>Reserved.``Legal Values:``0.</ipxact:description>
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<ipxact:bitOffset>6</ipxact:bitOffset>
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<ipxact:resets>
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<ipxact:reset>
|
||||
<ipxact:value>0x0</ipxact:value>
|
||||
<ipxact:mask>0x1</ipxact:mask>
|
||||
</ipxact:reset>
|
||||
</ipxact:resets>
|
||||
<ipxact:bitWidth>2</ipxact:bitWidth>
|
||||
<ipxact:access>read-write</ipxact:access>
|
||||
<ipxact:vendorExtensions>
|
||||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>STIE</ipxact:name>
|
||||
<ipxact:displayName>Supervisor-level Timer Interrupt Enable</ipxact:displayName>
|
||||
|
|
@ -583,7 +617,7 @@ an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1.</ipx
|
|||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>UTIE</ipxact:name>
|
||||
<ipxact:description>User-level timer interrupts are disabled when the UTIE bit in the sie register is clear.</ipxact:description>
|
||||
<ipxact:description>User-level timer interrupts are disabled when the UTIE bit in the sie register is clear.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>4</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
|
|
@ -597,6 +631,23 @@ an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1.</ipx
|
|||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>Reserved_2</ipxact:name>
|
||||
<ipxact:displayName>Reserved</ipxact:displayName>
|
||||
<ipxact:description>Reserved.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>2</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
<ipxact:value>0x0</ipxact:value>
|
||||
<ipxact:mask>0x1</ipxact:mask>
|
||||
</ipxact:reset>
|
||||
</ipxact:resets>
|
||||
<ipxact:bitWidth>2</ipxact:bitWidth>
|
||||
<ipxact:access>read-write</ipxact:access>
|
||||
<ipxact:vendorExtensions>
|
||||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>SSIE</ipxact:name>
|
||||
<ipxact:displayName>Supervisor-level Software Interrupt Enable</ipxact:displayName>
|
||||
|
|
@ -616,7 +667,7 @@ an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1.</ipx
|
|||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>USIE</ipxact:name>
|
||||
<ipxact:description>User-level software interrupts are disabled when the USIE bit in the sie register is clear</ipxact:description>
|
||||
<ipxact:description>User-level software interrupts are disabled when the USIE bit in the sie register is clear.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>0</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
|
|
@ -940,6 +991,23 @@ The value loaded into ``stval`` on an illegal-instruction exception is right-jus
|
|||
<ipxact:size>32</ipxact:size>
|
||||
<ipxact:volatile>true</ipxact:volatile>
|
||||
<ipxact:access>read-write</ipxact:access>
|
||||
<ipxact:field>
|
||||
<ipxact:name>Reserved_10</ipxact:name>
|
||||
<ipxact:displayName>Reserved</ipxact:displayName>
|
||||
<ipxact:description>Reserved.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>10</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
<ipxact:value>0x0</ipxact:value>
|
||||
<ipxact:mask>0x1</ipxact:mask>
|
||||
</ipxact:reset>
|
||||
</ipxact:resets>
|
||||
<ipxact:bitWidth>5</ipxact:bitWidth>
|
||||
<ipxact:access>read-write</ipxact:access>
|
||||
<ipxact:vendorExtensions>
|
||||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>SEIP</ipxact:name>
|
||||
<ipxact:displayName>Supervisor-level External Interrupt Pending</ipxact:displayName>
|
||||
|
|
@ -960,7 +1028,7 @@ The value loaded into ``stval`` on an illegal-instruction exception is right-jus
|
|||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>UEIP</ipxact:name>
|
||||
<ipxact:description>UEIP may be written by S-mode software to indicate to U-mode that an external interrupt is pending.</ipxact:description>
|
||||
<ipxact:description>UEIP may be written by S-mode software to indicate to U-mode that an external interrupt is pending.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>8</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
|
|
@ -974,6 +1042,23 @@ The value loaded into ``stval`` on an illegal-instruction exception is right-jus
|
|||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>Reserved_6</ipxact:name>
|
||||
<ipxact:displayName>Reserved</ipxact:displayName>
|
||||
<ipxact:description>Reserved.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>6</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
<ipxact:value>0x0</ipxact:value>
|
||||
<ipxact:mask>0x1</ipxact:mask>
|
||||
</ipxact:reset>
|
||||
</ipxact:resets>
|
||||
<ipxact:bitWidth>2</ipxact:bitWidth>
|
||||
<ipxact:access>read-write</ipxact:access>
|
||||
<ipxact:vendorExtensions>
|
||||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>STIP</ipxact:name>
|
||||
<ipxact:displayName>Supervisor-level Timer Interrupt Pending</ipxact:displayName>
|
||||
|
|
@ -994,7 +1079,7 @@ The value loaded into ``stval`` on an illegal-instruction exception is right-jus
|
|||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>UTIP</ipxact:name>
|
||||
<ipxact:description>A user-level timer interrupt is pending if the UTIP bit in the sip register is set</ipxact:description>
|
||||
<ipxact:description>A user-level timer interrupt is pending if the UTIP bit in the sip register is set.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>4</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
|
|
@ -1008,6 +1093,23 @@ The value loaded into ``stval`` on an illegal-instruction exception is right-jus
|
|||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>Reserved_2</ipxact:name>
|
||||
<ipxact:displayName>Reserved</ipxact:displayName>
|
||||
<ipxact:description>Reserved.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>2</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
<ipxact:value>0x0</ipxact:value>
|
||||
<ipxact:mask>0x1</ipxact:mask>
|
||||
</ipxact:reset>
|
||||
</ipxact:resets>
|
||||
<ipxact:bitWidth>2</ipxact:bitWidth>
|
||||
<ipxact:access>read-write</ipxact:access>
|
||||
<ipxact:vendorExtensions>
|
||||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>SSIP</ipxact:name>
|
||||
<ipxact:displayName>Supervisor-level Software Interrupt Pending</ipxact:displayName>
|
||||
|
|
@ -1028,7 +1130,7 @@ The value loaded into ``stval`` on an illegal-instruction exception is right-jus
|
|||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>USIP</ipxact:name>
|
||||
<ipxact:description>A user-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt-pending (USIP) bit</ipxact:description>
|
||||
<ipxact:description>A user-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt-pending (USIP) bit.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>0</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
|
|
@ -1763,6 +1865,23 @@ with the index of the bit position equal to the value returned in the ``mcause``
|
|||
<ipxact:addressOffset>'h304</ipxact:addressOffset>
|
||||
<ipxact:size>32</ipxact:size>
|
||||
<ipxact:access>read-write</ipxact:access>
|
||||
<ipxact:field>
|
||||
<ipxact:name>Reserved_12</ipxact:name>
|
||||
<ipxact:displayName>Reserved</ipxact:displayName>
|
||||
<ipxact:description>Reserved.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>12</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
<ipxact:value>0x0</ipxact:value>
|
||||
<ipxact:mask>0x1</ipxact:mask>
|
||||
</ipxact:reset>
|
||||
</ipxact:resets>
|
||||
<ipxact:bitWidth>4</ipxact:bitWidth>
|
||||
<ipxact:access>read-write</ipxact:access>
|
||||
<ipxact:vendorExtensions>
|
||||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>MEIE</ipxact:name>
|
||||
<ipxact:displayName>M-mode External Interrupt Enable</ipxact:displayName>
|
||||
|
|
@ -1780,6 +1899,23 @@ with the index of the bit position equal to the value returned in the ``mcause``
|
|||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>Reserved_10</ipxact:name>
|
||||
<ipxact:displayName>Reserved</ipxact:displayName>
|
||||
<ipxact:description>Reserved.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>10</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
<ipxact:value>0x0</ipxact:value>
|
||||
<ipxact:mask>0x1</ipxact:mask>
|
||||
</ipxact:reset>
|
||||
</ipxact:resets>
|
||||
<ipxact:bitWidth>1</ipxact:bitWidth>
|
||||
<ipxact:access>read-write</ipxact:access>
|
||||
<ipxact:vendorExtensions>
|
||||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>SEIE</ipxact:name>
|
||||
<ipxact:displayName>S-mode External Interrupt Enable</ipxact:displayName>
|
||||
|
|
@ -1799,7 +1935,7 @@ with the index of the bit position equal to the value returned in the ``mcause``
|
|||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>UEIE</ipxact:name>
|
||||
<ipxact:description>enables U-mode external interrupts</ipxact:description>
|
||||
<ipxact:description>enables U-mode external interrupts.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>8</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
|
|
@ -1830,6 +1966,23 @@ with the index of the bit position equal to the value returned in the ``mcause``
|
|||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>Reserved_6</ipxact:name>
|
||||
<ipxact:displayName>Reserved</ipxact:displayName>
|
||||
<ipxact:description>Reserved.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>6</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
<ipxact:value>0x0</ipxact:value>
|
||||
<ipxact:mask>0x1</ipxact:mask>
|
||||
</ipxact:reset>
|
||||
</ipxact:resets>
|
||||
<ipxact:bitWidth>1</ipxact:bitWidth>
|
||||
<ipxact:access>read-write</ipxact:access>
|
||||
<ipxact:vendorExtensions>
|
||||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>STIE</ipxact:name>
|
||||
<ipxact:displayName>S-mode Timer Interrupt Enable</ipxact:displayName>
|
||||
|
|
@ -1849,7 +2002,7 @@ with the index of the bit position equal to the value returned in the ``mcause``
|
|||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>UTIE</ipxact:name>
|
||||
<ipxact:description>timer interrupt-enable bit for U-mode</ipxact:description>
|
||||
<ipxact:description>timer interrupt-enable bit for U-mode.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>4</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
|
|
@ -1877,6 +2030,23 @@ with the index of the bit position equal to the value returned in the ``mcause``
|
|||
<ipxact:bitWidth>1</ipxact:bitWidth>
|
||||
<ipxact:access>read-write</ipxact:access>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>Reserved_2</ipxact:name>
|
||||
<ipxact:displayName>Reserved</ipxact:displayName>
|
||||
<ipxact:description>Reserved.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>2</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
<ipxact:value>0x0</ipxact:value>
|
||||
<ipxact:mask>0x1</ipxact:mask>
|
||||
</ipxact:reset>
|
||||
</ipxact:resets>
|
||||
<ipxact:bitWidth>1</ipxact:bitWidth>
|
||||
<ipxact:access>read-write</ipxact:access>
|
||||
<ipxact:vendorExtensions>
|
||||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>SSIE</ipxact:name>
|
||||
<ipxact:displayName>S-mode Software Interrupt Enable</ipxact:displayName>
|
||||
|
|
@ -1896,7 +2066,7 @@ with the index of the bit position equal to the value returned in the ``mcause``
|
|||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>USIE</ipxact:name>
|
||||
<ipxact:description>enable U-mode software interrrupts</ipxact:description>
|
||||
<ipxact:description>enable U-mode software interrrupts.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>0</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
|
|
@ -2243,6 +2413,23 @@ If ``mtval`` is written with a nonzero value when an instruction access-fault or
|
|||
<ipxact:size>32</ipxact:size>
|
||||
<ipxact:volatile>true</ipxact:volatile>
|
||||
<ipxact:access>read-write</ipxact:access>
|
||||
<ipxact:field>
|
||||
<ipxact:name>Reserved_12</ipxact:name>
|
||||
<ipxact:displayName>Reserved</ipxact:displayName>
|
||||
<ipxact:description>Reserved.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>12</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
<ipxact:value>0x0</ipxact:value>
|
||||
<ipxact:mask>0x1</ipxact:mask>
|
||||
</ipxact:reset>
|
||||
</ipxact:resets>
|
||||
<ipxact:bitWidth>4</ipxact:bitWidth>
|
||||
<ipxact:access>read-write</ipxact:access>
|
||||
<ipxact:vendorExtensions>
|
||||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>MEIP</ipxact:name>
|
||||
<ipxact:displayName>M-mode External Interrupt Pending</ipxact:displayName>
|
||||
|
|
@ -2258,6 +2445,23 @@ If ``mtval`` is written with a nonzero value when an instruction access-fault or
|
|||
<ipxact:volatile>true</ipxact:volatile>
|
||||
<ipxact:access>read-only</ipxact:access>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>Reserved_10</ipxact:name>
|
||||
<ipxact:displayName>Reserved</ipxact:displayName>
|
||||
<ipxact:description>Reserved.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>10</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
<ipxact:value>0x0</ipxact:value>
|
||||
<ipxact:mask>0x1</ipxact:mask>
|
||||
</ipxact:reset>
|
||||
</ipxact:resets>
|
||||
<ipxact:bitWidth>1</ipxact:bitWidth>
|
||||
<ipxact:access>read-write</ipxact:access>
|
||||
<ipxact:vendorExtensions>
|
||||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>SEIP</ipxact:name>
|
||||
<ipxact:displayName>S-mode External Interrupt Pending</ipxact:displayName>
|
||||
|
|
@ -2274,7 +2478,7 @@ If ``mtval`` is written with a nonzero value when an instruction access-fault or
|
|||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>UEIP</ipxact:name>
|
||||
<ipxact:description>enables external interrupts</ipxact:description>
|
||||
<ipxact:description>enables external interrupts.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>8</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
|
|
@ -2300,6 +2504,23 @@ If ``mtval`` is written with a nonzero value when an instruction access-fault or
|
|||
<ipxact:volatile>true</ipxact:volatile>
|
||||
<ipxact:access>read-only</ipxact:access>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>Reserved_6</ipxact:name>
|
||||
<ipxact:displayName>Reserved</ipxact:displayName>
|
||||
<ipxact:description>Reserved.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>6</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
<ipxact:value>0x0</ipxact:value>
|
||||
<ipxact:mask>0x1</ipxact:mask>
|
||||
</ipxact:reset>
|
||||
</ipxact:resets>
|
||||
<ipxact:bitWidth>1</ipxact:bitWidth>
|
||||
<ipxact:access>read-write</ipxact:access>
|
||||
<ipxact:vendorExtensions>
|
||||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>STIP</ipxact:name>
|
||||
<ipxact:displayName>S-mode Timer Interrupt Pending</ipxact:displayName>
|
||||
|
|
@ -2316,7 +2537,7 @@ If ``mtval`` is written with a nonzero value when an instruction access-fault or
|
|||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>UTIP</ipxact:name>
|
||||
<ipxact:description>Correspond to timer interrupt-pending bits for user interrupt</ipxact:description>
|
||||
<ipxact:description>Correspond to timer interrupt-pending bits for user interrupt.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>4</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
|
|
@ -2342,6 +2563,23 @@ If ``mtval`` is written with a nonzero value when an instruction access-fault or
|
|||
<ipxact:volatile>true</ipxact:volatile>
|
||||
<ipxact:access>read-only</ipxact:access>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>Reserved_2</ipxact:name>
|
||||
<ipxact:displayName>Reserved</ipxact:displayName>
|
||||
<ipxact:description>Reserved.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>2</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
<ipxact:value>0x0</ipxact:value>
|
||||
<ipxact:mask>0x1</ipxact:mask>
|
||||
</ipxact:reset>
|
||||
</ipxact:resets>
|
||||
<ipxact:bitWidth>1</ipxact:bitWidth>
|
||||
<ipxact:access>read-write</ipxact:access>
|
||||
<ipxact:vendorExtensions>
|
||||
<RISCV_behavior>WARL</RISCV_behavior>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>SSIP</ipxact:name>
|
||||
<ipxact:displayName>S-mode Software Interrupt Pending</ipxact:displayName>
|
||||
|
|
@ -2358,7 +2596,7 @@ If ``mtval`` is written with a nonzero value when an instruction access-fault or
|
|||
</ipxact:field>
|
||||
<ipxact:field>
|
||||
<ipxact:name>USIP</ipxact:name>
|
||||
<ipxact:description>A hart to directly write its own USIP bits when running in the appropriate mode</ipxact:description>
|
||||
<ipxact:description>A hart to directly write its own USIP bits when running in the appropriate mode.``Legal Values:``0.</ipxact:description>
|
||||
<ipxact:bitOffset>0</ipxact:bitOffset>
|
||||
<ipxact:resets>
|
||||
<ipxact:reset>
|
||||
|
|
|
|||
|
|
@ -399,6 +399,18 @@ component:
|
|||
size: '32'
|
||||
access: read-write
|
||||
field:
|
||||
- name: Reserved_10
|
||||
displayName: Reserved
|
||||
description: Reserved.``Legal Values:``0.
|
||||
bitOffset: '10'
|
||||
resets:
|
||||
reset:
|
||||
value: '0x0'
|
||||
mask: '0x1'
|
||||
bitWidth: '5'
|
||||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: SEIE
|
||||
displayName: Supervisor-level External Interrupt Enable
|
||||
description: SEIE is the interrupt-enable bit for supervisor-level external interrupts.
|
||||
|
|
@ -412,7 +424,7 @@ component:
|
|||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: UEIE
|
||||
description: User-level external interrupts are disabled when the UEIE bit in the sie register is clear.
|
||||
description: User-level external interrupts are disabled when the UEIE bit in the sie register is clear.``Legal Values:``0.
|
||||
bitOffset: '8'
|
||||
resets:
|
||||
reset:
|
||||
|
|
@ -422,6 +434,18 @@ component:
|
|||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: Reserved_6
|
||||
displayName: Reserved
|
||||
description: Reserved.``Legal Values:``0.
|
||||
bitOffset: '6'
|
||||
resets:
|
||||
reset:
|
||||
value: '0x0'
|
||||
mask: '0x1'
|
||||
bitWidth: '2'
|
||||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: STIE
|
||||
displayName: Supervisor-level Timer Interrupt Enable
|
||||
description: STIE is the interrupt-enable bit for supervisor-level timer interrupts.
|
||||
|
|
@ -435,7 +459,7 @@ component:
|
|||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: UTIE
|
||||
description: User-level timer interrupts are disabled when the UTIE bit in the sie register is clear.
|
||||
description: User-level timer interrupts are disabled when the UTIE bit in the sie register is clear.``Legal Values:``0.
|
||||
bitOffset: '4'
|
||||
resets:
|
||||
reset:
|
||||
|
|
@ -445,6 +469,18 @@ component:
|
|||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: Reserved_2
|
||||
displayName: Reserved
|
||||
description: Reserved.``Legal Values:``0.
|
||||
bitOffset: '2'
|
||||
resets:
|
||||
reset:
|
||||
value: '0x0'
|
||||
mask: '0x1'
|
||||
bitWidth: '2'
|
||||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: SSIE
|
||||
displayName: Supervisor-level Software Interrupt Enable
|
||||
description: SSIE is the interrupt-enable bit for supervisor-level software interrupts.
|
||||
|
|
@ -458,7 +494,7 @@ component:
|
|||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: USIE
|
||||
description: User-level software interrupts are disabled when the USIE bit in the sie register is clear
|
||||
description: User-level software interrupts are disabled when the USIE bit in the sie register is clear.``Legal Values:``0.
|
||||
bitOffset: '0'
|
||||
resets:
|
||||
reset:
|
||||
|
|
@ -667,6 +703,18 @@ component:
|
|||
volatile: 'true'
|
||||
access: read-write
|
||||
field:
|
||||
- name: Reserved_10
|
||||
displayName: Reserved
|
||||
description: Reserved.``Legal Values:``0.
|
||||
bitOffset: '10'
|
||||
resets:
|
||||
reset:
|
||||
value: '0x0'
|
||||
mask: '0x1'
|
||||
bitWidth: '5'
|
||||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: SEIP
|
||||
displayName: Supervisor-level External Interrupt Pending
|
||||
description: SEIP is the interrupt-pending bit for supervisor-level external interrupts.
|
||||
|
|
@ -681,7 +729,7 @@ component:
|
|||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: UEIP
|
||||
description: UEIP may be written by S-mode software to indicate to U-mode that an external interrupt is pending.
|
||||
description: UEIP may be written by S-mode software to indicate to U-mode that an external interrupt is pending.``Legal Values:``0.
|
||||
bitOffset: '8'
|
||||
resets:
|
||||
reset:
|
||||
|
|
@ -691,6 +739,18 @@ component:
|
|||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: Reserved_6
|
||||
displayName: Reserved
|
||||
description: Reserved.``Legal Values:``0.
|
||||
bitOffset: '6'
|
||||
resets:
|
||||
reset:
|
||||
value: '0x0'
|
||||
mask: '0x1'
|
||||
bitWidth: '2'
|
||||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: STIP
|
||||
displayName: Supervisor-level Timer Interrupt Pending
|
||||
description: SEIP is the interrupt-pending bit for supervisor-level timer interrupts.
|
||||
|
|
@ -705,7 +765,7 @@ component:
|
|||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: UTIP
|
||||
description: A user-level timer interrupt is pending if the UTIP bit in the sip register is set
|
||||
description: A user-level timer interrupt is pending if the UTIP bit in the sip register is set.``Legal Values:``0.
|
||||
bitOffset: '4'
|
||||
resets:
|
||||
reset:
|
||||
|
|
@ -715,6 +775,18 @@ component:
|
|||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: Reserved_2
|
||||
displayName: Reserved
|
||||
description: Reserved.``Legal Values:``0.
|
||||
bitOffset: '2'
|
||||
resets:
|
||||
reset:
|
||||
value: '0x0'
|
||||
mask: '0x1'
|
||||
bitWidth: '2'
|
||||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: SSIP
|
||||
displayName: Supervisor-level Software Interrupt Pending
|
||||
description: SSIP is the interrupt-pending bit for supervisor-level software interrupts.
|
||||
|
|
@ -729,7 +801,7 @@ component:
|
|||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: USIP
|
||||
description: A user-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt-pending (USIP) bit
|
||||
description: A user-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt-pending (USIP) bit.``Legal Values:``0.
|
||||
bitOffset: '0'
|
||||
resets:
|
||||
reset:
|
||||
|
|
@ -1267,6 +1339,18 @@ component:
|
|||
size: '32'
|
||||
access: read-write
|
||||
field:
|
||||
- name: Reserved_12
|
||||
displayName: Reserved
|
||||
description: Reserved.``Legal Values:``0.
|
||||
bitOffset: '12'
|
||||
resets:
|
||||
reset:
|
||||
value: '0x0'
|
||||
mask: '0x1'
|
||||
bitWidth: '4'
|
||||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: MEIE
|
||||
displayName: M-mode External Interrupt Enable
|
||||
description: Enables machine mode external interrupts.
|
||||
|
|
@ -1279,6 +1363,18 @@ component:
|
|||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: Reserved_10
|
||||
displayName: Reserved
|
||||
description: Reserved.``Legal Values:``0.
|
||||
bitOffset: '10'
|
||||
resets:
|
||||
reset:
|
||||
value: '0x0'
|
||||
mask: '0x1'
|
||||
bitWidth: '1'
|
||||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: SEIE
|
||||
displayName: S-mode External Interrupt Enable
|
||||
description: Enables supervisor mode external interrupts.
|
||||
|
|
@ -1292,7 +1388,7 @@ component:
|
|||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: UEIE
|
||||
description: enables U-mode external interrupts
|
||||
description: enables U-mode external interrupts.``Legal Values:``0.
|
||||
bitOffset: '8'
|
||||
resets:
|
||||
reset:
|
||||
|
|
@ -1314,6 +1410,18 @@ component:
|
|||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: Reserved_6
|
||||
displayName: Reserved
|
||||
description: Reserved.``Legal Values:``0.
|
||||
bitOffset: '6'
|
||||
resets:
|
||||
reset:
|
||||
value: '0x0'
|
||||
mask: '0x1'
|
||||
bitWidth: '1'
|
||||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: STIE
|
||||
displayName: S-mode Timer Interrupt Enable
|
||||
description: Enables supervisor mode timer interrupts.
|
||||
|
|
@ -1327,7 +1435,7 @@ component:
|
|||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: UTIE
|
||||
description: timer interrupt-enable bit for U-mode
|
||||
description: timer interrupt-enable bit for U-mode.``Legal Values:``0.
|
||||
bitOffset: '4'
|
||||
resets:
|
||||
reset:
|
||||
|
|
@ -1347,6 +1455,18 @@ component:
|
|||
mask: '0x1'
|
||||
bitWidth: '1'
|
||||
access: read-write
|
||||
- name: Reserved_2
|
||||
displayName: Reserved
|
||||
description: Reserved.``Legal Values:``0.
|
||||
bitOffset: '2'
|
||||
resets:
|
||||
reset:
|
||||
value: '0x0'
|
||||
mask: '0x1'
|
||||
bitWidth: '1'
|
||||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: SSIE
|
||||
displayName: S-mode Software Interrupt Enable
|
||||
description: Enables supervisor mode software interrupts.
|
||||
|
|
@ -1360,7 +1480,7 @@ component:
|
|||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: USIE
|
||||
description: enable U-mode software interrrupts
|
||||
description: enable U-mode software interrrupts.``Legal Values:``0.
|
||||
bitOffset: '0'
|
||||
resets:
|
||||
reset:
|
||||
|
|
@ -1593,6 +1713,18 @@ component:
|
|||
volatile: 'true'
|
||||
access: read-write
|
||||
field:
|
||||
- name: Reserved_12
|
||||
displayName: Reserved
|
||||
description: Reserved.``Legal Values:``0.
|
||||
bitOffset: '12'
|
||||
resets:
|
||||
reset:
|
||||
value: '0x0'
|
||||
mask: '0x1'
|
||||
bitWidth: '4'
|
||||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: MEIP
|
||||
displayName: M-mode External Interrupt Pending
|
||||
description: The interrupt-pending bit for machine-level external interrupts.
|
||||
|
|
@ -1604,6 +1736,18 @@ component:
|
|||
bitWidth: '1'
|
||||
volatile: 'true'
|
||||
access: read-only
|
||||
- name: Reserved_10
|
||||
displayName: Reserved
|
||||
description: Reserved.``Legal Values:``0.
|
||||
bitOffset: '10'
|
||||
resets:
|
||||
reset:
|
||||
value: '0x0'
|
||||
mask: '0x1'
|
||||
bitWidth: '1'
|
||||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: SEIP
|
||||
displayName: S-mode External Interrupt Pending
|
||||
description: The interrupt-pending bit for supervisor-level external interrupts.
|
||||
|
|
@ -1615,7 +1759,7 @@ component:
|
|||
bitWidth: '1'
|
||||
access: read-write
|
||||
- name: UEIP
|
||||
description: enables external interrupts
|
||||
description: enables external interrupts.``Legal Values:``0.
|
||||
bitOffset: '8'
|
||||
resets:
|
||||
reset:
|
||||
|
|
@ -1634,6 +1778,18 @@ component:
|
|||
bitWidth: '1'
|
||||
volatile: 'true'
|
||||
access: read-only
|
||||
- name: Reserved_6
|
||||
displayName: Reserved
|
||||
description: Reserved.``Legal Values:``0.
|
||||
bitOffset: '6'
|
||||
resets:
|
||||
reset:
|
||||
value: '0x0'
|
||||
mask: '0x1'
|
||||
bitWidth: '1'
|
||||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: STIP
|
||||
displayName: S-mode Timer Interrupt Pending
|
||||
description: The interrupt-pending bit for supervisor-level timer interrupts.
|
||||
|
|
@ -1645,7 +1801,7 @@ component:
|
|||
bitWidth: '1'
|
||||
access: read-write
|
||||
- name: UTIP
|
||||
description: Correspond to timer interrupt-pending bits for user interrupt
|
||||
description: Correspond to timer interrupt-pending bits for user interrupt.``Legal Values:``0.
|
||||
bitOffset: '4'
|
||||
resets:
|
||||
reset:
|
||||
|
|
@ -1664,6 +1820,18 @@ component:
|
|||
bitWidth: '1'
|
||||
volatile: 'true'
|
||||
access: read-only
|
||||
- name: Reserved_2
|
||||
displayName: Reserved
|
||||
description: Reserved.``Legal Values:``0.
|
||||
bitOffset: '2'
|
||||
resets:
|
||||
reset:
|
||||
value: '0x0'
|
||||
mask: '0x1'
|
||||
bitWidth: '1'
|
||||
access: read-write
|
||||
vendorExtensions:
|
||||
RISCV_behavior: WARL
|
||||
- name: SSIP
|
||||
displayName: S-mode Software Interrupt Pending
|
||||
description: The interrupt-pending bit for supervisor-level software interrupts.
|
||||
|
|
@ -1675,7 +1843,7 @@ component:
|
|||
bitWidth: '1'
|
||||
access: read-write
|
||||
- name: USIP
|
||||
description: A hart to directly write its own USIP bits when running in the appropriate mode
|
||||
description: A hart to directly write its own USIP bits when running in the appropriate mode.``Legal Values:``0.
|
||||
bitOffset: '0'
|
||||
resets:
|
||||
reset:
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue