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Implemented dummy MMU, currently pass-through

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This commit is contained in:
Florian Zaruba 2017-04-19 14:17:59 +02:00
parent 82de9e929a
commit 85dadce09f
4 changed files with 136 additions and 13 deletions
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1
Makefile
View file

@ -17,6 +17,7 @@ interfaces = include/debug_if.svh include/mem_if.svh
src = alu.sv tb/sequences/alu_sequence_pkg.sv tb/env/alu_env_pkg.sv tb/test/alu_lib_pkg.sv tb/alu_tb.sv \
tb/scoreboard_tb.sv \
if_stage.sv compressed_decoder.sv fetch_fifo.sv commit_stage.sv prefetch_buffer.sv \
mmu.sv \
scoreboard.sv issue_read_operands.sv decoder.sv id_stage.sv util/cluster_clock_gating.sv regfile.sv ex_stage.sv ariane.sv \
tb/core_tb.sv

1
README.md
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@ -14,6 +14,7 @@ For detailed documentation refer to the [online documentation](http://www.be4web
- For port definitions keep a post-fix direction (`_o`, `_i`).
- For active low signals put an additional (`_no`, `_ni`).
- Denote output of ff with `_q` and the input with `_n`.
- Do not use CamelCase
- Do not put overly large comment headers. Nevertheless, try to structure your HDL code, e.g.:
```
// ------------------------------------

75
ariane.sv
View file

@ -29,10 +29,8 @@ module ariane
input logic [ 5:0] cluster_id_i,
// Instruction memory interface
mem_if.Slave instr_if,
// Data memory interface
mem_if.Slave data_if,
// Interrupt inputs
input logic irq_i, // level sensitive IR lines
input logic [4:0] irq_id_i,
@ -76,6 +74,7 @@ module ariane
logic instr_gnt_i;
logic instr_rvalid_i;
logic [31:0] instr_rdata_i;
logic [31:0] fetch_rdata_o;
logic instr_valid_id_o;
logic [31:0] instr_rdata_id_o;
logic is_compressed_id_o;
@ -90,8 +89,30 @@ module ariane
logic commit_ack_i;
priv_lvl_t priv_lvl_o;
exception exception_o;
exception exception_if;
scoreboard_entry commit_instr_o;
logic enable_translation_i;
logic fetch_req_i;
logic fetch_gnt_o;
logic fetch_valid_o;
logic fetch_err_o;
logic [63:0] fetch_vaddr_i;
logic lsu_req_i;
logic lsu_gnt_o;
logic lsu_we_i;
logic [3:0] lsu_be_i;
logic lsu_err_o;
logic [63:0] lsu_vaddr_i;
priv_lvl_t priv_lvl_i;
logic flag_pum_i;
logic flag_mxr_i;
logic [19:0] pd_ppn_i;
logic [0:0] asid_i;
logic flush_tlb_i;
logic lsu_ready_wb_i;
assign id_ready_i = 1'b1;
assign halt_if_i = 1'b0;
@ -103,18 +124,18 @@ module ariane
.if_busy_o ( if_busy_o ),
.id_ready_i ( id_ready_i ),
.halt_if_i ( halt_if_i ),
.instr_req_o ( instr_if.data_req ),
.instr_addr_o ( instr_if.address ),
.instr_gnt_i ( instr_if.data_gnt ),
.instr_rvalid_i ( instr_if.data_rvalid ),
.instr_rdata_i ( instr_if.data_rdata ),
.instr_req_o ( fetch_req_i ),
.instr_addr_o ( fetch_vaddr_i ),
.instr_gnt_i ( fetch_gnt_o ),
.instr_rvalid_i ( fetch_valid_o ),
.instr_rdata_i ( fetch_rdata_o ),
.instr_valid_id_o ( instr_valid_id_o ),
.instr_rdata_id_o ( instr_rdata_id_o ),
.is_compressed_id_o ( is_compressed_id_o ),
.illegal_c_insn_id_o ( illegal_c_insn_id_o ),
.pc_if_o ( pc_if_o ),
.pc_id_o ( pc_id_o ),
.ex_o ( exception_o ),
.ex_o ( exception_if ),
.boot_addr_i ( boot_addr_i )
);
@ -130,7 +151,7 @@ module ariane
.instruction_i ( instr_rdata_id_o ),
.instruction_valid_i ( instr_valid_id_o ),
.pc_if_i ( pc_if_o ), // PC from if
.ex_i ( exception_o ), // exception from if
.ex_i ( exception_if ), // exception from if
.ready_o ( ready_o ),
.operator_o ( operator_o ),
.operand_a_o ( operand_a_o ),
@ -138,10 +159,10 @@ module ariane
.trans_id_o ( trans_id_o ),
.alu_ready_i ( alu_ready_i ),
.alu_valid_o ( alu_valid_i ),
.lsu_ready_i ( lsu_ready_i ),
.lsu_valid_o ( lsu_valid_o ),
.mult_ready_i ( mult_ready_i ),
.mult_valid_o ( mult_valid_o ),
.lsu_ready_i ( ),
.lsu_valid_o ( ),
.mult_ready_i ( ),
.mult_valid_o ( ),
.trans_id_i ( {alu_trans_id} ),
.wdata_i ( {alu_result} ),
.wb_valid_i ( {alu_valid_o} ),
@ -187,6 +208,34 @@ module ariane
.we_a_o ( we_a_i )
);
mmu i_mmu (
.clk_i ( clk_i ),
.rst_ni ( rst_n ),
.enable_translation_i ( enable_translation_i ),
.fetch_req_i ( fetch_req_i ),
.fetch_gnt_o ( fetch_gnt_o ),
.fetch_valid_o ( fetch_valid_o ),
.fetch_err_o ( fetch_err_o ),
.fetch_vaddr_i ( fetch_vaddr_i ),
.fetch_rdata_o ( fetch_rdata_o ),
.lsu_req_i ( lsu_req_i ),
.lsu_gnt_o ( lsu_gnt_o ),
.lsu_valid_o ( lsu_valid_o ),
.lsu_we_i ( lsu_we_i ),
.lsu_be_i ( lsu_be_i ),
.lsu_err_o ( lsu_err_o ),
.lsu_vaddr_i ( lsu_vaddr_i ),
.priv_lvl_i ( priv_lvl_i ), // from CSR
.flag_pum_i ( flag_pum_i ), // from CSR
.flag_mxr_i ( flag_mxr_i ), // from CSR
.pd_ppn_i ( pd_ppn_i ), // from CSR
.asid_i ( asid_i ), // from CSR
.flush_tlb_i ( flush_tlb_i ),
.lsu_ready_wb_i ( lsu_ready_wb_i ),
.instr_if ( instr_if ),
.data_if ( data_if )
);
always_ff @(posedge clk_i or negedge rst_n) begin
if(~rst_n) begin
fetch_enable <= 0;

72
mmu.sv
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@ -0,0 +1,72 @@
// Author: Florian Zaruba, ETH Zurich / David Schaffenrath, TU Graz
// Date: 19/04/2017
// Description: Memory Management Unit for Ariane, contains TLB and
// address translation unit. SV39 as defined in RISC-V
// privilege specification 1.9
//
// Copyright (C) 2017 ETH Zurich, University of Bologna
// All rights reserved.
//
// This code is under development and not yet released to the public.
// Until it is released, the code is under the copyright of ETH Zurich and
// the University of Bologna, and may contain confidential and/or unpublished
// work. Any reuse/redistribution is strictly forbidden without written
// permission from ETH Zurich.
//
// Bug fixes and contributions will eventually be released under the
// SolderPad open hardware license in the context of the PULP platform
// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
// University of Bologna.
//
import ariane_pkg::*;
module mmu #(
parameter int INSTR_TLB_ENTRIES = 4,
parameter int DATA_TLB_ENTRIES = 4,
parameter int ASID_WIDTH = 1
)
(
input logic clk_i,
input logic rst_ni,
input logic enable_translation_i,
// IF interface
input logic fetch_req_i,
output logic fetch_gnt_o,
output logic fetch_valid_o,
output logic fetch_err_o,
input logic [63:0] fetch_vaddr_i,
output logic [31:0] fetch_rdata_o,
// LSU interface
input logic lsu_req_i,
output logic lsu_gnt_o,
output logic lsu_valid_o,
input logic lsu_we_i,
input logic [3:0] lsu_be_i,
output logic lsu_err_o,
input logic [63:0] lsu_vaddr_i,
// General control signals
input priv_lvl_t priv_lvl_i,
input logic flag_pum_i,
input logic flag_mxr_i,
// input logic flag_mprv_i,
input logic [19:0] pd_ppn_i,
input logic [ASID_WIDTH-1:0] asid_i,
input logic flush_tlb_i,
input logic lsu_ready_wb_i,
// Memory interfaces
// Instruction memory interface
mem_if.Slave instr_if,
// Data memory interface
mem_if.Slave data_if
);
// dummy implementation
// instruction interface
assign instr_if.data_req = fetch_req_i;
assign fetch_gnt_o = instr_if.data_gnt;
assign fetch_valid_o = instr_if.data_rvalid;
assign instr_if.address = fetch_vaddr_i;
assign fetch_rdata_o = instr_if.data_rdata;
assign fetch_err_o = 1'b0;
endmodule