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Add Direct D$ Access to acc_dispatcher (#1361)
This commit is contained in:
JeanRochCoulon
GitHub
commit
885be3c1e4
8 changed files with 150 additions and 109 deletions
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@ -54,6 +54,8 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; #(
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input logic flush_ex_i,
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output logic flush_pipeline_o,
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// Interface with cache subsystem
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output dcache_req_i_t [1:0] acc_dcache_req_ports_o,
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input dcache_req_o_t [1:0] acc_dcache_req_ports_i,
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input logic inval_ready_i,
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output logic inval_valid_o,
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output logic [63:0] inval_addr_o,
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@ -412,5 +414,6 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; #(
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assign acc_stall_st_pending_o = 1'b0;
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assign flush_pipeline_o = 1'b0;
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assign acc_dcache_req_ports_o = '0;
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endmodule : acc_dispatcher
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@ -18,7 +18,7 @@
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module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter int unsigned NR_PORTS = 3,
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parameter int unsigned NR_PORTS = 4,
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parameter type axi_req_t = logic,
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parameter type axi_rsp_t = logic
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)(
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@ -524,7 +524,7 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #(
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bypass_ports_req[id].req = miss_req_valid[id] & miss_req_bypass[id];
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bypass_ports_req[id].reqtype = ariane_pkg::SINGLE_REQ;
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bypass_ports_req[id].amo = AMO_NONE;
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bypass_ports_req[id].id = {2'b10, id};
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bypass_ports_req[id].id = 4'b1000 | 4'(id);
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bypass_ports_req[id].addr = miss_req_addr[id];
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bypass_ports_req[id].wdata = miss_req_wdata[id];
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bypass_ports_req[id].we = miss_req_we[id];
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@ -619,7 +619,7 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #(
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.wdata_i ( req_fsm_miss_wdata ),
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.be_i ( req_fsm_miss_be ),
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.size_i ( req_fsm_miss_size ),
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.id_i ( {{CVA6Cfg.AxiIdWidth-4{1'b0}}, 4'b1100} ),
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.id_i ( {{CVA6Cfg.AxiIdWidth-4{1'b0}}, 4'b0111} ),
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.valid_o ( valid_miss_fsm ),
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.rdata_o ( data_miss_fsm ),
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.id_o ( ),
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@ -18,6 +18,7 @@
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module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions
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parameter int unsigned NumPorts = 4,
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parameter type axi_ar_chan_t = logic,
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parameter type axi_aw_chan_t = logic,
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parameter type axi_w_chan_t = logic,
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@ -48,8 +49,8 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
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output logic dcache_miss_o, // we missed on a ld/st
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output logic wbuffer_empty_o, // statically set to 1, as there is no wbuffer in this cache system
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// Request ports
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input dcache_req_i_t [2:0] dcache_req_ports_i, // to/from LSU
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output dcache_req_o_t [2:0] dcache_req_ports_o, // to/from LSU
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input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // to/from LSU
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output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to/from LSU
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// memory side
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output axi_req_t axi_req_o,
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input axi_rsp_t axi_resp_i
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@ -87,10 +88,12 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
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// decreasing priority
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// Port 0: PTW
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// Port 1: Load Unit
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// Port 2: Store Unit
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// Port 2: Accelerator
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// Port 3: Store Unit
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std_nbdcache #(
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.CVA6Cfg ( CVA6Cfg ),
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.ArianeCfg ( ArianeCfg ),
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.NumPorts ( NumPorts ),
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.axi_req_t ( axi_req_t ),
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.axi_rsp_t ( axi_rsp_t )
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) i_nbdcache (
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@ -151,10 +154,10 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
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// to forward the correct write data.
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always_comb begin
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w_select = 0;
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unique case (axi_req_o.aw.id)
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4'b1100: w_select = 2; // dcache
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4'b1000, 4'b1001, 4'b1010, 4'b1011: w_select = 1; // bypass
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default: w_select = 0; // icache
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unique casez (axi_req_o.aw.id)
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4'b0111: w_select = 2; // dcache
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4'b1???: w_select = 1; // bypass
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default: w_select = 0; // icache
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endcase
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end
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@ -199,9 +202,9 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
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);
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// Route responses based on ID
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// 0000 -> I$
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// 10[00|10|01|11] -> Bypass
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// 1100 -> D$
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// 0000 -> I$
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// 0111 -> D$
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// 1??? -> Bypass
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// R Channel
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assign axi_resp_icache.r = axi_resp_i.r;
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assign axi_resp_bypass.r = axi_resp_i.r;
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@ -211,11 +214,11 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
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always_comb begin
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r_select = 0;
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unique case (axi_resp_i.r.id)
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4'b1100: r_select = 0; // dcache
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4'b1000, 4'b1001, 4'b1010, 4'b1011: r_select = 1; // bypass
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4'b0000: r_select = 2; // icache
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default: r_select = 0;
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unique casez (axi_resp_i.r.id)
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4'b0111: r_select = 0; // dcache
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4'b1???: r_select = 1; // bypass
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4'b0000: r_select = 2; // icache
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default: r_select = 0;
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endcase
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end
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@ -238,11 +241,11 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
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always_comb begin
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b_select = 0;
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unique case (axi_resp_i.b.id)
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4'b1100: b_select = 0; // dcache
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4'b1000, 4'b1001, 4'b1010, 4'b1011: b_select = 1; // bypass
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4'b0000: b_select = 2; // icache
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default: b_select = 0;
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unique casez (axi_resp_i.b.id)
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4'b0111: b_select = 0; // dcache
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4'b1???: b_select = 1; // bypass
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4'b0000: b_select = 2; // icache
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default: b_select = 0;
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endcase
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end
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@ -269,11 +272,11 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
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icache_dreq_o.vaddr, icache_dreq_o.data);
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a_invalid_write_data: assert property (
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@(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_i[2].data_req |-> |dcache_req_ports_i[2].data_be |-> (|dcache_req_ports_i[2].data_wdata) !== 1'hX)
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@(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_i[NumPorts-1].data_req |-> |dcache_req_ports_i[NumPorts-1].data_be |-> (|dcache_req_ports_i[NumPorts-1].data_wdata) !== 1'hX)
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else $warning(1,"[l1 dcache] writing invalid data: paddr=%016X, be=%02X, data=%016X",
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{dcache_req_ports_i[2].address_tag, dcache_req_ports_i[2].address_index}, dcache_req_ports_i[2].data_be, dcache_req_ports_i[2].data_wdata);
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{dcache_req_ports_i[NumPorts-1].address_tag, dcache_req_ports_i[NumPorts-1].address_index}, dcache_req_ports_i[NumPorts-1].data_be, dcache_req_ports_i[NumPorts-1].data_wdata);
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generate
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for(genvar j=0; j<2; j++) begin
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for(genvar j=0; j<NumPorts-1; j++) begin
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a_invalid_read_data: assert property (
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@(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_o[j].data_rvalid |-> (|dcache_req_ports_o[j].data_rdata) !== 1'hX)
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else $warning(1,"[l1 dcache] reading invalid data on port %01d: data=%016X",
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@ -16,6 +16,7 @@
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module std_nbdcache import std_cache_pkg::*; import ariane_pkg::*; #(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions
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parameter int unsigned NumPorts = 4,
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parameter type axi_req_t = logic,
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parameter type axi_rsp_t = logic
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)(
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@ -30,8 +31,8 @@ module std_nbdcache import std_cache_pkg::*; import ariane_pkg::*; #(
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input amo_req_t amo_req_i,
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output amo_resp_t amo_resp_o,
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// Request ports
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input dcache_req_i_t [2:0] req_ports_i, // request ports
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output dcache_req_o_t [2:0] req_ports_o, // request ports
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input dcache_req_i_t [NumPorts-1:0] req_ports_i, // request ports
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output dcache_req_o_t [NumPorts-1:0] req_ports_o, // request ports
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// Cache AXI refill port
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output axi_req_t axi_data_o,
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input axi_rsp_t axi_data_i,
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@ -47,34 +48,35 @@ import std_cache_pkg::*;
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// 1. Miss handler
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// 2. PTW
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// 3. Load Unit
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// 4. Store unit
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logic [3:0][DCACHE_SET_ASSOC-1:0] req;
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logic [3:0][DCACHE_INDEX_WIDTH-1:0]addr;
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logic [3:0] gnt;
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cache_line_t [DCACHE_SET_ASSOC-1:0] rdata;
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logic [3:0][DCACHE_TAG_WIDTH-1:0] tag;
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// 4. Accelerator
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// 5. Store unit
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logic [NumPorts:0][DCACHE_SET_ASSOC-1:0] req;
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logic [NumPorts:0][DCACHE_INDEX_WIDTH-1:0]addr;
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logic [NumPorts:0] gnt;
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cache_line_t [DCACHE_SET_ASSOC-1:0] rdata;
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logic [NumPorts:0][DCACHE_TAG_WIDTH-1:0] tag;
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cache_line_t [3:0] wdata;
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logic [3:0] we;
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cl_be_t [3:0] be;
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logic [DCACHE_SET_ASSOC-1:0] hit_way;
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cache_line_t [NumPorts:0] wdata;
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logic [NumPorts:0] we;
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cl_be_t [NumPorts:0] be;
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logic [DCACHE_SET_ASSOC-1:0] hit_way;
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// -------------------------------
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// Controller <-> Miss unit
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// -------------------------------
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logic [2:0] busy;
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logic [2:0][55:0] mshr_addr;
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logic [2:0] mshr_addr_matches;
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logic [2:0] mshr_index_matches;
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logic [63:0] critical_word;
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logic critical_word_valid;
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logic [NumPorts-1:0] busy;
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logic [NumPorts-1:0][55:0] mshr_addr;
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logic [NumPorts-1:0] mshr_addr_matches;
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logic [NumPorts-1:0] mshr_index_matches;
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logic [63:0] critical_word;
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logic critical_word_valid;
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logic [2:0][$bits(miss_req_t)-1:0] miss_req;
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logic [2:0] miss_gnt;
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logic [2:0] active_serving;
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logic [NumPorts-1:0][$bits(miss_req_t)-1:0] miss_req;
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logic [NumPorts-1:0] miss_gnt;
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logic [NumPorts-1:0] active_serving;
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logic [2:0] bypass_gnt;
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logic [2:0] bypass_valid;
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logic [2:0][63:0] bypass_data;
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logic [NumPorts-1:0] bypass_gnt;
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logic [NumPorts-1:0] bypass_valid;
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logic [NumPorts-1:0][63:0] bypass_data;
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// -------------------------------
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// Arbiter <-> Datram,
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// -------------------------------
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@ -89,7 +91,7 @@ import std_cache_pkg::*;
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// Cache Controller
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// ------------------
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generate
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for (genvar i = 0; i < 3; i++) begin : master_ports
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for (genvar i = 0; i < NumPorts; i++) begin : master_ports
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cache_ctrl #(
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.CVA6Cfg ( CVA6Cfg ),
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.ArianeCfg ( ArianeCfg )
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@ -132,7 +134,7 @@ import std_cache_pkg::*;
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// ------------------
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miss_handler #(
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.CVA6Cfg ( CVA6Cfg ),
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.NR_PORTS ( 3 ),
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.NR_PORTS ( NumPorts ),
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.axi_req_t ( axi_req_t ),
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.axi_rsp_t ( axi_rsp_t )
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) i_miss_handler (
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@ -243,7 +245,7 @@ import std_cache_pkg::*;
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// ------------------------------------------------
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tag_cmp #(
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.CVA6Cfg ( CVA6Cfg ),
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.NR_PORTS ( 4 ),
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.NR_PORTS ( NumPorts+1 ),
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.ADDR_WIDTH ( DCACHE_INDEX_WIDTH ),
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.DCACHE_SET_ASSOC ( DCACHE_SET_ASSOC )
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) i_tag_cmp (
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@ -22,7 +22,7 @@
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module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, // contains cacheable regions
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parameter int unsigned NumPorts = 3,
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parameter int unsigned NumPorts = 4,
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parameter type noc_req_t = logic,
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parameter type noc_resp_t = logic
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) (
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@ -50,8 +50,8 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
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input amo_req_t dcache_amo_req_i,
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output amo_resp_t dcache_amo_resp_o,
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// Request ports
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input dcache_req_i_t [2:0] dcache_req_ports_i, // to/from LSU
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output dcache_req_o_t [2:0] dcache_req_ports_o, // to/from LSU
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input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // to/from LSU
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output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to/from LSU
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// writebuffer status
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output logic wbuffer_empty_o,
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output logic wbuffer_not_ni_o,
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@ -193,13 +193,13 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
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for (genvar j=0; j<riscv::XLEN/8; j++) begin : gen_invalid_write_assertion
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a_invalid_write_data: assert property (
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@(posedge clk_i) disable iff (!rst_ni) dcache_req_ports_i[2].data_req |-> dcache_req_ports_i[2].data_be[j] |-> (|dcache_req_ports_i[2].data_wdata[j*8+:8] !== 1'hX))
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@(posedge clk_i) disable iff (!rst_ni) dcache_req_ports_i[NumPorts-1].data_req |-> dcache_req_ports_i[NumPorts-1].data_be[j] |-> (|dcache_req_ports_i[NumPorts-1].data_wdata[j*8+:8] !== 1'hX))
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else $warning(1,"[l1 dcache] writing invalid data: paddr=%016X, be=%02X, data=%016X, databe=%016X",
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{dcache_req_ports_i[2].address_tag, dcache_req_ports_i[2].address_index}, dcache_req_ports_i[2].data_be, dcache_req_ports_i[2].data_wdata, dcache_req_ports_i[2].data_be & dcache_req_ports_i[2].data_wdata);
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{dcache_req_ports_i[NumPorts-1].address_tag, dcache_req_ports_i[NumPorts-1].address_index}, dcache_req_ports_i[NumPorts-1].data_be, dcache_req_ports_i[NumPorts-1].data_wdata, dcache_req_ports_i[NumPorts-1].data_be & dcache_req_ports_i[NumPorts-1].data_wdata);
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end
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for (genvar j=0; j<2; j++) begin : gen_assertion
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for (genvar j=0; j<NumPorts-1; j++) begin : gen_assertion
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a_invalid_read_data: assert property (
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@(posedge clk_i) disable iff (!rst_ni) dcache_req_ports_o[j].data_rvalid && ~dcache_req_ports_i[j].kill_req |-> (|dcache_req_ports_o[j].data_rdata) !== 1'hX)
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else $warning(1,"[l1 dcache] reading invalid data on port %01d: data=%016X",
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@ -15,7 +15,7 @@
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module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter int unsigned NumPorts = 3, // number of miss ports
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parameter int unsigned NumPorts = 4, // number of miss ports
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// ID to be used for read and AMO transactions.
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// note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions
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parameter logic [CACHE_ID_WIDTH-1:0] RdAmoTxId = 1,
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@ -38,8 +38,8 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(
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output amo_resp_t amo_resp_o,
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// Request ports
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input dcache_req_i_t [2:0] req_ports_i,
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output dcache_req_o_t [2:0] req_ports_o,
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input dcache_req_i_t [NumPorts-1:0] req_ports_i,
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output dcache_req_o_t [NumPorts-1:0] req_ports_o,
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output logic [NumPorts-1:0][DCACHE_SET_ASSOC-1:0] miss_vld_bits_o,
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@ -217,60 +217,60 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(
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///////////////////////////////////////////////////////
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|
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// set read port to low priority
|
||||
assign rd_prio[2] = 1'b0;
|
||||
assign rd_prio[NumPorts-1] = 1'b0;
|
||||
|
||||
wt_dcache_wbuffer #(
|
||||
.CVA6Cfg ( CVA6Cfg ),
|
||||
.ArianeCfg ( ArianeCfg )
|
||||
) i_wt_dcache_wbuffer (
|
||||
.clk_i ( clk_i ),
|
||||
.rst_ni ( rst_ni ),
|
||||
.empty_o ( wbuffer_empty_o ),
|
||||
.not_ni_o ( wbuffer_not_ni_o ),
|
||||
.clk_i ( clk_i ),
|
||||
.rst_ni ( rst_ni ),
|
||||
.empty_o ( wbuffer_empty_o ),
|
||||
.not_ni_o ( wbuffer_not_ni_o ),
|
||||
// TODO: fix this
|
||||
.cache_en_i ( cache_en ),
|
||||
.cache_en_i ( cache_en ),
|
||||
// .cache_en_i ( '0 ),
|
||||
// request ports from core (store unit)
|
||||
.req_port_i ( req_ports_i [2] ),
|
||||
.req_port_o ( req_ports_o [2] ),
|
||||
.req_port_i ( req_ports_i [NumPorts-1] ),
|
||||
.req_port_o ( req_ports_o [NumPorts-1] ),
|
||||
// miss unit interface
|
||||
.miss_req_o ( miss_req [2] ),
|
||||
.miss_ack_i ( miss_ack [2] ),
|
||||
.miss_we_o ( miss_we [2] ),
|
||||
.miss_wdata_o ( miss_wdata [2] ),
|
||||
.miss_wuser_o ( miss_wuser [2] ),
|
||||
.miss_vld_bits_o ( miss_vld_bits_o[2] ),
|
||||
.miss_paddr_o ( miss_paddr [2] ),
|
||||
.miss_nc_o ( miss_nc [2] ),
|
||||
.miss_size_o ( miss_size [2] ),
|
||||
.miss_id_o ( miss_id [2] ),
|
||||
.miss_rtrn_vld_i ( miss_rtrn_vld [2] ),
|
||||
.miss_rtrn_id_i ( miss_rtrn_id ),
|
||||
.miss_req_o ( miss_req [NumPorts-1] ),
|
||||
.miss_ack_i ( miss_ack [NumPorts-1] ),
|
||||
.miss_we_o ( miss_we [NumPorts-1] ),
|
||||
.miss_wdata_o ( miss_wdata [NumPorts-1] ),
|
||||
.miss_wuser_o ( miss_wuser [NumPorts-1] ),
|
||||
.miss_vld_bits_o ( miss_vld_bits_o[NumPorts-1] ),
|
||||
.miss_paddr_o ( miss_paddr [NumPorts-1] ),
|
||||
.miss_nc_o ( miss_nc [NumPorts-1] ),
|
||||
.miss_size_o ( miss_size [NumPorts-1] ),
|
||||
.miss_id_o ( miss_id [NumPorts-1] ),
|
||||
.miss_rtrn_vld_i ( miss_rtrn_vld [NumPorts-1] ),
|
||||
.miss_rtrn_id_i ( miss_rtrn_id ),
|
||||
// cache read interface
|
||||
.rd_tag_o ( rd_tag [2] ),
|
||||
.rd_idx_o ( rd_idx [2] ),
|
||||
.rd_off_o ( rd_off [2] ),
|
||||
.rd_req_o ( rd_req [2] ),
|
||||
.rd_tag_only_o ( rd_tag_only [2] ),
|
||||
.rd_ack_i ( rd_ack [2] ),
|
||||
.rd_data_i ( rd_data ),
|
||||
.rd_vld_bits_i ( rd_vld_bits ),
|
||||
.rd_hit_oh_i ( rd_hit_oh ),
|
||||
.rd_tag_o ( rd_tag [NumPorts-1] ),
|
||||
.rd_idx_o ( rd_idx [NumPorts-1] ),
|
||||
.rd_off_o ( rd_off [NumPorts-1] ),
|
||||
.rd_req_o ( rd_req [NumPorts-1] ),
|
||||
.rd_tag_only_o ( rd_tag_only [NumPorts-1] ),
|
||||
.rd_ack_i ( rd_ack [NumPorts-1] ),
|
||||
.rd_data_i ( rd_data ),
|
||||
.rd_vld_bits_i ( rd_vld_bits ),
|
||||
.rd_hit_oh_i ( rd_hit_oh ),
|
||||
// incoming invalidations/cache refills
|
||||
.wr_cl_vld_i ( wr_cl_vld ),
|
||||
.wr_cl_idx_i ( wr_cl_idx ),
|
||||
.wr_cl_vld_i ( wr_cl_vld ),
|
||||
.wr_cl_idx_i ( wr_cl_idx ),
|
||||
// single word write interface
|
||||
.wr_req_o ( wr_req ),
|
||||
.wr_ack_i ( wr_ack ),
|
||||
.wr_idx_o ( wr_idx ),
|
||||
.wr_off_o ( wr_off ),
|
||||
.wr_data_o ( wr_data ),
|
||||
.wr_user_o ( wr_user ),
|
||||
.wr_data_be_o ( wr_data_be ),
|
||||
.wr_req_o ( wr_req ),
|
||||
.wr_ack_i ( wr_ack ),
|
||||
.wr_idx_o ( wr_idx ),
|
||||
.wr_off_o ( wr_off ),
|
||||
.wr_data_o ( wr_data ),
|
||||
.wr_user_o ( wr_user ),
|
||||
.wr_data_be_o ( wr_data_be ),
|
||||
// write buffer forwarding
|
||||
.wbuffer_data_o ( wbuffer_data ),
|
||||
.tx_paddr_o ( tx_paddr ),
|
||||
.tx_vld_o ( tx_vld )
|
||||
.wbuffer_data_o ( wbuffer_data ),
|
||||
.tx_paddr_o ( tx_paddr ),
|
||||
.tx_vld_o ( tx_vld )
|
||||
);
|
||||
|
||||
///////////////////////////////////////////////////////
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ module wt_dcache_missunit import ariane_pkg::*; import wt_cache_pkg::*; #(
|
|||
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
|
||||
parameter bit AxiCompliant = 1'b0, // set this to 1 when using in conjunction with AXI bus adapter
|
||||
parameter logic [CACHE_ID_WIDTH-1:0] AmoTxId = 1, // TX id to be used for AMOs
|
||||
parameter int unsigned NumPorts = 3 // number of miss ports
|
||||
parameter int unsigned NumPorts = 4 // number of miss ports
|
||||
) (
|
||||
input logic clk_i, // Clock
|
||||
input logic rst_ni, // Asynchronous reset active low
|
||||
|
|
|
|||
43
core/cva6.sv
43
core/cva6.sv
|
|
@ -205,7 +205,7 @@ module cva6 import ariane_pkg::*; #(
|
|||
logic eret;
|
||||
logic [CVA6ExtendCfg.NrCommitPorts-1:0] commit_ack;
|
||||
|
||||
localparam NumPorts = 3;
|
||||
localparam NumPorts = 4;
|
||||
cvxif_pkg::cvxif_req_t cvxif_req;
|
||||
cvxif_pkg::cvxif_resp_t cvxif_resp;
|
||||
|
||||
|
|
@ -408,6 +408,8 @@ module cva6 import ariane_pkg::*; #(
|
|||
// ----------------
|
||||
dcache_req_i_t [2:0] dcache_req_ports_ex_cache;
|
||||
dcache_req_o_t [2:0] dcache_req_ports_cache_ex;
|
||||
dcache_req_i_t [1:0] dcache_req_ports_acc_cache;
|
||||
dcache_req_o_t [1:0] dcache_req_ports_cache_acc;
|
||||
logic dcache_commit_wbuffer_empty;
|
||||
logic dcache_commit_wbuffer_not_ni;
|
||||
|
||||
|
|
@ -888,6 +890,31 @@ module cva6 import ariane_pkg::*; #(
|
|||
// Cache Subsystem
|
||||
// -------------------
|
||||
|
||||
// Acc dispatcher and store buffer share a dcache request port.
|
||||
// Store buffer always has priority access over acc dipsatcher.
|
||||
dcache_req_i_t [NumPorts-1:0] dcache_req_to_cache;
|
||||
dcache_req_o_t [NumPorts-1:0] dcache_req_from_cache;
|
||||
|
||||
// D$ request
|
||||
assign dcache_req_to_cache[0] = dcache_req_ports_ex_cache[0];
|
||||
assign dcache_req_to_cache[1] = dcache_req_ports_ex_cache[1];
|
||||
assign dcache_req_to_cache[2] = dcache_req_ports_acc_cache[0];
|
||||
assign dcache_req_to_cache[3] = dcache_req_ports_ex_cache[2].data_req ? dcache_req_ports_ex_cache [2] :
|
||||
dcache_req_ports_acc_cache[1];
|
||||
|
||||
// D$ response
|
||||
assign dcache_req_ports_cache_ex [0] = dcache_req_from_cache[0];
|
||||
assign dcache_req_ports_cache_ex [1] = dcache_req_from_cache[1];
|
||||
assign dcache_req_ports_cache_acc[0] = dcache_req_from_cache[2];
|
||||
always_comb begin : gen_dcache_req_store_data_gnt
|
||||
dcache_req_ports_cache_ex [2] = dcache_req_from_cache[3];
|
||||
dcache_req_ports_cache_acc[1] = dcache_req_from_cache[3];
|
||||
|
||||
// Set gnt signal
|
||||
dcache_req_ports_cache_ex [2].data_gnt &= dcache_req_ports_ex_cache[2].data_req;
|
||||
dcache_req_ports_cache_acc[1].data_gnt &= !dcache_req_ports_ex_cache[2].data_req;
|
||||
end
|
||||
|
||||
if (DCACHE_TYPE == int'(cva6_config_pkg::WT)) begin : gen_cache_wt
|
||||
// this is a cache subsystem that is compatible with OpenPiton
|
||||
wt_cache_subsystem #(
|
||||
|
|
@ -918,8 +945,8 @@ module cva6 import ariane_pkg::*; #(
|
|||
// from PTW, Load Unit and Store Unit
|
||||
.dcache_miss_o ( dcache_miss_cache_perf ),
|
||||
.miss_vld_bits_o ( miss_vld_bits ),
|
||||
.dcache_req_ports_i ( dcache_req_ports_ex_cache ),
|
||||
.dcache_req_ports_o ( dcache_req_ports_cache_ex ),
|
||||
.dcache_req_ports_i ( dcache_req_to_cache ),
|
||||
.dcache_req_ports_o ( dcache_req_from_cache ),
|
||||
// write buffer status
|
||||
.wbuffer_empty_o ( dcache_commit_wbuffer_empty ),
|
||||
.wbuffer_not_ni_o ( dcache_commit_wbuffer_not_ni ),
|
||||
|
|
@ -938,6 +965,7 @@ module cva6 import ariane_pkg::*; #(
|
|||
// deprecated
|
||||
.CVA6Cfg ( CVA6ExtendCfg ),
|
||||
.ArianeCfg ( ArianeCfg ),
|
||||
.NumPorts ( NumPorts ),
|
||||
.axi_ar_chan_t ( axi_ar_chan_t ),
|
||||
.axi_aw_chan_t ( axi_aw_chan_t ),
|
||||
.axi_w_chan_t ( axi_w_chan_t ),
|
||||
|
|
@ -967,8 +995,8 @@ module cva6 import ariane_pkg::*; #(
|
|||
// this is statically set to 1 as the std_cache does not have a wbuffer
|
||||
.wbuffer_empty_o ( dcache_commit_wbuffer_empty ),
|
||||
// from PTW, Load Unit and Store Unit
|
||||
.dcache_req_ports_i ( dcache_req_ports_ex_cache ),
|
||||
.dcache_req_ports_o ( dcache_req_ports_cache_ex ),
|
||||
.dcache_req_ports_i ( dcache_req_to_cache ),
|
||||
.dcache_req_ports_o ( dcache_req_from_cache ),
|
||||
// memory side
|
||||
.axi_req_o ( noc_req_o ),
|
||||
.axi_resp_i ( noc_resp_i )
|
||||
|
|
@ -1015,6 +1043,8 @@ module cva6 import ariane_pkg::*; #(
|
|||
.acc_no_st_pending_i ( no_st_pending_commit ),
|
||||
.dcache_req_ports_i ( dcache_req_ports_ex_cache ),
|
||||
.ctrl_halt_o ( halt_acc_ctrl ),
|
||||
.acc_dcache_req_ports_o ( dcache_req_ports_acc_cache ),
|
||||
.acc_dcache_req_ports_i ( dcache_req_ports_cache_acc ),
|
||||
.inval_ready_i ( inval_ready ),
|
||||
.inval_valid_o ( inval_valid ),
|
||||
.inval_addr_o ( inval_addr ),
|
||||
|
|
@ -1035,6 +1065,9 @@ module cva6 import ariane_pkg::*; #(
|
|||
assign stall_st_pending_ex = '0;
|
||||
assign flush_acc = '0;
|
||||
|
||||
// D$ connection is unused
|
||||
assign dcache_req_ports_acc_cache = '0;
|
||||
|
||||
// No invalidation interface
|
||||
assign inval_valid = '0;
|
||||
assign inval_addr = '0;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue