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✅ Add empty store queue test

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This commit is contained in:
Florian Zaruba 2017-04-28 12:58:57 +02:00
parent c65f9a9efa
commit 89042efdba
6 changed files with 189 additions and 30 deletions
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11
.gitlab-ci.yml
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@ -46,6 +46,17 @@ test_mem_arbiter:
paths:
- covhtmlreport
test_store_queue:
stage: test
script:
- make build
- make store_queue
- vcover report store_queue.ucdb
- vcover report -html store_queue.ucdb
artifacts:
paths:
- covhtmlreport
pages:
stage: deploy
dependencies:

15
Makefile
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@ -7,19 +7,20 @@ library = work
# Top level module to compile
top_level = core_tb
test_top_level = core_tb
tests = alu scoreboard fifo mem_arbiter
tests = alu scoreboard fifo mem_arbiter store_queue
# path to agents
agents = tb/agents/fu_if/fu_if.sv tb/agents/fu_if/fu_if_agent_pkg.sv \
include/ariane_pkg.svh tb/agents/scoreboard_if/scoreboard_if.sv tb/agents/scoreboard_if/scoreboard_if_agent_pkg.sv tb/common/eth_tb_pkg.sv
interfaces = include/debug_if.svh include/mem_if.svh tb/agents/fifo_if/fifo_if.sv
interfaces = include/debug_if.svh include/mem_if.svh tb/agents/fifo_if/fifo_if.sv tb/agents/store_queue_if/store_queue_if.sv
# this list contains the standalone components
src = alu.sv tb/sequences/alu_sequence_pkg.sv tb/env/alu_env_pkg.sv tb/test/alu_lib_pkg.sv tb/alu_tb.sv \
tb/scoreboard_tb.sv ptw.sv tlb.sv store_queue.sv \
src = alu.sv tb/sequences/alu_sequence_pkg.sv tb/env/alu_env_pkg.sv tb/test/alu_lib_pkg.sv \
ptw.sv tlb.sv store_queue.sv \
if_stage.sv compressed_decoder.sv fetch_fifo.sv commit_stage.sv prefetch_buffer.sv \
mmu.sv lsu.sv fifo.sv tb/fifo_tb.sv mem_arbiter.sv \
scoreboard.sv issue_read_operands.sv decoder.sv id_stage.sv util/cluster_clock_gating.sv regfile.sv ex_stage.sv ariane.sv \
tb/mem_arbiter_tb.sv tb/core_tb.sv
scoreboard.sv issue_read_operands.sv decoder.sv id_stage.sv util/cluster_clock_gating.sv regfile.sv ex_stage.sv ariane.sv
tb = tb/alu_tb.sv tb/mem_arbiter_tb.sv tb/core_tb.sv tb/scoreboard_tb.sv tb/store_queue_tb.sv
# Search here for include files (e.g.: non-standalone components)
incdir = ./includes
@ -43,7 +44,7 @@ build:
# Compile interfaces
vlog${questa_version} ${compile_flag} -incr ${interfaces} ${list_incdir} -suppress 2583
# Compile source files
vlog${questa_version} ${compile_flag} -incr ${src} ${list_incdir} -suppress 2583
vlog${questa_version} ${compile_flag} -incr ${src} ${tb} ${list_incdir} -suppress 2583
# Optimize top level
vopt${questa_version} ${compile_flag} ${test_top_level} -o ${test_top_level}_optimized +acc -check_synthesis

10
include/mem_if.svh
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@ -9,9 +9,13 @@
// Guard statement proposed by "Easier UVM" (doulos)
`ifndef MEM_IF_SV
`define MEM_IF_SV
interface mem_if #(parameter int ADDRESS_SIZE = 64,
parameter int DATA_WIDTH = 64 )
(input clk);
interface mem_if
#( parameter int ADDRESS_SIZE = 64,
parameter int DATA_WIDTH = 64
)
(
input clk
);
wire [ADDRESS_SIZE-1:0] address; // Address for read/write request
wire [DATA_WIDTH-1:0] data_wdata; // Data to be written
wire data_req; // Requests read data

40
lsu.sv
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@ -29,32 +29,32 @@ module lsu #(
input logic [63:0] operand_a_i,
input logic [63:0] operand_b_i,
input logic [63:0] imm_i,
output logic lsu_ready_o, // FU is ready e.g. not busy
input logic lsu_valid_i, // Input is valid
input logic [TRANS_ID_BITS-1:0] lsu_trans_id_i, // transaction id, needed for WB
output logic [TRANS_ID_BITS-1:0] lsu_trans_id_o, // ID of scoreboard entry at which to write back
output logic lsu_ready_o, // FU is ready e.g. not busy
input logic lsu_valid_i, // Input is valid
input logic [TRANS_ID_BITS-1:0] lsu_trans_id_i, // transaction id, needed for WB
output logic [TRANS_ID_BITS-1:0] lsu_trans_id_o, // ID of scoreboard entry at which to write back
output logic [63:0] lsu_result_o,
output logic lsu_valid_o, // transaction id for which the output is the requested one
input logic commit_i, // commit the pending store
output logic lsu_valid_o, // transaction id for which the output is the requested one
input logic commit_i, // commit the pending store
input logic enable_translation_i,
input logic enable_translation_i, // enable virtual memory translation
input logic fetch_req_i,
output logic fetch_gnt_o,
output logic fetch_valid_o,
output logic fetch_err_o,
input logic [63:0] fetch_vaddr_i,
output logic [31:0] fetch_rdata_o,
input logic fetch_req_i, // Instruction fetch interface
output logic fetch_gnt_o, // Instruction fetch interface
output logic fetch_valid_o, // Instruction fetch interface
output logic fetch_err_o, // Instruction fetch interface
input logic [63:0] fetch_vaddr_i, // Instruction fetch interface
output logic [31:0] fetch_rdata_o, // Instruction fetch interface
input priv_lvl_t priv_lvl_i,
input logic flag_pum_i,
input logic flag_mxr_i,
input logic [37:0] pd_ppn_i,
input logic [ASID_WIDTH-1:0] asid_i,
input priv_lvl_t priv_lvl_i, // From CSR register file
input logic flag_pum_i, // From CSR register file
input logic flag_mxr_i, // From CSR register file
input logic [37:0] pd_ppn_i, // From CSR register file
input logic [ASID_WIDTH-1:0] asid_i, // From CSR register file
input logic flush_tlb_i,
mem_if.Slave instr_if,
mem_if.Slave data_if,
mem_if.Slave instr_if, // Instruction memory/cache
mem_if.Slave data_if, // Data memory/cache
output exception lsu_exception_o // to WB, signal exception status LD/ST exception

55
tb/agents/store_queue_if/store_queue_if.sv Executable file
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@ -0,0 +1,55 @@
// Author: Florian Zaruba, ETH Zurich
// Date: 28.4.2017
// Description: Store Queue Interface
//
//
// Copyright (C) 2017 ETH Zurich, University of Bologna
// All rights reserved.
//
// This code is under development and not yet released to the public.
// Until it is released, the code is under the copyright of ETH Zurich and
// the University of Bologna, and may contain confidential and/or unpublished
// work. Any reuse/redistribution is strictly forbidden without written
// permission from ETH Zurich.
//
// Bug fixes and contributions will eventually be released under the
// SolderPad open hardware license in the context of the PULP platform
// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
// University of Bologna.
//
`ifndef STORE_QUEUE_IF_SV
`define STORE_QUEUE_IF_SV
interface store_queue_if
#( parameter int ADDRESS_SIZE = 64,
parameter int DATA_WIDTH = 64
)
(
input clk
);
wire flush;
wire [ADDRESS_SIZE-1:0] check_paddr;
wire [DATA_WIDTH-1:0] check_data;
wire valid;
wire [DATA_WIDTH/8-1:0] check_be;
wire commit;
wire ready;
wire store_valid;
wire [ADDRESS_SIZE-1:0] store_paddr;
wire [DATA_WIDTH-1:0] store_data;
wire [DATA_WIDTH/8-1:0] store_be;
clocking mck @(posedge clk);
output flush, commit, valid, store_paddr, store_data, store_be;
input check_paddr, check_data, check_be, ready, store_valid;
endclocking
clocking pck @(posedge clk);
input flush, check_paddr, check_data, valid, check_be, commit, ready, store_valid, store_paddr, store_data, store_be;
endclocking
endinterface
`endif

88
tb/store_queue_tb.sv Executable file
View file

@ -0,0 +1,88 @@
// Author: Florian Zaruba, ETH Zurich
// Date: 28.4.2017
// Description: Store Queue Testbench
//
//
// Copyright (C) 2017 ETH Zurich, University of Bologna
// All rights reserved.
//
// This code is under development and not yet released to the public.
// Until it is released, the code is under the copyright of ETH Zurich and
// the University of Bologna, and may contain confidential and/or unpublished
// work. Any reuse/redistribution is strictly forbidden without written
// permission from ETH Zurich.
//
// Bug fixes and contributions will eventually be released under the
// SolderPad open hardware license in the context of the PULP platform
// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
// University of Bologna.
//
module store_queue_tb;
logic rst_ni, clk;
mem_if slave(clk);
store_queue_if store_queue(clk);
store_queue dut (
.clk_i ( clk ),
.rst_ni ( rst_ni ),
.flush_i ( store_queue.flush ),
.paddr_o ( store_queue.check_paddr ),
.data_o ( store_queue.check_data ),
.valid_o ( store_queue.valid ),
.be_o ( store_queue.check_be ),
.commit_i ( store_queue.commit ),
.ready_o ( store_queue.ready ),
.valid_i ( store_queue.store_valid ),
.paddr_i ( store_queue.store_paddr ),
.data_i ( store_queue.store_data ),
.be_i ( store_queue.store_be ),
.address_o ( slave.address ),
.data_wdata_o ( slave.data_wdata ),
.data_req_o ( slave.data_req ),
.data_we_o ( slave.data_we ),
.data_be_o ( slave.data_be ),
.data_gnt_i ( slave.data_gnt ),
.data_rvalid_i ( slave.data_rvalid )
);
initial begin
clk = 1'b0;
rst_ni = 1'b0;
repeat(8)
#10ns clk = ~clk;
rst_ni = 1'b1;
forever
#10ns clk = ~clk;
end
// simulator stopper, this is suboptimal better go for coverage
initial begin
#10000000ns
$stop;
end
program testbench (mem_if slave, store_queue_if store_queue);
// ----------
// Driver
// ----------
initial begin
end
// -------------------
// Monitor && Checker
// -------------------
initial begin
end
endprogram
testbench tb(slave, store_queue);
endmodule