mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-20 04:07:36 -04:00
Split smoke-tests.sh into 3 tests to speed-up CI timing execution of light stage
This commit is contained in:
Jean-Roch Coulon
JeanRochCoulon
parent
ce24338d5b
commit
8a457272b7
5 changed files with 203 additions and 75 deletions
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@ -135,7 +135,23 @@ build_tools:
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- head -10000 verif/sim/logfile.log > artifacts/logs/logfile.log.head
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- if [ -n "$SPIKE_TANDEM" ]; then python3 .gitlab-ci/scripts/report_tandem.py verif/sim/out*/"$DV_SIMULATORS"_sim; else python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log; fi
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smoke-tests:
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smoke-tests-cv32a65x:
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extends:
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- .fe_smoke_test
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variables:
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DASHBOARD_JOB_TITLE: "Smoke test $DV_SIMULATORS"
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DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge most architectures with most testbenchs configurations"
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DASHBOARD_SORT_INDEX: 0
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DASHBOARD_JOB_CATEGORY: "Basic"
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SPIKE_TANDEM: 1
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COLLECT_SIMU_LOGS: 1
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DV_SIMULATORS: "vcs-uvm"
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script:
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- bash verif/regress/smoke-tests-cv32a65x.sh
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- if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone
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- !reference [.simu_after_script]
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smoke-tests-cv32a6_imac_sv32:
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extends:
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- .fe_smoke_test
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variables:
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@ -150,10 +166,30 @@ smoke-tests:
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- DV_SIMULATORS:
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- "vcs-testharness"
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- "questa-testharness"
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- "vcs-uvm"
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script:
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- source $QUESTA_BASHRC
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- bash verif/regress/smoke-tests.sh
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- bash verif/regress/smoke-tests-cv32a6_imac_sv32.sh
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- if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone
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- !reference [.simu_after_script]
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smoke-tests-cv64a6_imafdc_sv39:
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extends:
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- .fe_smoke_test
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variables:
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DASHBOARD_JOB_TITLE: "Smoke test $DV_SIMULATORS"
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DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge most architectures with most testbenchs configurations"
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DASHBOARD_SORT_INDEX: 0
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DASHBOARD_JOB_CATEGORY: "Basic"
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SPIKE_TANDEM: 1
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COLLECT_SIMU_LOGS: 1
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parallel:
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matrix:
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- DV_SIMULATORS:
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- "vcs-testharness"
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- "questa-testharness"
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script:
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- source $QUESTA_BASHRC
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- bash verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh
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- if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone
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- !reference [.simu_after_script]
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52
verif/regress/smoke-tests-cv32a65x.sh
Normal file
52
verif/regress/smoke-tests-cv32a65x.sh
Normal file
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@ -0,0 +1,52 @@
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# Copyright 2021 Thales DIS design services SAS
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#
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# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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# You may obtain a copy of the License at https://solderpad.org/licenses/
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#
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# Original Author: Jean-Roch COULON - Thales
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# where are the tools
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if ! [ -n "$RISCV" ]; then
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echo "Error: RISCV variable undefined"
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return
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fi
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# install the required tools
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source ./verif/regress/install-verilator.sh
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source ./verif/regress/install-spike.sh
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# install the required test suites
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source ./verif/regress/install-riscv-compliance.sh
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source ./verif/regress/install-riscv-tests.sh
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source ./verif/regress/install-riscv-arch-test.sh
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# setup sim env
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source ./verif/sim/setup-env.sh
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echo "$SPIKE_INSTALL_DIR$"
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if ! [ -n "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=vcs-testharness,spike
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fi
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if ! [ -n "$UVM_VERBOSITY" ]; then
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export UVM_VERBOSITY=UVM_NONE
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fi
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export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
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CC_OPTS="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -lgcc"
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cd verif/sim/
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make -C ../.. clean
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make clean_all
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python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS
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make -C ../.. clean
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make clean_all
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cd -
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55
verif/regress/smoke-tests-cv32a6_imac_sv32.sh
Normal file
55
verif/regress/smoke-tests-cv32a6_imac_sv32.sh
Normal file
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@ -0,0 +1,55 @@
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# Copyright 2021 Thales DIS design services SAS
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#
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# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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# You may obtain a copy of the License at https://solderpad.org/licenses/
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#
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# Original Author: Jean-Roch COULON - Thales
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# where are the tools
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if ! [ -n "$RISCV" ]; then
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echo "Error: RISCV variable undefined"
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return
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fi
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# install the required tools
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source ./verif/regress/install-verilator.sh
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source ./verif/regress/install-spike.sh
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# install the required test suites
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source ./verif/regress/install-riscv-compliance.sh
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source ./verif/regress/install-riscv-tests.sh
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source ./verif/regress/install-riscv-arch-test.sh
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# setup sim env
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source ./verif/sim/setup-env.sh
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echo "$SPIKE_INSTALL_DIR$"
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if ! [ -n "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=vcs-testharness,spike
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fi
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if ! [ -n "$UVM_VERBOSITY" ]; then
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export UVM_VERBOSITY=UVM_NONE
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fi
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export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
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CC_OPTS="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -lgcc"
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cd verif/sim/
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make -C ../.. clean
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make clean_all
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python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS
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python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS
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python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/linker/link.ld
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python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/linker/link.ld --gcc_opts="$CC_OPTS -nostdlib -lgcc" $DV_OPTS
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make -C ../.. clean
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make clean_all
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cd -
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57
verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh
Normal file
57
verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh
Normal file
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@ -0,0 +1,57 @@
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# Copyright 2021 Thales DIS design services SAS
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#
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# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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# You may obtain a copy of the License at https://solderpad.org/licenses/
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#
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# Original Author: Jean-Roch COULON - Thales
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# where are the tools
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if ! [ -n "$RISCV" ]; then
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echo "Error: RISCV variable undefined"
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return
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fi
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# install the required tools
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source ./verif/regress/install-verilator.sh
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source ./verif/regress/install-spike.sh
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# install the required test suites
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source ./verif/regress/install-riscv-compliance.sh
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source ./verif/regress/install-riscv-tests.sh
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source ./verif/regress/install-riscv-arch-test.sh
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# setup sim env
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source ./verif/sim/setup-env.sh
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echo "$SPIKE_INSTALL_DIR$"
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if ! [ -n "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=vcs-testharness,spike
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fi
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if ! [ -n "$UVM_VERBOSITY" ]; then
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export UVM_VERBOSITY=UVM_NONE
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fi
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export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
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CC_OPTS="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -lgcc"
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cd verif/sim/
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make -C ../.. clean
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make clean_all
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python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
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python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml --test rv64ui-v-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
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python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
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python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml --test rv64i_m-add-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/linker/link.ld
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python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
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python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --gcc_opts="$CC_OPTS -nostdlib -lgcc" $DV_OPTS --linker=../../config/gen_from_riscv_config/linker/link.ld
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make -C ../.. clean
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make clean_all
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cd -
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@ -1,72 +0,0 @@
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# Copyright 2021 Thales DIS design services SAS
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#
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# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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# You may obtain a copy of the License at https://solderpad.org/licenses/
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#
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# Original Author: Jean-Roch COULON - Thales
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# where are the tools
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if ! [ -n "$RISCV" ]; then
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echo "Error: RISCV variable undefined"
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return
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fi
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# install the required tools
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source ./verif/regress/install-verilator.sh
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source ./verif/regress/install-spike.sh
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# install the required test suites
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source ./verif/regress/install-riscv-compliance.sh
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source ./verif/regress/install-riscv-tests.sh
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source ./verif/regress/install-riscv-arch-test.sh
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# setup sim env
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source ./verif/sim/setup-env.sh
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echo "$SPIKE_INSTALL_DIR$"
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if ! [ -n "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=vcs-testharness,spike
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fi
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if ! [ -n "$UVM_VERBOSITY" ]; then
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export UVM_VERBOSITY=UVM_NONE
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fi
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export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
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CC_OPTS="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -lgcc"
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cd verif/sim/
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if [[ "$DV_SIMULATORS" != *"uvm"* ]]; then
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make -C ../.. clean
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make clean_all
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python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
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python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml --test rv64ui-v-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
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python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
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python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml --test rv64i_m-add-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/cv32a6_imac_sv32/linker/link.ld
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python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
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python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --gcc_opts="$CC_OPTS -nostdlib -lgcc" $DV_OPTS --linker=../../config/gen_from_riscv_config/cv64a6_imafdc_sv39/linker/test.ld
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make -C ../.. clean
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make clean_all
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python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS
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python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS
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python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/cv32a6_imac_sv32/linker/link.ld
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python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a6_imac_sv32/linker/test.ld --gcc_opts="$CC_OPTS -nostdlib -lgcc" $DV_OPTS
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fi
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if [[ "$DV_SIMULATORS" == *"uvm"* ]]; then
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make -C ../.. clean
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make clean_all
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python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/test.ld --gcc_opts="$CC_OPTS" $DV_OPTS
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fi
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make -C ../.. clean
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make clean_all
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cd -
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