Load tests in physical mode are passing [ci skip]

CHANGELOG.md

@@ -6,6 +6,18 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 ## [Unreleased]
 
+### 1.0.0
+
+### Added
+
+- Non-blocking data cache
+- Two AXI interfaces on top level, one for bypassing and one for actual cache-able regions
+
+### Changed
+
+- Testbench: EOC component now listening on store interface only
+- Store interfaces has been simplified by removing the `valid` signal, a transaction is now considered finished as soon as the dcache gives the grant signal.
+
 ### 0.4.0 - 2017-10-13
 
 Linux booting on FPGA.

include/nbdcache_pkg.sv

@@ -46,10 +46,10 @@ package nbdcache_pkg;
     } miss_req_t;
 
     typedef struct packed {
-        logic [TAG_WIDTH-1:0]                tag;    // tag array
-        logic [CACHE_LINE_WIDTH/8-1:0][7:0]  data;   // data array
-        logic                                valid;  // state array
-        logic                                dirty;  // state array
+        logic [TAG_WIDTH-1:0]           tag;    // tag array
+        logic [CACHE_LINE_WIDTH-1:0]    data;   // data array
+        logic                           valid;  // state array
+        logic                           dirty;  // state array
     } cache_line_t;
 
     // cache line byte enable

src/cache_ctrl.sv

@@ -82,6 +82,11 @@ module cache_ctrl #(
     // Cache FSM
     // --------------
     always_comb begin : cache_ctrl_fsm
+        // incoming cache-line -> this is needed as synopsys is not supporting +: indexing in a multi-dimensional array
+        automatic logic [CACHE_LINE_WIDTH-1:0] cl_i = data_i[one_hot_to_bin(hit_way_i)].data;
+        // cache-line offset -> multiple of 64
+        automatic logic [$clog2(CACHE_LINE_WIDTH)-1:0] cl_offset = mem_req_q.index[BYTE_OFFSET-1:3] << 6;
+        automatic logic [$clog2(CACHE_LINE_WIDTH/8)-1:0] be_offset =  mem_req_q.index[BYTE_OFFSET-1:3] << 3;
         // default assignments
         state_d   = state_q;
         mem_req_d = mem_req_q;
@@ -142,10 +147,6 @@ module cache_ctrl #(
 
             // cache enabled and waiting for tag
             WAIT_TAG, WAIT_TAG_SAVED: begin
-                // incoming cache-line -> this is needed as synopsys is not supporting +: indexing in a multi-dimensional array
-                automatic logic [CACHE_LINE_WIDTH-1:0] cl_i = data_i[one_hot_to_bin(hit_way_i)].data;
-                // cache-line offset -> multiple of 64
-                automatic logic [$clog2(CACHE_LINE_WIDTH)-1:0] cl_offset = mem_req_q.index[BYTE_OFFSET-1:0] << 3;
                 // depending on where we come from
                 // For the store case the tag comes in the same cycle
                 tag_o = (state_q == WAIT_TAG_SAVED || mem_req_q.we) ? mem_req_q.tag :  address_tag_i;
@@ -224,8 +225,8 @@ module cache_ctrl #(
                 be_o.dirty = hit_way_q;
                 be_o.valid = hit_way_q;
 
-                be_o.data[mem_req_q.index[BYTE_OFFSET-1:0] +: 64] = mem_req_q.be;
-                data_o.data[mem_req_q.index[BYTE_OFFSET-1:0] +: 64] = mem_req_q.wdata;
+                be_o.data[be_offset +: 8] = mem_req_q.be;
+                data_o.data[cl_offset +: 64] = mem_req_q.wdata;
                 // ~> change the state
                 data_o.dirty = 1'b1;
                 data_o.valid = 1'b1;

src/miss_handler.sv

@@ -192,7 +192,7 @@ module miss_handler #(
             // ~> replace the cacheline
             REPL_CACHELINE: begin
                 // calculate cacheline offset
-                automatic logic [BYTE_OFFSET-1:0] cl_offset = mshr_q.addr[BYTE_OFFSET-1:0];
+                automatic logic [BYTE_OFFSET-1:0] cl_offset = mshr_q.addr[BYTE_OFFSET-1:3] << 6;
                 // we've got a valid response from refill unit
                 if (valid_miss_fsm) begin
 
@@ -213,7 +213,7 @@ module miss_handler #(
                         for (int i = 0; i < 8; i++) begin
                             // check if we really want to write the corresponding bute
                             if (mshr_q.be[i])
-                                data_o.data[cl_offset + i] = mshr_q.wdata[i];
+                                data_o.data[(cl_offset + i*8) +: 8] = mshr_q.wdata[i];
                         end
                         // its immediately dirty if we write
                         data_o.dirty = 1'b1;