⚡ restructure travis and gitlab-ci flow scripts and make targets

* fix typo in signal naming and make axi_adapter questa-sim compliant
2025-04-22 05:07:21 -04:00 · 2018-08-21 13:54:59 +02:00 · 2018-08-21 13:54:59 +02:00 · 8e89f62181
commit 8e89f62181
parent 238dbf8f04
17 changed files with 372 additions and 167 deletions
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@ -1,102 +1,77 @@
 before_script:
+  - export CXX=g++-4.8.3 CC=gcc-4.8.3
+  # paths to local or network installation (the riscv toolchain and 
+  # verilator are not built in a ci job in this case)
+  - export QUESTASIM_HOME=/scratch/$USER/questasim
+  - export QUESTASIM_VERSION=
+  - export RISCV=/scratch/$USER/riscv_install
+  - export VERILATOR_ROOT=/scratch/$USER/verilator-3.924
+  # setup dependent paths
+  - export PATH=${RISCV}/bin:$VERILATOR_ROOT/bin:${PATH}
+  - export LIBRARY_PATH=$CI_PROJECT_DIR/tmp/lib
+  - export LD_LIBRARY_PATH=$CI_PROJECT_DIR/tmp/lib
+  - export C_INCLUDE_PATH=$CI_PROJECT_DIR/tmp/include:$VERILATOR_ROOT/include
+  - export CPLUS_INCLUDE_PATH=$CI_PROJECT_DIR/tmp/include:$VERILATOR_ROOT/include
+  # number of parallel jobs to use for make commands and simulation
+  - export NUM_JOBS=4
+  - ci/make-tmp.sh
  - git submodule update --init --recursive
-  - export LIBRARY_PATH=$LIBRARY_PATH:$CI_PROJECT_DIR/tmp/lib
-  - export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$CI_PROJECT_DIR/tmp/lib
-  - export C_INCLUDE_PATH=$C_INCLUDE_PATH:$CI_PROJECT_DIR/tmp/include
-  - export CPLUS_INCLUDE_PATH=$CPLUS_INCLUDE_PATH:$CI_PROJECT_DIR/tmp/include
-  - export VERILATOR_ROOT=$CI_PROJECT_DIR/tmp/verilator-3.918/
-
+  
 variables:
  GIT_SUBMODULE_STRATEGY: recursive

 stages:
  - build
  - test
-  - deploy

-build-ci:
+build:
  stage: build
  script:
-    - make build
-    - echo $VERILATOR_ROOT
-    - ci/make-tmp.sh
    - ci/install-fesvr.sh
-    - ci/install-verilator.sh
    - ci/build-riscv-tests.sh
+    - make clean
+    - make build questa_version=$QUESTASIM_VERSION
+    - make verilate verilator=$VERILATOR_ROOT/bin/verilator
  artifacts:
-    paths:
-      - tmp/
+      paths:
+        - tmp 

-test_alu:
+# rv64ui-p-* and rv64ui-v-* tests    
+run-asm-tests-questa:
  stage: test
  script:
-    - make build library=alu_lib
-    - make alu library=alu_lib
-    - vcover-10.6 report alu.ucdb
-
-test_fifo:
-  stage: test
-  script:
-    - make build library=fifo_lib
-    - make fifo library=fifo_lib
-    - vcover-10.6 report fifo.ucdb
-
-.test_scoreboard:
-  stage: test
-  script:
-    - make build library=scoreboard_lib
-    - make scoreboard library=scoreboard_lib
-    - vcover-10.6 report scoreboard.ucdb
-
-
-test_store_queue:
-  stage: test
-  script:
-    - make build library=store_queue_lib
-    - make store_queue library=store_queue_lib
-    - vcover-10.6 report store_queue.ucdb
-
-test_core_asm:
-  stage: test
-  script:
-    - make build library=core_lib
-    - make run-asm-tests library=core_lib
-    - vcover-10.6 report run-asm-tests.ucdb
+    - make -j${NUM_JOBS} run-asm-tests questa_version=$QUESTASIM_VERSION
  dependencies:
-    - build-ci
+    - build

-test_core_asm_verilator:
+run-benchmarks-questa:
  stage: test
  script:
-    - make run-asm-tests-verilator verilator=$CI_PROJECT_DIR/tmp/bin/verilator
+    - make -j${NUM_JOBS} run-benchmarks questa_version=$QUESTASIM_VERSION
  dependencies:
-    - build-ci
+    - build    

-# test with the randomized memory interfaces
-.test_core_asm_rand:
+# rv64ui-p-* tests
+run-asm-tests1-verilator:
  stage: test
  script:
-    - make build library=core_rand_lib
-    # same as above but pass the rand_mem_if flag
-    - make run-asm-tests library=core_rand_lib uvm-flags=+rand_mem_if
-    - vcover-10.6 report run-asm-rand-tests.ucdb
+    - make -j${NUM_JOBS} run-asm-tests1-verilator verilator=$VERILATOR_ROOT/bin/verilator
  dependencies:
-    - build-ci
+    - build

-.test_failed_tests:
+# rv64ui-v-* tests
+run-asm-tests2-verilator:
  stage: test
  script:
-    - make build library=failed_tests_lib
-    - make run-failed-tests library=failed_tests_lib
-    - vcover-10.6 report run-failed-tests.ucdb
+    - make -j${NUM_JOBS} run-asm-tests2-verilator verilator=$VERILATOR_ROOT/bin/verilator
+  dependencies:
+    - build    

-.test_lsu:
+run-benchmarks-verilator:
  stage: test
  script:
-    - make build library=lsu_lib
-    - make lsu library=lsu_lib
-    - vcover-10.6 report lsu.ucdb
-    - vcover-10.6 report -html lsu.ucdb
-  artifacts:
-    paths:
-      - covhtmlreport
+    - make -j${NUM_JOBS} run-benchmarks-verilator verilator=$VERILATOR_ROOT/bin/verilator
+  dependencies:
+    - build
+
+
--- a/.travis.yml
+++ b/.travis.yml
@ -5,6 +5,7 @@ cache:
  apt: true
  directories:
    $RISCV
+    $VERILATOR_ROOT

 # required packages to install
 addons:
@ -32,7 +33,7 @@ addons:
 env:
  global:
    - RISCV="/home/travis/riscv_install"
-    - PATH="/home/travis/riscv_install/bin:$PATH"
+    - VERILATOR_ROOT="/home/travis/verilator-3.924/"

 branches:
  only:
@ -41,12 +42,16 @@ branches:

 before_install:
  - export CXX=g++-4.8 CC=gcc-4.8
-  - ci/make-tmp.sh
+  # setup dependent paths
+  - export PATH=$RISCV/bin:$VERILATOR_ROOT/bin:$PATH
  - export LIBRARY_PATH=$TRAVIS_BUILD_DIR/tmp/lib
  - export LD_LIBRARY_PATH=$TRAVIS_BUILD_DIR/tmp/lib
-  - export C_INCLUDE_PATH=$TRAVIS_BUILD_DIR/tmp/include
-  - export CPLUS_INCLUDE_PATH=$TRAVIS_BUILD_DIR/tmp/include
-  - export VERILATOR_ROOT=$TRAVIS_BUILD_DIR/tmp/verilator-3.924/
+  - export C_INCLUDE_PATH=$TRAVIS_BUILD_DIR/tmp/include:$VERILATOR_ROOT/include
+  - export CPLUS_INCLUDE_PATH=$TRAVIS_BUILD_DIR/tmp/include:$VERILATOR_ROOT/include
+  # number of parallel jobs to use for make commands and simulation
+  - export NUM_JOBS=4
+  - ci/make-tmp.sh
+  - git submodule update --init --recursive

 stages:
  - compile
@ -55,15 +60,30 @@ stages:
 jobs:
  include:
    - stage: compile
+      name: prepare cache
      script:
        - ci/build-riscv-gcc.sh
-    - stage: test
-      script:
        - ci/install-verilator.sh
+    - stage: test
+      name: run riscv benchmarks
+      script:
        - ci/install-fesvr.sh
        - ci/build-riscv-tests.sh
-        - make verilate verilator=$TRAVIS_BUILD_DIR/tmp/bin/verilator
-        - ci/run-tests.sh
-
+        - make -j${NUM_JOBS} run-benchmarks-verilator verilator=$VERILATOR_ROOT/bin/verilator
+    # rv64ui-p-* tests
+    - stage: test
+      name: run rv64ui-p-* asm tests
+      script:
+        - ci/install-fesvr.sh
+        - ci/build-riscv-tests.sh
+        - make -j${NUM_JOBS} run-asm-tests1-verilator verilator=$VERILATOR_ROOT/bin/verilator
+    # rv64ui-v-* tests
+    - stage: test
+      name: run rv64ui-v-* asm tests
+      script:
+        - ci/install-fesvr.sh
+        - ci/build-riscv-tests.sh
+        - make -j${NUM_JOBS} run-asm-tests2-verilator verilator=$VERILATOR_ROOT/bin/verilator
+    
 # extra time during long builds
 install: travis_wait
--- a/120
+++ b/120
@ -3,18 +3,18 @@
 # Description: Makefile for linting and testing Ariane.

 # compile everything in the following library
-library ?= work
+library        ?= work
 # Top level module to compile
-top_level ?= ariane_tb
+top_level      ?= ariane_tb
 test_top_level ?= ariane_tb
 # Maximum amount of cycles for a successful simulation run
-max_cycles ?= 10000000
+max_cycles     ?= 10000000
 # Test case to run
-test_case ?= core_test
+test_case      ?= core_test
 # QuestaSim Version
-questa_version ?=
+questa_version ?= ${QUESTASIM_VERSION}
 # verilator version
-verilator ?= verilator
+verilator      ?= verilator
 # traget option
 target-options ?=
 # Sources
@ -24,37 +24,45 @@ ariane_pkg := include/riscv_pkg.sv     \
              include/ariane_pkg.sv    \
              include/std_cache_pkg.sv \
              include/axi_if.sv
-
 # utility modules
-util := $(wildcard src/util/*.svh) src/util/instruction_tracer_pkg.sv src/util/instruction_tracer_if.sv \
-		src/util/generic_fifo.sv src/util/cluster_clock_gating.sv src/util/behav_sram.sv
+util := $(wildcard src/util/*.svh)         \
+        src/util/instruction_tracer_pkg.sv \
+        src/util/instruction_tracer_if.sv  \
+		src/util/generic_fifo.sv           \
+        src/util/cluster_clock_gating.sv   \
+        src/util/behav_sram.sv
 # Test packages
-test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) $(wildcard tb/test/*/*_pkg.sv*)
+test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \
+            $(wildcard tb/test/*/*_pkg.sv*)
 # DPI
 dpi := $(patsubst tb/dpi/%.cc,work/%.o,$(wildcard tb/dpi/*.cc))
 dpi_hdr := $(wildcard tb/dpi/*.h)
 # this list contains the standalone components
-src := $(wildcard src/*.sv) $(wildcard tb/common/*.sv) $(wildcard tb/common/*.v)                    \
-       $(wildcard src/axi_slice/*.sv) $(wildcard src/clint/*.sv)                                    \
-       $(wildcard src/axi_node/*.sv) $(wildcard src/axi_mem_if/src/*.sv)                            \
-       $(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) $(wildcard bootrom/*.sv)       \
+src := $(wildcard src/*.sv)           $(wildcard tb/common/*.sv)          \
+       $(wildcard tb/common/*.v)      $(wildcard bootrom/*.sv)            \
+       $(wildcard src/axi_slice/*.sv) $(wildcard src/clint/*.sv)          \
+       $(wildcard src/axi_node/*.sv)  $(wildcard src/axi_mem_if/src/*.sv) \
+       $(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv))      \
       $(wildcard src/debug/debug_rom/*.sv)
 # look for testbenches
 tbs := tb/ariane_tb.sv tb/ariane_testharness.sv
-
-# RISCV-tests path
-riscv-test-dir := tmp/riscv-tests/build/isa
-# there is a defined test-list of CI tests
-riscv-ci-tests := $$(xargs printf '\n%s' < ci/test.list | cut -b 1-)
+# RISCV asm tests and benchmark setup (used for CI)
+# there is a defined test-list with selected CI tests
+riscv-test-dir        := tmp/riscv-tests/build/isa/
+riscv-benchmarks-dir  := tmp/riscv-tests/build/benchmarks/
+riscv-asm-tests-list  := ci/riscv-asm-tests.list
+riscv-benchmarks-list := ci/riscv-benchmarks.list
+riscv-asm-tests       := $(shell xargs printf '\n%s' < $(riscv-asm-tests-list)  | cut -b 1-)
+riscv-benchmarks      := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)
 # preset which runs a single test
-riscv-test ?= $(riscv-test-dir)/rv64ui-p-add
+riscv-test ?= rv64ui-p-add
 # failed test directory
 failed-tests := $(wildcard failedtests/*.S)
 # Search here for include files (e.g.: non-standalone components)
 incdir := ./includes
 # Compile and sim flags
 compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive
-uvm-flags += +UVM_NO_RELNOTES
+uvm-flags    += +UVM_NO_RELNOTES
 # Iterate over all include directories and write them with +incdir+ prefixed
 # +incdir+ works for Verilator and QuestaSim
 list_incdir := $(foreach dir, ${incdir}, +incdir+$(dir))
@ -89,23 +97,50 @@ $(library)/ariane_dpi.so: $(dpi)
 $(library):
 	# Create the library
 	vlib${questa_version} ${library}
+
 # +jtag_rbb_enable=1
 sim: build $(library)/ariane_dpi.so
 	vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
-	 +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug  +jtag_rbb_enable=0 \
-	 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" ${top_level}_optimized +permissive-off ++$(riscv-test) ++$(target-options)
+	+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug  +jtag_rbb_enable=0 \
+	-gblso tmp/riscv-fesvr/build/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" \
+    ${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options)

 simc: build $(library)/ariane_dpi.so
 	vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
-	 +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
-	 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" ${top_level}_optimized +permissive-off ++$(riscv-test) ++$(target-options)
+	+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
+	-gblso tmp/riscv-fesvr/build/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" \
+    ${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options)
+
+
+$(riscv-asm-tests): build $(library)/ariane_dpi.so
+	vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+	+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0     \
+	-gblso tmp/riscv-fesvr/build/libfesvr.so -sv_lib $(library)/ariane_dpi                                        \
+	-do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]"    \
+	${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-asm-tests-$@.log 
+
+$(riscv-benchmarks): build $(library)/ariane_dpi.so
+	vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+	+BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0   \
+	-gblso tmp/riscv-fesvr/build/libfesvr.so -sv_lib $(library)/ariane_dpi                                        \
+	-do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]"    \
+	${top_level}_optimized +permissive-off ++$(riscv-benchmarks-dir)/$@ ++$(target-options) | tee tmp/riscv-benchmarks-$@.log 
+
+
+# can use -jX to run ci tests in parallel using X processes
+run-asm-tests: $(riscv-asm-tests)
+	make check-asm-tests	
+
+check-asm-tests: 
+	ci/check-tests.sh tmp/riscv-asm-tests- $(riscv-asm-tests-list)   
+
+# can use -jX to run ci tests in parallel using X processes
+run-benchmarks: $(riscv-benchmarks)
+	make check-benchmarks
+
+check-benchmarks: 
+	ci/check-tests.sh tmp/riscv-benchmarks- $(riscv-benchmarks-list)   

-run-asm-tests: build
-	$(foreach test, $(riscv-ci-tests), vsim$(questa_version) +permissive -64 +BASEDIR=$(riscv-test-dir) +max-cycles=$(max_cycles) \
-		+UVM_TESTNAME=$(test_case) $(uvm-flags) +ASMTEST=$(test) +uvm_set_action="*,_ALL_,UVM_ERROR,UVM_DISPLAY|UVM_STOP" -c \
-		-coverage -classdebug  -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \
-		-do "coverage save -onexit $@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]"  \
-		$(library).$(test_top_level)_optimized +permissive-off ++$(test);)

 verilate_command := $(verilator)                                                     \
                    $(ariane_pkg)                                                    \
@ -144,7 +179,24 @@ verilate_command := $(verilator)
 # User Verilator, at some point in the future this will be auto-generated
 verilate:
 	$(verilate_command)
-	cd build && make -j8 -f Variane_testharness.mk
+	cd build && make -j4 -f Variane_testharness.mk
+
+$(addsuffix -verilator,$(riscv-asm-tests)): verilate
+	build/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
+
+run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests))
+
+# split into two halfs for travis jobs (otherwise they will time out)
+run-asm-tests1-verilator: $(addsuffix -verilator, $(filter rv64ui-p-% ,$(riscv-asm-tests)))
+
+run-asm-tests2-verilator: $(addsuffix -verilator, $(filter rv64ui-v-% ,$(riscv-asm-tests)))
+
+
+$(addsuffix -verilator,$(riscv-benchmarks)): verilate
+	build/Variane_testharness $(riscv-benchmarks-dir)/$(subst -verilator,,$@)
+
+run-benchmarks-verilator: $(addsuffix -verilator,$(riscv-benchmarks))
+

 verify:
 	qverify vlog -sv src/csr_regfile.sv
@ -152,6 +204,8 @@ verify:
 clean:
 	rm -rf work/ *.ucdb
 	rm -rf build
+	rm -f tmp/*.ucdb
+	rm -f tmp/*.log

 .PHONY:
-	build lint build-moore
+	build lint build-moore $(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) check simc sim verilate clean verilate
--- a/ci/build-riscv-gcc.sh
+++ b/ci/build-riscv-gcc.sh
@ -3,6 +3,10 @@ set -e
 ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
 cd $ROOT/tmp

+if [ -z ${NUM_JOBS} ]; then
+    NUM_JOBS=1
+fi
+
 if ! [ -e $RISCV/bin ]; then
    [ -d $ROOT/tmp/riscv-gnu-toolchain ] || git clone https://github.com/riscv/riscv-gnu-toolchain.git
    cd riscv-gnu-toolchain
@ -13,6 +17,6 @@ if ! [ -e $RISCV/bin ]; then

    echo "Compiling RISC-V Toolchain"
    ./configure --prefix=$RISCV > /dev/null
-    make -j2 > /dev/null
+    make -j${NUM_JOBS} > /dev/null
    echo "Compilation Finished"
 fi
--- a/ci/build-riscv-tests.sh
+++ b/ci/build-riscv-tests.sh
@ -3,6 +3,10 @@ set -e
 ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
 cd $ROOT/tmp

+if [ -z ${NUM_JOBS} ]; then
+    NUM_JOBS=1
+fi
+
 [ -d $ROOT/tmp/riscv-tests ] || git clone https://github.com/riscv/riscv-tests.git
 cd riscv-tests
 git checkout 294bfce8a1ca2fc501b8939292146e44f813a2b8
@ -11,5 +15,6 @@ autoconf
 mkdir -p build
 cd build
 ../configure --prefix=$ROOT/tmp/riscv-tests/build
-make isa -j2 > /dev/null
+make isa        -j${NUM_JOBS} > /dev/null
+make benchmarks -j${NUM_JOBS} > /dev/null
 make install
--- a/ci/check-tests.sh
+++ b/ci/check-tests.sh
@ -0,0 +1,67 @@
+#!/bin/bash
+# check simulation output (only for questasim flow)
+#
+# $1 simulation output file basename
+# $2 list file containing the test names
+#
+
+ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
+cd $ROOT
+
+# only use colors in interactive mode
+if [[ -z "$-" ]]; then
+  GREEN=''
+  RED=''
+  NC='' 
+else
+  GREEN='\033[0;32m'
+  RED='\033[0;31m'
+  NC='\033[0m' # No Color
+fi
+
+if [ ! -f "${1}"*.log ]; then
+  echo -e "${RED}FAILED file $1 does not exist ${NC}"
+  exit 1;
+fi
+
+if [ ! -f "$2" ]; then
+  echo -e "${RED}FAILED file $2 does not exist ${NC}"
+  exit 1;
+fi
+
+# get NUM_TOTAL number of tests
+NUM_TOTAL=`wc -l $2 | awk -F " " '{ print $1 }'`
+
+echo "list containint tests: $2"
+
+echo "checking files:"
+ls "${1}"*.log
+
+# check for patterns
+NUM_PASSED=`grep -s "SUCCESS"  ${1}*.log | wc -l`
+NUM_FAILED=`grep -s "FAILED"   ${1}*.log | wc -l`
+NUM_FATAL=`grep  -s "Fatal:"   ${1}*.log | wc -l`
+NUM_ERROR=`grep  -s "Error:"   ${1}*.log | wc -l`
+
+echo "NUM_TOTAL:  $NUM_TOTAL"
+echo "NUM_PASSED: $NUM_PASSED"
+echo "NUM_FAILED: $NUM_FAILED"
+echo "NUM_FATAL:  $NUM_FATAL"
+echo "NUM_ERROR:  $NUM_ERROR"
+
+if [[ $(($NUM_FAILED)) -gt 0 ]]; then 
+  echo -e "${RED}FAILED $NUM_FAILED of $NUM_TOTAL tests ${NC}"
+  exit 1;
+elif [[ $(($NUM_FATAL)) -ne  0 ]]; then
+  echo -e "${RED}FAILED at least one test due to $NUM_FATAL FATAL assertions ${NC}"
+  exit 1;
+elif [[ $(($NUM_ERROR)) -ne 0 ]]; then
+  echo -e "${RED}FAILED at least one test due to $NUM_ERROR ERROR assertions ${NC}"
+  exit 1;
+elif [[ $(($NUM_PASSED)) -ne $(($NUM_TOTAL)) ]]; then
+  echo -e "${RED}FAILED since not all tests have been executed  ${NC}"
+  exit 1;
+else
+  echo -e "${GREEN}PASSED all $NUM_TOTAL tests ${NC}"
+  exit 0;
+fi    
--- a/ci/gitlab-ci-emul.sh
+++ b/ci/gitlab-ci-emul.sh
@ -0,0 +1,43 @@
+# !/bin/bash
+# This script emulates what the gitlab ci config does (not on public server)
+# source this with a bash shell in the project root
+# comment out next command if you don't want to use sudo
+sudo apt install \
+    gcc-4.8 \
+    g++-4.8 \
+    gperf \
+    autoconf \
+    automake \
+    autotools-dev \
+    libmpc-dev \
+    libmpfr-dev \
+    libgmp-dev \
+    gawk \
+    build-essential \
+    bison \
+    flex \
+    texinfo \
+    python-pexpect \
+    libusb-1.0-0-dev \
+    device-tree-compiler
+
+# customize your paths here
+source ci/path-setup.sh
+
+git submodule update --init --recursive
+ci/make-tmp.sh
+ci/build-riscv-gcc.sh
+ci/install-fesvr.sh
+ci/install-verilator.sh
+ci/build-riscv-tests.sh
+make clean
+
+# run asm tests on verilator
+make -j${NUM_JOBS} verilate                 verilator=$VERILATOR_ROOT/bin/verilator
+make -j${NUM_JOBS} run-asm-tests-verilator  verilator=$VERILATOR_ROOT/bin/verilator
+make -j${NUM_JOBS} run-benchmarks-verilator verilator=$VERILATOR_ROOT/bin/verilator
+
+# run asm tests on questa
+make -j${NUM_JOBS} build                    questa_version=$QUESTASIM_VERSION
+make -j${NUM_JOBS} run-asm-tests            questa_version=$QUESTASIM_VERSION
+make -j${NUM_JOBS} run-benchmarks           questa_version=$QUESTASIM_VERSION
--- a/ci/install-fesvr.sh
+++ b/ci/install-fesvr.sh
@ -4,6 +4,10 @@ ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
 cd $ROOT/tmp
 RELEASE=0.1.0

+if [ -z ${NUM_JOBS} ]; then
+    NUM_JOBS=1
+fi
+
 if ! [ -e $ROOT/tmp/riscv-fesvr ]; then
    git clone https://github.com/riscv/riscv-fesvr.git
 fi
@ -11,5 +15,5 @@ cd $ROOT/tmp/riscv-fesvr
 mkdir -p build
 cd build
 ../configure --prefix="$ROOT/tmp"
-make -j2
+make -j${NUM_JOBS}
 make install
--- a/ci/install-verilator.sh
+++ b/ci/install-verilator.sh
@ -3,11 +3,19 @@ set -e
 ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
 cd $ROOT/tmp

-if [ ! -e "$ROOT/tmp/bin/verilator" ]; then
+if [ -z ${NUM_JOBS} ]; then
+    NUM_JOBS=1
+fi
+
+if [ ! -e "$VERILATOR_ROOT/bin/verilator" ]; then
    echo "Installing Verilator"
    wget https://www.veripool.org/ftp/verilator-3.924.tgz
    tar xzf verilator*.t*gz && cd verilator-*
-    autoconf && ./configure --prefix="$ROOT/tmp" && make -j2 && make test && make install
+    mkdir -p $VERILATOR_ROOT
+    # copy scripts
+    autoconf && ./configure --prefix="$VERILATOR_ROOT" && make -j${NUM_JOBS} 
+    cp -r * $VERILATOR_ROOT/ 
+    make test
 else
    echo "Using Verilator from cached directory."
 fi
--- a/ci/path-setup.sh
+++ b/ci/path-setup.sh
@ -0,0 +1,21 @@
+# Customise this to a fast local disk
+export TOP=/scratch/$USER/projects
+export CI_BUILD_DIR=$TOP/ariane-repo
+
+#customize this to your setup
+export QUESTASIM_HOME=
+export QUESTASIM_VERSION=
+export CXX=g++-4.8 CC=gcc-4.8
+
+# where to install the tools
+export RISCV=$TOP/riscv_install
+export VERILATOR_ROOT=$TOP/verilator-3.924/
+
+export PATH=$RISCV/bin:$VERILATOR_ROOT/bin:$PATH
+export LIBRARY_PATH=$CI_BUILD_DIR/tmp/lib
+export LD_LIBRARY_PATH=$CI_BUILD_DIR/tmp/lib
+export C_INCLUDE_PATH=$CI_BUILD_DIR/tmp/include:$VERILATOR_ROOT/include
+export CPLUS_INCLUDE_PATH=$CI_BUILD_DIR/tmp/include:$VERILATOR_ROOT/include
+
+# number of parallel jobs to use for make commands and simulation
+export NUM_JOBS=8
--- a/ci/riscv-asm-tests.list
+++ b/ci/riscv-asm-tests.list
@ -80,7 +80,6 @@ rv64ui-v-sub
 rv64ui-v-subw
 rv64ui-v-xor
 rv64ui-v-xori
-rv64ui-v-slliw
 rv64ui-v-sll
 rv64ui-v-slli
 rv64ui-v-slliw
--- a/ci/riscv-benchmarks.list
+++ b/ci/riscv-benchmarks.list
@ -0,0 +1,8 @@
+dhrystone.riscv
+median.riscv
+multiply.riscv
+pmp.riscv
+qsort.riscv
+rsort.riscv
+towers.riscv
+vvadd.riscv
--- a/ci/run-tests.sh
+++ b/ci/run-tests.sh
@ -1,5 +0,0 @@
-#!/bin/bash
-set -e
-ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
-# run the tests in parallel, 4 at a time
-printf "$(xargs printf '\n%s' < ${ROOT}/ci/test.list | cut -b 1-)" | xargs -n1 -P4 -I{} ${ROOT}/build/Variane_testharness tmp/riscv-tests/build/isa/{}
--- a/ci/travis-ci-emul.sh
+++ b/ci/travis-ci-emul.sh
@ -0,0 +1,38 @@
+#!/bin/bash
+# This script emulates what travis check in test does on the public server
+# source this with a bash shell in the project root
+# comment out next command if you don't want to use sudo
+sudo apt install \
+    gcc-4.8 \
+    g++-4.8 \
+    gperf \
+    autoconf \
+    automake \
+    autotools-dev \
+    libmpc-dev \
+    libmpfr-dev \
+    libgmp-dev \
+    gawk \
+    build-essential \
+    bison \
+    flex \
+    texinfo \
+    python-pexpect \
+    libusb-1.0-0-dev \
+    device-tree-compiler
+
+# customize your paths here
+source ci/path-setup.sh
+
+git submodule update --init --recursive
+ci/make-tmp.sh
+ci/build-riscv-gcc.sh
+ci/install-fesvr.sh
+ci/install-verilator.sh
+ci/build-riscv-tests.sh
+make clean
+
+# run asm tests on verilator
+make -j${NUM_JOBS} verilate                 verilator=$VERILATOR_ROOT/bin/verilator
+make -j${NUM_JOBS} run-asm-tests-verilator  verilator=$VERILATOR_ROOT/bin/verilator
+make -j${NUM_JOBS} run-benchmarks-verilator verilator=$VERILATOR_ROOT/bin/verilator
--- a/src/axi_adapter.sv
+++ b/src/axi_adapter.sv
@ -16,6 +16,7 @@
 */
 import std_cache_pkg::*;

+
 module axi_adapter #(
        parameter int unsigned DATA_WIDTH          = 256,
        parameter logic        CRITICAL_WORD_FIRST = 0, // the AXI subsystem needs to support wrapping reads for this feature
--- a/src/clint/clint.sv
+++ b/src/clint/clint.sv
@ -50,7 +50,7 @@ module clint #(
    // actual registers
    logic [63:0]               mtime_n, mtime_q;
    logic [NR_CORES-1:0][63:0] mtimecmp_n, mtimecmp_q;
-    logic [NR_CORES-1:0]       msip_n, misp_q;
+    logic [NR_CORES-1:0]       msip_n, msip_q;
    // increase the timer
    logic increase_timer;

@ -111,7 +111,7 @@ module clint #(
        if (en && !we) begin
            case (register_address) inside
                [MSIP_BASE:MSIP_BASE+8*NR_CORES]: begin
-                    rdata = misp_q[$unsigned(address[NR_CORES-1+3:3])];
+                    rdata = msip_q[$unsigned(address[NR_CORES-1+3:3])];
                end

                [MTIMECMP_BASE:MTIMECMP_BASE+8*NR_CORES]: begin
@ -138,9 +138,9 @@ module clint #(
        // check that the mtime cmp register is set to a meaningful value
        for (int unsigned i = 0; i < NR_CORES; i++) begin
            if (mtimecmp_q[i] != 0 && mtime_q >= mtimecmp_q[i])
-                irq_o[i] = 1'b1;
+                timer_irq_o[i] = 1'b1;
            else
-                irq_o[i] = 1'b0;
+                timer_irq_o[i] = 1'b0;
        end
    end

@ -163,11 +163,11 @@ module clint #(
        if(~rst_ni) begin
            mtime_q    <= 64'b0;
            mtimecmp_q <= 'b0;
-            misp_q     <= '0;
+            msip_q     <= '0;
        end else begin
            mtime_q    <= mtime_n;
            mtimecmp_q <= mtimecmp_n;
-            misp_q     <= msip_n;
+            msip_q     <= msip_n;
        end
    end

--- a/travis.sh
+++ b/travis.sh
@ -1,37 +0,0 @@
-# This script emulates what travis check in test does on the public server
-# comment out next command if you don't want to use sudo
-sudo apt install \
-      gcc-4.8 \
-      g++-4.8 \
-      gperf \
-      autoconf \
-      automake \
-      autotools-dev \
-      libmpc-dev \
-      libmpfr-dev \
-      libgmp-dev \
-      gawk \
-      build-essential \
-      bison \
-      flex \
-      texinfo \
-      python-pexpect \
-      libusb-1.0-0-dev \
-      device-tree-compiler
-# Customise this to a fast local disk
-export TOP=/local/scratch/$USER
-export TRAVIS_BUILD_DIR=$TOP/ariane-isatest
-export RISCV=$TOP/riscv_install
-export PATH=$TOP/riscv_install/bin:$TRAVIS_BUILD_DIR/tmp/bin:$PATH
-export CXX=g++-4.8 CC=gcc-4.8
-ci/make-tmp.sh
-export LIBRARY_PATH=$TRAVIS_BUILD_DIR/tmp/lib
-export LD_LIBRARY_PATH=$TRAVIS_BUILD_DIR/tmp/lib
-export C_INCLUDE_PATH=$TRAVIS_BUILD_DIR/tmp/include
-export CPLUS_INCLUDE_PATH=$TRAVIS_BUILD_DIR/tmp/include
-export VERILATOR_ROOT=$TRAVIS_BUILD_DIR/tmp/verilator-3.918/
-ci/build-riscv-gcc.sh
-ci/install-verilator.sh
-ci/install-fesvr.sh
-ci/build-riscv-tests.sh
-make run-asm-tests-verilator