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add gen from riscv config software (#2156)
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config/gen_from_riscv_config/README.md
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config/gen_from_riscv_config/README.md
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<!--
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# Copyright 2024 Thales DIS France SAS
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# Original Author: Abdessamii Oukalrazqou
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-->
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# Gen From Risc-V Config
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This software takes a `Risc -V Config Yaml` description of CSR Registers, and generates ReStructuredText documents and Mardown Documents for CSR Registers and ISA Extensions. In the example/tb directory there is an example of how to generate
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the packages.
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For more details about RISC-V Config Yaml, see [Annexes](##Annexes) section
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## Requirements
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The software depend on python libraries that you need to install using `pip3` command , these libraries exist in `requirements.txt`:
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```bash
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pip3 install -r requirements.txt
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```
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## Usage
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```bash
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#Generate the Markdown-text /Restructred-text documentation for Control and Status Registers (CSR)
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python3 <scripts/riscv_config_gen>.py -s <../riscv-config/Config_Name/generated/isa_gen>.yaml -m <updaters/Config_Name/csr_updater>.yaml -t < Config_Name>
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#Generate the Markdown-text /Restructred-text documentation for ISA extensions
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python3 <scripts/riscv_config_gen>.py -s <../riscv-config/Config_Name/generated/isa_gen>.yaml -i <templates/isa_template>.yaml -m <updaters/Config_Name/isa_updater>.yaml -t < Config_Name>
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```
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## Usage with cv32a65x
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```bash
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#Generate the Markdown-text /Restructred-text documentation for Control and Status Registers (CSR)
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python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_gen.yaml -m updaters/cv32a65x/csr_updater.yaml -t cv32a65x
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#Generate the Markdown-text /Restructred-text documentation for ISA extensions
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python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_gen.yaml -i templates/isa_template.yaml -m updaters/cv32a65x/isa_updater.yaml -t cv32a65x
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```
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You could find your output files in this directory :
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if the output is ISA Documentation:
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[Config_Name]\isa\
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if the output is CSR Documentation :
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[Config_Name]\csr\
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for more details about How to write CSR or ISA Updater,see [UPDATERS](##Updaters) section
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for more details about How to write ISA template ,see [Annexes2](##Annexes2) section
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## Updaters
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Since the Software is to generate Documentation, to add dynamic aspect to the software we add the updater that make us able to update the output of the software either in term of ISA_Extensions we can add or remove an extension from documentation or in term of CSR we can change reset-value or exclude register who have certain conditions.
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- the format of updaters is Yaml type
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- the software may work without updater and will generated the documentation without modification
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Since the software generate CSR and ISA Documentation we have two types of updaters :
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### ISA Updater
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If you want to add an extension to documentation not existed by default u can put it in yaml :
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- Format :
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[Extension_Name]: True
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- Example :
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Zicond : True
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If you want to remove an extension from documentation not existed by default u can put it in yaml :
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- Format :
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[Extension_Name]: False
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- Example :
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Zicmp : False
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If you want to remove an extension from documentation already existed :
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- Format :
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[Extension_Name]: False
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- Example :
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M : False
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Example : ISA_Updater.yaml
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Zicond : True
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Zicsr : False
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I : False
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### CSR Updater
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-If you want to modify any parameter for registers in RISC CONFIG YAML :
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Format :
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Register name :
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sub_feature :
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key : value
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Example :
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misa :
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rv64 :
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accessible : false
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mcause :
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reset-val : 12346
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-If you want to exclude any registers base on condition :
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Format :
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exclude :
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key : value
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sub_key : sub_value (if exist if not dont include it )
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cond: value
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Exemple :
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exclude :
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key : priv_mode
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cond : S
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-If you want to control the number of register in RISC CONFIG YAML :
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Example : (PMPADDR , MHPMCOUNTER, ...)
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Format :
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Register Name :
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range : number
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Exemple :
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pmpaddr :
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range : 6 #it reduces number of pmpaddr registers from (start_index to 6)
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CSR/ISA Updater read RISC-CONFIG.yaml and update the registers so if you want to add register in Risc-V Config you need to respect it architecture.
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## Annexes
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Risc-V Config Yaml file is generated based on Risc-Config tool which include all Control and Status Registers(CSR) and ISA extensions supported in each Config of CVA6.
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- The tool is placed in _vendor/riscv/riscv-config_ :
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<https://github.com/openhwgroup/cva6/tree/master/vendor/riscv/riscv-config>.
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You can execute the tool from `Config/riscv-config` repo :
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- It needs python dependancies with :
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'pip3 install -r ../../vendor/riscv-config/Requirements.txt' .
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- It needs to setup path (From 'CVA6 stage') with :
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'export PYTHONPATH =`pwd ../../vendor/riscv/riscv-config:$PYTHONPATH`.
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- You can do the execution with :
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```bash
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make -C <CVA6_top_directory>/config/riscv-config all
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```
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You can change the target in the makefile located in `config/riscv-config/Makefile`
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The generated files will be located in `config/riscv-config/[target]/generated\`.
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Risc -V Config Yaml is our input file for Gen From Risc-V Config.
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## Annexes2
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isa_full_template.yaml which is in the repo is a file which include all ISA Extensions Description supported by CVA6 if you want to add any extensions to the this Yaml ,
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you can write it on this format :
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__Format__ :
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Extension Full Name:
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Description :
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Subset_Name :
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Instructions :
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Operation type 1:
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Instruction Name:
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Format:
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Description:
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Pseudocode:
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Invalid_Values:
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Exception_Raised:
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Operation type 2:
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Name:
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Format:
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Description:
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Pseudocode:
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Invalid_Values:
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Exception_Raised:
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__Exemple__:
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RV32I Base Integer Instructions:
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Description : |
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the base integer instruction set, also known as the 'RV32I' or 'RV64I' instruction set , depending on the address space size, provides the core functionality required for general-purpose computing .
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it includes instructions for arithmetic, logical, and control operations, as well as memory access
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and manipulation
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Subset_Name : I
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Instructions :
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Integer_Register_Immediate_Operations:
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ADDI:
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Format: addi rd, rs1, imm[11:0]
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Description: add sign-extended 12-bit immediate to register rs1, and store the result in register rd.
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Pseudocode: x[rd] = x[rs1] + sext(imm[11:0])
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Invalid_Values: NONE
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Exception_Raised: NONE
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Integer_Register_Register_Operations:
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ADD:
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Format: add rd, rs1, rs2
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Description: add rs2 to register rs1, and store the result in register rd.
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Pseudocode: x[rd] = x[rs1] + x[rs2]
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Invalid_Values: NONE
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Exception_Raised: NONE
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360
config/gen_from_riscv_config/cv32a65x/csr/csr.md
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360
config/gen_from_riscv_config/cv32a65x/csr/csr.md
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@ -0,0 +1,360 @@
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<!--Copyright (c) 2024 OpenHW Group
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Copyright (c) 2024 Thales
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SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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Author: Abdessamii Oukalrazqou
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-->
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# csr
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## Registers Summary
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|Address|Register Name|Description|
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| :--- | :--- | :--- |
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|0x300|[mstatus](#mstatus)|The mstatus register keeps track of and controls the hart’s current operating state.|
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|0x300|[mstatush](#mstatush)|The mstatush register keeps track of and controls the hart’s current operating state.|
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|0x301|[misa](#misa)|misa is a read-write register reporting the ISA supported by the hart.|
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|0x304|[mie](#mie)|The mie register is an MXLEN-bit read/write register containing interrupt enable bits.|
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|0x305|[mtvec](#mtvec)|MXLEN-bit read/write register that holds trap vector configuration.|
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|0x320|[mcountinhibit](#mcountinhibit)|The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment.|
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|0x323-0x33f|[mhpmevent[3-31]](#mhpmevent[3-31])|The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3.|
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|0x340|[mscratch](#mscratch)|The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode.|
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|0x341|[mepc](#mepc)|The mepc is a warl register that must be able to hold all valid physical and virtual addresses.|
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|0x342|[mcause](#mcause)|The mcause register stores the information regarding the trap.|
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|0x343|[mtval](#mtval)|The mtval is a warl register that holds the address of the instruction which caused the exception.|
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|0x344|[mip](#mip)|The mip register is an MXLEN-bit read/write register containing information on pending interrupts.|
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|0x3a0-0x3af|[pmpcfg[0-15]](#pmpcfg[0-15])|PMP configuration register|
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|0x3b0-0x3ef|[pmpaddr[0-63]](#pmpaddr[0-63])|Physical memory protection address register|
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|0xb00|[mcycle](#mcycle)|Counts the number of clock cycles executed from an arbitrary point in time.|
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|0xb02|[minstret](#minstret)|Counts the number of instructions completed from an arbitrary point in time.|
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|0xb03-0xb1f|[mhpmcounter[3-31]](#mhpmcounter[3-31])|The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode.|
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|0xb80|[mcycleh](#mcycleh)|upper 32 bits of mcycle|
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|0xb82|[minstreth](#minstreth)|Upper 32 bits of minstret.|
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|0xb83-0xb9f|[mhpmcounter[3-31]h](#mhpmcounter[3-31]h)|The mhpmcounterh returns the upper half word in RV32I systems.|
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|0xf11|[mvendorid](#mvendorid)|32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core.|
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|0xf12|[marchid](#marchid)|MXLEN-bit read-only register encoding the base microarchitecture of the hart.|
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|0xf13|[mimpid](#mimpid)|Provides a unique encoding of the version of the processor implementation.|
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|0xf14|[mhartid](#mhartid)|MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.|
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### Registers Description
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#### mstatus
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---
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**Address** 0x300
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**Reset Value**0x0
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**Priviliege mode** M
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**Description** The mstatus register keeps track of and controls the hart’s current operating state.
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|Bits|Field name|legal values|Mask|Access|Description|
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| :--- | :--- | :--- | :--- | :--- | :--- |
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|0|uie|||RW|Stores the state of the user mode interrupts.|
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|1|sie|||RW|Stores the state of the supervisor mode interrupts.|
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|3|mie|0|1|RW|Stores the state of the machine mode interrupts.|
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|4|upie|||RW|Stores the state of the user mode interrupts prior to the trap.|
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|5|spie|||RW|Stores the state of the supervisor mode interrupts prior to the trap.|
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|7|mpie|0|1|RW|Stores the state of the machine mode interrupts prior to the trap.|
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|8|spp|||RW|Stores the previous priority mode for supervisor.|
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|[12:11]|mpp|0x0|0x3|RW|Stores the previous priority mode for machine.|
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|[14:13]|fs|||RW|Encodes the status of the floating-point unit, including the CSR fcsr and floating-point data registers.|
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|[16:15]|xs|0x1|0|RW|Encodes the status of additional user-mode extensions and associated state.|
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|17|mprv|||RW|Modifies the privilege level at which loads and stores execute in all privilege modes.|
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|18|sum|||RW|Modifies the privilege with which S-mode loads and stores access virtual memory.|
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|19|mxr|||RW|Modifies the privilege with which loads access virtual memory.|
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|20|tvm|||RW|Supports intercepting supervisor virtual-memory management operations.|
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|21|tw|||RW|Supports intercepting the WFI instruction.|
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|22|tsr|||RW|Supports intercepting the supervisor exception return instruction.|
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|23|spelp|||RW|Supervisor mode previous expected-landing-pad (ELP) state.|
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|31|sd|||RW|Read-only bit that summarizes whether either the FS field or XS field signals the presence of some dirty state.|
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|[30:24]|Reserved_24|||Reserved|Reserved|
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#### mstatush
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---
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**Address** 0x300
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**Reset Value**0x0
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**Priviliege mode** M
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**Description** The mstatush register keeps track of and controls the hart’s current operating state.
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|Bits|Field name|legal values|Mask|Access|Description|
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| :--- | :--- | :--- | :--- | :--- | :--- |
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|4|sbe|||RW|control the endianness of memory accesses other than instruction fetches for supervisor mode|
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|5|mbe|||RW|control the endianness of memory accesses other than instruction fetches for machine mode|
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|6|gva|||RW|Stores the state of the supervisor mode interrupts.|
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|7|mpv|||RW|Stores the state of the user mode interrupts.|
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|9|mpelp|||RW|Machine mode previous expected-landing-pad (ELP) state.|
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|[31:10]|Reserved_10|||Reserved|Reserved|
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#### misa
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---
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**Address** 0x301
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**Reset Value**0x40001104
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**Priviliege mode** M
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**Description** misa is a read-write register reporting the ISA supported by the hart.
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|Bits|Field name|legal values|Mask|Access|Description|
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| :--- | :--- | :--- | :--- | :--- | :--- |
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|[25:0]|extensions|0x0000000|0x3FFFFFF|RW|Encodes the presence of the standard extensions, with a single bit per letter of the alphabet.|
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|[31:30]|mxl|0|1|RW|Encodes the native base integer ISA width.|
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|[29:26]|Reserved_26|||Reserved|Reserved|
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#### mie
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---
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**Address** 0x304
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**Reset Value**0x0
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**Priviliege mode** M
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**Description** The mie register is an MXLEN-bit read/write register containing interrupt enable bits.
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|Bits|Field name|legal values|Mask|Access|Description|
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| :--- | :--- | :--- | :--- | :--- | :--- |
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|0|usie|||RW|User Software Interrupt enable.|
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|1|ssie|||RW|Supervisor Software Interrupt enable.|
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|2|vssie|||RW|VS-level Software Interrupt enable.|
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|3|msie|0x0|0x1|RW|Machine Software Interrupt enable.|
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|4|utie|||RW|User Timer Interrupt enable.|
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|5|stie|||RW|Supervisor Timer Interrupt enable.|
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|6|vstie|||RW|VS-level Timer Interrupt enable.|
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|7|mtie|0|1|RW|Machine Timer Interrupt enable.|
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|8|ueie|||RW|User External Interrupt enable.|
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|9|seie|||RW|Supervisor External Interrupt enable.|
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|10|vseie|||RW|VS-level External Interrupt enable.|
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|11|meie|0|1|RW|Machine External Interrupt enable.|
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|12|sgeie|||RW|HS-level External Interrupt enable.|
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|[31:13]|Reserved_13|||Reserved|Reserved|
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#### mtvec
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---
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**Address** 0x305
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**Reset Value**0x80010000
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**Priviliege mode** M
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**Description** MXLEN-bit read/write register that holds trap vector configuration.
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|Bits|Field name|legal values|Mask|Access|Description|
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| :--- | :--- | :--- | :--- | :--- | :--- |
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|[1:0]|mode|0x0|0x1|RW|Vector mode.|
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|[31:2]|base|0x3FFFFFFF|0x00000000|RW|Vector base address.|
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#### mcountinhibit
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---
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**Address** 0x320
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**Reset Value**0x0
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**Priviliege mode** M
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**Description** The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment.
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|Bits|Field name|legal values|Mask|Access|Description|
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| :--- | :--- | :--- | :--- | :--- | :--- |
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|[31:0]|mcountinhibit|0x00000000|0xFFFFFFFF|RW|The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment.|
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#### mhpmevent[3-31]
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---
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**Address** 0x323-0x33f
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**Reset Value**0x0
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**Priviliege mode** M
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**Description** The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3.
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|Bits|Field name|legal values|Mask|Access|Description|
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| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|[31:0]|mhpmevent[i]|0x00000000|0xFFFFFFFF|RW|The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3.|
|
||||
|
||||
#### mscratch
|
||||
|
||||
---
|
||||
**Address** 0x340
|
||||
**Reset Value**0x0
|
||||
**Priviliege mode** M
|
||||
**Description** The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode.
|
||||
|Bits|Field name|legal values|Mask|Access|Description|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|[31:0]|mscratch|0x00000000|0xFFFFFFFF|RW|The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode.|
|
||||
|
||||
#### mepc
|
||||
|
||||
---
|
||||
**Address** 0x341
|
||||
**Reset Value**0x0
|
||||
**Priviliege mode** M
|
||||
**Description** The mepc is a warl register that must be able to hold all valid physical and virtual addresses.
|
||||
|Bits|Field name|legal values|Mask|Access|Description|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|[31:0]|mepc|0x00000000|0xFFFFFFFF|RW|The mepc is a warl register that must be able to hold all valid physical and virtual addresses.|
|
||||
|
||||
#### mcause
|
||||
|
||||
---
|
||||
**Address** 0x342
|
||||
**Reset Value**0x0
|
||||
**Priviliege mode** M
|
||||
**Description** The mcause register stores the information regarding the trap.
|
||||
|Bits|Field name|legal values|Mask|Access|Description|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|[30:0]|exception_code|0|15|RW|Encodes the exception code.|
|
||||
|31|interrupt|0x0|0x1|RW|Indicates whether the trap was due to an interrupt.|
|
||||
|
||||
#### mtval
|
||||
|
||||
---
|
||||
**Address** 0x343
|
||||
**Reset Value**0x0
|
||||
**Priviliege mode** M
|
||||
**Description** The mtval is a warl register that holds the address of the instruction which caused the exception.
|
||||
|Bits|Field name|legal values|Mask|Access|Description|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|[31:0]|mtval|0x00000000|0xFFFFFFFF|RW|The mtval is a warl register that holds the address of the instruction which caused the exception.|
|
||||
|
||||
#### mip
|
||||
|
||||
---
|
||||
**Address** 0x344
|
||||
**Reset Value**0x0
|
||||
**Priviliege mode** M
|
||||
**Description** The mip register is an MXLEN-bit read/write register containing information on pending interrupts.
|
||||
|Bits|Field name|legal values|Mask|Access|Description|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|0|usip|||RW|User Software Interrupt Pending.|
|
||||
|1|ssip|||RW|Supervisor Software Interrupt Pending.|
|
||||
|2|vssip|||RW|VS-level Software Interrupt Pending.|
|
||||
|3|msip|0x1|0|RW|Machine Software Interrupt Pending.|
|
||||
|4|utip|||RW|User Timer Interrupt Pending.|
|
||||
|5|stip|||RW|Supervisor Timer Interrupt Pending.|
|
||||
|6|vstip|||RW|VS-level Timer Interrupt Pending.|
|
||||
|7|mtip|0x1|0|RW|Machine Timer Interrupt Pending.|
|
||||
|8|ueip|||RW|User External Interrupt Pending.|
|
||||
|9|seip|||RW|Supervisor External Interrupt Pending.|
|
||||
|10|vseip|||RW|VS-level External Interrupt Pending.|
|
||||
|11|meip|0x1|0|RW|Machine External Interrupt Pending.|
|
||||
|12|sgeip|||RW|HS-level External Interrupt Pending.|
|
||||
|[31:13]|Reserved_13|||Reserved|Reserved|
|
||||
|
||||
#### pmpcfg[0-15]
|
||||
|
||||
---
|
||||
**Address** 0x3a0-0x3af
|
||||
**Reset Value**0x0
|
||||
**Priviliege mode** M
|
||||
**Description** PMP configuration register
|
||||
|Bits|Field name|legal values|Mask|Access|Description|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|[7:0]|pmp[i*4 + 0]cfg|0x00|0xFF|RW|pmp configuration bits|
|
||||
|[15:8]|pmp[i*4 + 1]cfg|0x00|0xFF|RW|pmp configuration bits|
|
||||
|[23:16]|pmp[i*4 + 2]cfg|0x00|0xFF|RW|pmp configuration bits|
|
||||
|[31:24]|pmp[i*4 + 3]cfg|0x00|0xFF|RW|pmp configuration bits|
|
||||
|
||||
#### pmpaddr[0-63]
|
||||
|
||||
---
|
||||
**Address** 0x3b0-0x3ef
|
||||
**Reset Value**0x20
|
||||
**Priviliege mode** M
|
||||
**Description** Physical memory protection address register
|
||||
|Bits|Field name|legal values|Mask|Access|Description|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|[31:0]|pmpaddr[i]|0x00000000|0xFFFFFFFF|RW|Physical memory protection address register|
|
||||
|
||||
#### mcycle
|
||||
|
||||
---
|
||||
**Address** 0xb00
|
||||
**Reset Value**0x0
|
||||
**Priviliege mode** M
|
||||
**Description** Counts the number of clock cycles executed from an arbitrary point in time.
|
||||
|Bits|Field name|legal values|Mask|Access|Description|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|[31:0]|mcycle|0x00000000|0xFFFFFFFF|RW|Counts the number of clock cycles executed from an arbitrary point in time.|
|
||||
|
||||
#### minstret
|
||||
|
||||
---
|
||||
**Address** 0xb02
|
||||
**Reset Value**0x0
|
||||
**Priviliege mode** M
|
||||
**Description** Counts the number of instructions completed from an arbitrary point in time.
|
||||
|Bits|Field name|legal values|Mask|Access|Description|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|[31:0]|minstret|0x00000000|0xFFFFFFFF|RW|Counts the number of instructions completed from an arbitrary point in time.|
|
||||
|
||||
#### mhpmcounter[3-31]
|
||||
|
||||
---
|
||||
**Address** 0xb03-0xb1f
|
||||
**Reset Value**0x0
|
||||
**Priviliege mode** M
|
||||
**Description** The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode.
|
||||
|Bits|Field name|legal values|Mask|Access|Description|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|[31:0]|mhpmcounter[i]|0x00000000|0xFFFFFFFF|RW|The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode.|
|
||||
|
||||
#### mcycleh
|
||||
|
||||
---
|
||||
**Address** 0xb80
|
||||
**Reset Value**0x0
|
||||
**Priviliege mode** M
|
||||
**Description** upper 32 bits of mcycle
|
||||
|Bits|Field name|legal values|Mask|Access|Description|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|[31:0]|mcycleh|0x00000000|0xFFFFFFFF|RW|upper 32 bits of mcycle|
|
||||
|
||||
#### minstreth
|
||||
|
||||
---
|
||||
**Address** 0xb82
|
||||
**Reset Value**0x0
|
||||
**Priviliege mode** M
|
||||
**Description** Upper 32 bits of minstret.
|
||||
|Bits|Field name|legal values|Mask|Access|Description|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|[31:0]|minstreth|0x00000000|0xFFFFFFFF|RW|Upper 32 bits of minstret.|
|
||||
|
||||
#### mhpmcounter[3-31]h
|
||||
|
||||
---
|
||||
**Address** 0xb83-0xb9f
|
||||
**Reset Value**0x0
|
||||
**Priviliege mode** M
|
||||
**Description** The mhpmcounterh returns the upper half word in RV32I systems.
|
||||
|Bits|Field name|legal values|Mask|Access|Description|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|[31:0]|mhpmcounter[i]h|0x00000000|0xFFFFFFFF|RW|The mhpmcounterh returns the upper half word in RV32I systems.|
|
||||
|
||||
#### mvendorid
|
||||
|
||||
---
|
||||
**Address** 0xf11
|
||||
**Reset Value**0xdeadbeef
|
||||
**Priviliege mode** M
|
||||
**Description** 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core.
|
||||
|Bits|Field name|legal values|Mask|Access|Description|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|[31:0]|mvendorid|0xdeadbeef|0|RW|32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core.|
|
||||
|
||||
#### marchid
|
||||
|
||||
---
|
||||
**Address** 0xf12
|
||||
**Reset Value**0x0
|
||||
**Priviliege mode** M
|
||||
**Description** MXLEN-bit read-only register encoding the base microarchitecture of the hart.
|
||||
|Bits|Field name|legal values|Mask|Access|Description|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|[31:0]|marchid|0x0|0|RW|MXLEN-bit read-only register encoding the base microarchitecture of the hart.|
|
||||
|
||||
#### mimpid
|
||||
|
||||
---
|
||||
**Address** 0xf13
|
||||
**Reset Value**0x0
|
||||
**Priviliege mode** M
|
||||
**Description** Provides a unique encoding of the version of the processor implementation.
|
||||
|Bits|Field name|legal values|Mask|Access|Description|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|[31:0]|mimpid|0x0|0|RW|Provides a unique encoding of the version of the processor implementation.|
|
||||
|
||||
#### mhartid
|
||||
|
||||
---
|
||||
**Address** 0xf14
|
||||
**Reset Value**0x0
|
||||
**Priviliege mode** M
|
||||
**Description** MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.
|
||||
|Bits|Field name|legal values|Mask|Access|Description|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|[31:0]|mhartid|0x0|0|RW|MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.|
|
||||
536
config/gen_from_riscv_config/cv32a65x/csr/csr.rst
Normal file
536
config/gen_from_riscv_config/cv32a65x/csr/csr.rst
Normal file
|
|
@ -0,0 +1,536 @@
|
|||
.. ..::
|
||||
|
||||
Copyright (c) 2024 OpenHW Group
|
||||
Copyright (c) 2024 Thales
|
||||
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
Author: Abdessamii Oukalrazqou
|
||||
|
||||
===
|
||||
csr
|
||||
===
|
||||
|
||||
Register Summary
|
||||
----------------
|
||||
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| Address | Register Name | Description |
|
||||
+=============+====================+============================================================================================================================+
|
||||
| 0x300 | mstatus | The mstatus register keeps track of and controls the hart’s current operating state. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0x300 | mstatush | The mstatush register keeps track of and controls the hart’s current operating state. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0x301 | misa | misa is a read-write register reporting the ISA supported by the hart. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0x304 | mie | The mie register is an MXLEN-bit read/write register containing interrupt enable bits. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0x305 | mtvec | MXLEN-bit read/write register that holds trap vector configuration. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0x320 | mcountinhibit | The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0x323-0x33f | mhpmevent[3-31] | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0x340 | mscratch | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0x341 | mepc | The mepc is a warl register that must be able to hold all valid physical and virtual addresses. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0x342 | mcause | The mcause register stores the information regarding the trap. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0x343 | mtval | The mtval is a warl register that holds the address of the instruction which caused the exception. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0x344 | mip | The mip register is an MXLEN-bit read/write register containing information on pending interrupts. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0x3a0-0x3af | pmpcfg[0-15] | PMP configuration register |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0x3b0-0x3ef | pmpaddr[0-63] | Physical memory protection address register |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0xb00 | mcycle | Counts the number of clock cycles executed from an arbitrary point in time. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0xb02 | minstret | Counts the number of instructions completed from an arbitrary point in time. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0xb03-0xb1f | mhpmcounter[3-31] | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0xb80 | mcycleh | upper 32 bits of mcycle |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0xb82 | minstreth | Upper 32 bits of minstret. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0xb83-0xb9f | mhpmcounter[3-31]h | The mhpmcounterh returns the upper half word in RV32I systems. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0xf11 | mvendorid | 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0xf12 | marchid | MXLEN-bit read-only register encoding the base microarchitecture of the hart. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0xf13 | mimpid | Provides a unique encoding of the version of the processor implementation. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| 0xf14 | mhartid | MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. |
|
||||
+-------------+--------------------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
Register Description
|
||||
--------------------
|
||||
mstatus
|
||||
-------
|
||||
|
||||
:Address: 0x300
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: The mstatus register keeps track of and controls the
|
||||
hart’s current operating state.
|
||||
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+=========+==============+===============+========+==========+=================================================================================================================+
|
||||
| 0 | uie | | | RW | Stores the state of the user mode interrupts. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| 1 | sie | | | RW | Stores the state of the supervisor mode interrupts. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| 3 | mie | 0 | 1 | RW | Stores the state of the machine mode interrupts. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| 4 | upie | | | RW | Stores the state of the user mode interrupts prior to the trap. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| 5 | spie | | | RW | Stores the state of the supervisor mode interrupts prior to the trap. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| 7 | mpie | 0 | 1 | RW | Stores the state of the machine mode interrupts prior to the trap. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| 8 | spp | | | RW | Stores the previous priority mode for supervisor. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| [12:11] | mpp | 0x0 | 0x3 | RW | Stores the previous priority mode for machine. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| [14:13] | fs | | | RW | Encodes the status of the floating-point unit, including the CSR fcsr and floating-point data registers. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| [16:15] | xs | 0x1 | 0 | RW | Encodes the status of additional user-mode extensions and associated state. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| 17 | mprv | | | RW | Modifies the privilege level at which loads and stores execute in all privilege modes. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| 18 | sum | | | RW | Modifies the privilege with which S-mode loads and stores access virtual memory. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| 19 | mxr | | | RW | Modifies the privilege with which loads access virtual memory. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| 20 | tvm | | | RW | Supports intercepting supervisor virtual-memory management operations. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| 21 | tw | | | RW | Supports intercepting the WFI instruction. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| 22 | tsr | | | RW | Supports intercepting the supervisor exception return instruction. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| 23 | spelp | | | RW | Supervisor mode previous expected-landing-pad (ELP) state. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| 31 | sd | | | RW | Read-only bit that summarizes whether either the FS field or XS field signals the presence of some dirty state. |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
| [30:24] | Reserved_24 | | | Reserved | Reserved |
|
||||
+---------+--------------+---------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
mstatush
|
||||
--------
|
||||
|
||||
:Address: 0x300
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: The mstatush register keeps track of and controls the
|
||||
hart’s current operating state.
|
||||
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------------------------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+=========+==============+===============+========+==========+==============================================================================================+
|
||||
| 4 | sbe | | | RW | control the endianness of memory accesses other than instruction fetches for supervisor mode |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------------------------------------------------------------+
|
||||
| 5 | mbe | | | RW | control the endianness of memory accesses other than instruction fetches for machine mode |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------------------------------------------------------------+
|
||||
| 6 | gva | | | RW | Stores the state of the supervisor mode interrupts. |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------------------------------------------------------------+
|
||||
| 7 | mpv | | | RW | Stores the state of the user mode interrupts. |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------------------------------------------------------------+
|
||||
| 9 | mpelp | | | RW | Machine mode previous expected-landing-pad (ELP) state. |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------------------------------------------------------------+
|
||||
| [31:10] | Reserved_10 | | | Reserved | Reserved |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------------------------------------------------------------+
|
||||
|
||||
misa
|
||||
----
|
||||
|
||||
:Address: 0x301
|
||||
:Reset Value: 0x40001104
|
||||
:priviliege mode: M
|
||||
:Description: misa is a read-write register reporting the ISA supported
|
||||
by the hart.
|
||||
|
||||
+---------+--------------+---------------+-----------+----------+------------------------------------------------------------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+=========+==============+===============+===========+==========+================================================================================================+
|
||||
| [25:0] | extensions | 0x0000000 | 0x3FFFFFF | RW | Encodes the presence of the standard extensions, with a single bit per letter of the alphabet. |
|
||||
+---------+--------------+---------------+-----------+----------+------------------------------------------------------------------------------------------------+
|
||||
| [31:30] | mxl | 0 | 1 | RW | Encodes the native base integer ISA width. |
|
||||
+---------+--------------+---------------+-----------+----------+------------------------------------------------------------------------------------------------+
|
||||
| [29:26] | Reserved_26 | | | Reserved | Reserved |
|
||||
+---------+--------------+---------------+-----------+----------+------------------------------------------------------------------------------------------------+
|
||||
|
||||
mie
|
||||
---
|
||||
|
||||
:Address: 0x304
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: The mie register is an MXLEN-bit read/write register
|
||||
containing interrupt enable bits.
|
||||
|
||||
+---------+--------------+---------------+--------+----------+---------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+=========+==============+===============+========+==========+=======================================+
|
||||
| 0 | usie | | | RW | User Software Interrupt enable. |
|
||||
+---------+--------------+---------------+--------+----------+---------------------------------------+
|
||||
| 1 | ssie | | | RW | Supervisor Software Interrupt enable. |
|
||||
+---------+--------------+---------------+--------+----------+---------------------------------------+
|
||||
| 2 | vssie | | | RW | VS-level Software Interrupt enable. |
|
||||
+---------+--------------+---------------+--------+----------+---------------------------------------+
|
||||
| 3 | msie | 0x0 | 0x1 | RW | Machine Software Interrupt enable. |
|
||||
+---------+--------------+---------------+--------+----------+---------------------------------------+
|
||||
| 4 | utie | | | RW | User Timer Interrupt enable. |
|
||||
+---------+--------------+---------------+--------+----------+---------------------------------------+
|
||||
| 5 | stie | | | RW | Supervisor Timer Interrupt enable. |
|
||||
+---------+--------------+---------------+--------+----------+---------------------------------------+
|
||||
| 6 | vstie | | | RW | VS-level Timer Interrupt enable. |
|
||||
+---------+--------------+---------------+--------+----------+---------------------------------------+
|
||||
| 7 | mtie | 0 | 1 | RW | Machine Timer Interrupt enable. |
|
||||
+---------+--------------+---------------+--------+----------+---------------------------------------+
|
||||
| 8 | ueie | | | RW | User External Interrupt enable. |
|
||||
+---------+--------------+---------------+--------+----------+---------------------------------------+
|
||||
| 9 | seie | | | RW | Supervisor External Interrupt enable. |
|
||||
+---------+--------------+---------------+--------+----------+---------------------------------------+
|
||||
| 10 | vseie | | | RW | VS-level External Interrupt enable. |
|
||||
+---------+--------------+---------------+--------+----------+---------------------------------------+
|
||||
| 11 | meie | 0 | 1 | RW | Machine External Interrupt enable. |
|
||||
+---------+--------------+---------------+--------+----------+---------------------------------------+
|
||||
| 12 | sgeie | | | RW | HS-level External Interrupt enable. |
|
||||
+---------+--------------+---------------+--------+----------+---------------------------------------+
|
||||
| [31:13] | Reserved_13 | | | Reserved | Reserved |
|
||||
+---------+--------------+---------------+--------+----------+---------------------------------------+
|
||||
|
||||
mtvec
|
||||
-----
|
||||
|
||||
:Address: 0x305
|
||||
:Reset Value: 0x80010000
|
||||
:priviliege mode: M
|
||||
:Description: MXLEN-bit read/write register that holds trap vector
|
||||
configuration.
|
||||
|
||||
+--------+--------------+---------------+------------+----------+----------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+==============+===============+============+==========+======================+
|
||||
| [1:0] | mode | 0x0 | 0x1 | RW | Vector mode. |
|
||||
+--------+--------------+---------------+------------+----------+----------------------+
|
||||
| [31:2] | base | 0x3FFFFFFF | 0x00000000 | RW | Vector base address. |
|
||||
+--------+--------------+---------------+------------+----------+----------------------+
|
||||
|
||||
mcountinhibit
|
||||
-------------
|
||||
|
||||
:Address: 0x320
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: The mcountinhibit is a 32-bit WARL register that controls
|
||||
which of the hardware performance-monitoring counters increment.
|
||||
|
||||
+--------+---------------+---------------+------------+----------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+===============+===============+============+==========+============================================================================================================================+
|
||||
| [31:0] | mcountinhibit | 0x00000000 | 0xFFFFFFFF | RW | The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment. |
|
||||
+--------+---------------+---------------+------------+----------+----------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
mhpmevent[3-31]
|
||||
---------------
|
||||
|
||||
:Address: 0x323-0x33f
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: The mhpmevent is a MXLEN-bit event register which controls
|
||||
mhpmcounter3.
|
||||
|
||||
+--------+--------------+---------------+------------+----------+--------------------------------------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+==============+===============+============+==========+==========================================================================+
|
||||
| [31:0] | mhpmevent[i] | 0x00000000 | 0xFFFFFFFF | RW | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3. |
|
||||
+--------+--------------+---------------+------------+----------+--------------------------------------------------------------------------+
|
||||
|
||||
mscratch
|
||||
--------
|
||||
|
||||
:Address: 0x340
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: The mscratch register is an MXLEN-bit read/write register
|
||||
dedicated for use by machine mode.
|
||||
|
||||
+--------+--------------+---------------+------------+----------+----------------------------------------------------------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+==============+===============+============+==========+==============================================================================================+
|
||||
| [31:0] | mscratch | 0x00000000 | 0xFFFFFFFF | RW | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. |
|
||||
+--------+--------------+---------------+------------+----------+----------------------------------------------------------------------------------------------+
|
||||
|
||||
mepc
|
||||
----
|
||||
|
||||
:Address: 0x341
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: The mepc is a warl register that must be able to hold all
|
||||
valid physical and virtual addresses.
|
||||
|
||||
+--------+--------------+---------------+------------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+==============+===============+============+==========+=================================================================================================+
|
||||
| [31:0] | mepc | 0x00000000 | 0xFFFFFFFF | RW | The mepc is a warl register that must be able to hold all valid physical and virtual addresses. |
|
||||
+--------+--------------+---------------+------------+----------+-------------------------------------------------------------------------------------------------+
|
||||
|
||||
mcause
|
||||
------
|
||||
|
||||
:Address: 0x342
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: The mcause register stores the information regarding the
|
||||
trap.
|
||||
|
||||
+--------+----------------+---------------+--------+----------+-----------------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+================+===============+========+==========+=====================================================+
|
||||
| [30:0] | exception_code | 0 | 15 | RW | Encodes the exception code. |
|
||||
+--------+----------------+---------------+--------+----------+-----------------------------------------------------+
|
||||
| 31 | interrupt | 0x0 | 0x1 | RW | Indicates whether the trap was due to an interrupt. |
|
||||
+--------+----------------+---------------+--------+----------+-----------------------------------------------------+
|
||||
|
||||
mtval
|
||||
-----
|
||||
|
||||
:Address: 0x343
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: The mtval is a warl register that holds the address of the
|
||||
instruction which caused the exception.
|
||||
|
||||
+--------+--------------+---------------+------------+----------+----------------------------------------------------------------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+==============+===============+============+==========+====================================================================================================+
|
||||
| [31:0] | mtval | 0x00000000 | 0xFFFFFFFF | RW | The mtval is a warl register that holds the address of the instruction which caused the exception. |
|
||||
+--------+--------------+---------------+------------+----------+----------------------------------------------------------------------------------------------------+
|
||||
|
||||
mip
|
||||
---
|
||||
|
||||
:Address: 0x344
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: The mip register is an MXLEN-bit read/write register
|
||||
containing information on pending interrupts.
|
||||
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+=========+==============+===============+========+==========+========================================+
|
||||
| 0 | usip | | | RW | User Software Interrupt Pending. |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------+
|
||||
| 1 | ssip | | | RW | Supervisor Software Interrupt Pending. |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------+
|
||||
| 2 | vssip | | | RW | VS-level Software Interrupt Pending. |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------+
|
||||
| 3 | msip | 0x1 | 0 | RW | Machine Software Interrupt Pending. |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------+
|
||||
| 4 | utip | | | RW | User Timer Interrupt Pending. |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------+
|
||||
| 5 | stip | | | RW | Supervisor Timer Interrupt Pending. |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------+
|
||||
| 6 | vstip | | | RW | VS-level Timer Interrupt Pending. |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------+
|
||||
| 7 | mtip | 0x1 | 0 | RW | Machine Timer Interrupt Pending. |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------+
|
||||
| 8 | ueip | | | RW | User External Interrupt Pending. |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------+
|
||||
| 9 | seip | | | RW | Supervisor External Interrupt Pending. |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------+
|
||||
| 10 | vseip | | | RW | VS-level External Interrupt Pending. |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------+
|
||||
| 11 | meip | 0x1 | 0 | RW | Machine External Interrupt Pending. |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------+
|
||||
| 12 | sgeip | | | RW | HS-level External Interrupt Pending. |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------+
|
||||
| [31:13] | Reserved_13 | | | Reserved | Reserved |
|
||||
+---------+--------------+---------------+--------+----------+----------------------------------------+
|
||||
|
||||
pmpcfg[0-15]
|
||||
------------
|
||||
|
||||
:Address: 0x3a0-0x3af
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: PMP configuration register
|
||||
|
||||
+---------+-----------------+---------------+--------+----------+------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+=========+=================+===============+========+==========+========================+
|
||||
| [7:0] | pmp[i*4 + 0]cfg | 0x00 | 0xFF | RW | pmp configuration bits |
|
||||
+---------+-----------------+---------------+--------+----------+------------------------+
|
||||
| [15:8] | pmp[i*4 + 1]cfg | 0x00 | 0xFF | RW | pmp configuration bits |
|
||||
+---------+-----------------+---------------+--------+----------+------------------------+
|
||||
| [23:16] | pmp[i*4 + 2]cfg | 0x00 | 0xFF | RW | pmp configuration bits |
|
||||
+---------+-----------------+---------------+--------+----------+------------------------+
|
||||
| [31:24] | pmp[i*4 + 3]cfg | 0x00 | 0xFF | RW | pmp configuration bits |
|
||||
+---------+-----------------+---------------+--------+----------+------------------------+
|
||||
|
||||
pmpaddr[0-63]
|
||||
-------------
|
||||
|
||||
:Address: 0x3b0-0x3ef
|
||||
:Reset Value: 0x00000020
|
||||
:priviliege mode: M
|
||||
:Description: Physical memory protection address register
|
||||
|
||||
+--------+--------------+---------------+------------+----------+---------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+==============+===============+============+==========+=============================================+
|
||||
| [31:0] | pmpaddr[i] | 0x00000000 | 0xFFFFFFFF | RW | Physical memory protection address register |
|
||||
+--------+--------------+---------------+------------+----------+---------------------------------------------+
|
||||
|
||||
mcycle
|
||||
------
|
||||
|
||||
:Address: 0xb00
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: Counts the number of clock cycles executed from an
|
||||
arbitrary point in time.
|
||||
|
||||
+--------+--------------+---------------+------------+----------+-----------------------------------------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+==============+===============+============+==========+=============================================================================+
|
||||
| [31:0] | mcycle | 0x00000000 | 0xFFFFFFFF | RW | Counts the number of clock cycles executed from an arbitrary point in time. |
|
||||
+--------+--------------+---------------+------------+----------+-----------------------------------------------------------------------------+
|
||||
|
||||
minstret
|
||||
--------
|
||||
|
||||
:Address: 0xb02
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: Counts the number of instructions completed from an
|
||||
arbitrary point in time.
|
||||
|
||||
+--------+--------------+---------------+------------+----------+------------------------------------------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+==============+===============+============+==========+==============================================================================+
|
||||
| [31:0] | minstret | 0x00000000 | 0xFFFFFFFF | RW | Counts the number of instructions completed from an arbitrary point in time. |
|
||||
+--------+--------------+---------------+------------+----------+------------------------------------------------------------------------------+
|
||||
|
||||
mhpmcounter[3-31]
|
||||
-----------------
|
||||
|
||||
:Address: 0xb03-0xb1f
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: The mhpmcounter is a 64-bit counter. Returns lower 32 bits
|
||||
in RV32I mode.
|
||||
|
||||
+--------+----------------+---------------+------------+----------+---------------------------------------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+================+===============+============+==========+===========================================================================+
|
||||
| [31:0] | mhpmcounter[i] | 0x00000000 | 0xFFFFFFFF | RW | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode. |
|
||||
+--------+----------------+---------------+------------+----------+---------------------------------------------------------------------------+
|
||||
|
||||
mcycleh
|
||||
-------
|
||||
|
||||
:Address: 0xb80
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: upper 32 bits of mcycle
|
||||
|
||||
+--------+--------------+---------------+------------+----------+-------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+==============+===============+============+==========+=========================+
|
||||
| [31:0] | mcycleh | 0x00000000 | 0xFFFFFFFF | RW | upper 32 bits of mcycle |
|
||||
+--------+--------------+---------------+------------+----------+-------------------------+
|
||||
|
||||
minstreth
|
||||
---------
|
||||
|
||||
:Address: 0xb82
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: Upper 32 bits of minstret.
|
||||
|
||||
+--------+--------------+---------------+------------+----------+----------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+==============+===============+============+==========+============================+
|
||||
| [31:0] | minstreth | 0x00000000 | 0xFFFFFFFF | RW | Upper 32 bits of minstret. |
|
||||
+--------+--------------+---------------+------------+----------+----------------------------+
|
||||
|
||||
mhpmcounter[3-31]h
|
||||
------------------
|
||||
|
||||
:Address: 0xb83-0xb9f
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: The mhpmcounterh returns the upper half word in RV32I
|
||||
systems.
|
||||
|
||||
+--------+-----------------+---------------+------------+----------+----------------------------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+=================+===============+============+==========+================================================================+
|
||||
| [31:0] | mhpmcounter[i]h | 0x00000000 | 0xFFFFFFFF | RW | The mhpmcounterh returns the upper half word in RV32I systems. |
|
||||
+--------+-----------------+---------------+------------+----------+----------------------------------------------------------------+
|
||||
|
||||
mvendorid
|
||||
---------
|
||||
|
||||
:Address: 0xf11
|
||||
:Reset Value: 0xdeadbeef
|
||||
:priviliege mode: M
|
||||
:Description: 32-bit read-only register providing the JEDEC manufacturer
|
||||
ID of the provider of the core.
|
||||
|
||||
+--------+--------------+---------------+--------+----------+--------------------------------------------------------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+==============+===============+========+==========+============================================================================================+
|
||||
| [31:0] | mvendorid | 0xdeadbeef | 0 | RW | 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. |
|
||||
+--------+--------------+---------------+--------+----------+--------------------------------------------------------------------------------------------+
|
||||
|
||||
marchid
|
||||
-------
|
||||
|
||||
:Address: 0xf12
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: MXLEN-bit read-only register encoding the base
|
||||
microarchitecture of the hart.
|
||||
|
||||
+--------+--------------+---------------+--------+----------+-------------------------------------------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+==============+===============+========+==========+===============================================================================+
|
||||
| [31:0] | marchid | 0x0 | 0 | RW | MXLEN-bit read-only register encoding the base microarchitecture of the hart. |
|
||||
+--------+--------------+---------------+--------+----------+-------------------------------------------------------------------------------+
|
||||
|
||||
mimpid
|
||||
------
|
||||
|
||||
:Address: 0xf13
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: Provides a unique encoding of the version of the processor
|
||||
implementation.
|
||||
|
||||
+--------+--------------+---------------+--------+----------+----------------------------------------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+==============+===============+========+==========+============================================================================+
|
||||
| [31:0] | mimpid | 0x0 | 0 | RW | Provides a unique encoding of the version of the processor implementation. |
|
||||
+--------+--------------+---------------+--------+----------+----------------------------------------------------------------------------+
|
||||
|
||||
mhartid
|
||||
-------
|
||||
|
||||
:Address: 0xf14
|
||||
:Reset Value: 0x00000000
|
||||
:priviliege mode: M
|
||||
:Description: MXLEN-bit read-only register containing the integer ID of
|
||||
the hardware thread running the code.
|
||||
|
||||
+--------+--------------+---------------+--------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| Bits | Field name | Legalvalues | Mask | Access | Description |
|
||||
+========+==============+===============+========+==========+=================================================================================================+
|
||||
| [31:0] | mhartid | 0x0 | 0 | RW | MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. |
|
||||
+--------+--------------+---------------+--------+----------+-------------------------------------------------------------------------------------------------+
|
||||
|
||||
126
config/gen_from_riscv_config/cv32a65x/isa/isa.md
Normal file
126
config/gen_from_riscv_config/cv32a65x/isa/isa.md
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
<!--Copyright (c) 2024 OpenHW Group
|
||||
Copyright (c) 2024 Thales
|
||||
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
Author: Abdessamii Oukalrazqou
|
||||
-->
|
||||
|
||||
# isa
|
||||
|
||||
|
||||
|
||||
## Instructions
|
||||
|
||||
|Subset Name|Name |Description|
|
||||
| :--- | :--- | :--- |
|
||||
|I|[RV32I Base Integer Instructions](#RV32I Base Integer Instructions)|the base integer instruction set, also known as the 'RV32I' or 'RV64I' instruction set , depending on the address space size, provides the core functionality required for general-purpose computing . it includes instructions for arithmetic, logical, and control operations, as well as memory access and manipulation |
|
||||
|M|[RV32M Multiplication and Division Instructions](#RV32M Multiplication and Division Instructions)|the standard integer multiplication and division instruction extension, which is named “M” and contains instructions that multiply or divide values held in two integer registers. |
|
||||
|C|[RV32C Compressed Instructions](#RV32C Compressed Instructions)|RVC uses a simple compression scheme that offers shorter 16-bit versions of common 32-bit RISC-V instructions when: the immediate or address offset is small; one of the registers is the zero register (x0), the ABI link register (x1), or the ABI stack pointer (x2); the destination register and the first source register are identical; the registers used are the 8 most popular ones. The C extension is compatible with all other standard instruction extensions. The C extension allows 16-bit instructions to be freely intermixed with 32-bit instructions, with the latter now able to start on any 16-bit boundary. With the addition of the C extension, JAL and JALR instructions will no longer raise an instruction misaligned exception |
|
||||
|Zicsr|[RV32Zicsr Control and Status Register Instructions](#RV32Zicsr Control and Status Register Instructions)|All CSR instructions atomically read-modify-write a single CSR, whose CSR specifier is encoded in the 12-bit csr field of the instruction held in bits 31–20. The immediate forms use a 5-bit zero-extended immediate encoded in the rs1 field. |
|
||||
|Zifencei|[RVZifencei Instruction Fetch Fence](#RVZifencei Instruction Fetch Fence)|FENCE.I instruction that provides explicit synchronization between writes to instruction memory and instruction fetches on the same hart. Currently, this instruction is the only standard mechanism to ensure that stores visible to a hart will also be visible to it instruction fetches. |
|
||||
|Zicntr|[Zicntr](#Zicntr)|No info found yet for extension Zicntr|
|
||||
|
||||
### RV32I Base Integer Instructions
|
||||
|
||||
|Name|Format|Pseudocode|Invalid_values|Exception_raised|Description|Op Name|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|ADDI |[addi rd, rs1, imm[11:0]](#addi rd, rs1, imm[11:0])|x[rd] = x[rs1] + sext(imm[11:0])|NONE|NONE |add sign-extended 12-bit immediate to register rs1, and store the result in register rd.|Integer_Register_Immediate_Operations|
|
||||
|ANDI |[andi rd, rs1, imm[11:0]](#andi rd, rs1, imm[11:0])|x[rd] = x[rs1] & sext(imm[11:0])|NONE|NONE |perform bitwise AND on register rs1 and the sign-extended 12-bit immediate and place the result in rd.|Integer_Register_Immediate_Operations|
|
||||
|ORI |[ori rd, rs1, imm[11:0]](#ori rd, rs1, imm[11:0])|x[rd] = x[rs1] \| sext(imm[11:0])|NONE|NONE |perform bitwise OR on register rs1 and the sign-extended 12-bit immediate and place the result in rd.|Integer_Register_Immediate_Operations|
|
||||
|XORI |[xori rd, rs1, imm[11:0]](#xori rd, rs1, imm[11:0])|x[rd] = x[rs1] ^ sext(imm[11:0])|NONE|NONE |perform bitwise XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd.|Integer_Register_Immediate_Operations|
|
||||
|SLTI |[slti rd, rs1, imm[11:0]](#slti rd, rs1, imm[11:0])|if (x[rs1] < sext(imm[11:0])) x[rd] = 1 else x[rd] = 0|NONE|NONE |set register rd to 1 if register rs1 is less than the sign extended immediate when both are treated as signed numbers, else 0 is written to rd.|Integer_Register_Immediate_Operations|
|
||||
|SLTIU |[sltiu rd, rs1, imm[11:0]](#sltiu rd, rs1, imm[11:0])|if (x[rs1] <u sext(imm[11:0])) x[rd] = 1 else x[rd] = 0|NONE|NONE |set register rd to 1 if register rs1 is less than the sign extended immediate when both are treated as unsigned numbers, else 0 is written to rd."|Integer_Register_Immediate_Operations|
|
||||
|SLLI |[slli rd, rs1, imm[4:0]](#slli rd, rs1, imm[4:0])|x[rd] = x[rs1] << imm[4:0]|NONE|NONE |logical left shift (zeros are shifted into the lower bits).|Integer_Register_Immediate_Operations|
|
||||
|SRLI |[srli rd, rs1, imm[4:0]](#srli rd, rs1, imm[4:0])|x[rd] = x[rs1] >> imm[4:0]|NONE|NONE |logical right shift (zeros are shifted into the upper bits).|Integer_Register_Immediate_Operations|
|
||||
|SRAI |[srai rd, rs1, imm[4:0]](#srai rd, rs1, imm[4:0])|x[rd] = x[rs1] >>s imm[4:0]|NONE|NONE |arithmetic right shift (the original sign bit is copied into the vacated upper bits).|Integer_Register_Immediate_Operations|
|
||||
|LUI |[lui rd, imm[19:0]](#lui rd, imm[19:0])|x[rd] = sext(imm[31:12] << 12)|NONE|NONE |place the immediate value in the top 20 bits of the destination register rd, filling in the lowest 12 bits with zeros.|Integer_Register_Immediate_Operations|
|
||||
|AUIPC |[auipc rd, imm[19:0]](#auipc rd, imm[19:0])|x[rd] = pc + sext(immediate[31:12] << 12)|NONE|NONE |form a 32-bit offset from the 20-bit immediate, filling in the lowest 12 bits with zeros, adds this offset to the pc, then place the result in register rd.|Integer_Register_Immediate_Operations|
|
||||
|ADD |[add rd, rs1, rs2](#add rd, rs1, rs2)|x[rd] = x[rs1] + x[rs2]|NONE|NONE |add rs2 to register rs1, and store the result in register rd.|Integer_Register_Register_Operations|
|
||||
|SUB |[sub rd, rs1, rs2](#sub rd, rs1, rs2)|x[rd] = x[rs1] - x[rs2]|NONE|NONE |subtract rs2 from register rs1, and store the result in register rd.|Integer_Register_Register_Operations|
|
||||
|AND |[and rd, rs1, rs2](#and rd, rs1, rs2)|x[rd] = x[rs1] & x[rs2]|NONE|NONE |perform bitwise AND on register rs1 and rs2 and place the result in rd.|Integer_Register_Register_Operations|
|
||||
|OR |[or rd, rs1, rs2](#or rd, rs1, rs2)|x[rd] = x[rs1] \| x[rs2]|NONE|NONE |perform bitwise OR on register rs1 and rs2 and place the result in rd.|Integer_Register_Register_Operations|
|
||||
|XOR |[xor rd, rs1, rs2](#xor rd, rs1, rs2)|x[rd] = x[rs1] ^ x[rs2]|NONE|NONE |perform bitwise XOR on register rs1 and rs2 and place the result in rd.|Integer_Register_Register_Operations|
|
||||
|SLT |[slt rd, rs1, rs2](#slt rd, rs1, rs2)|if (x[rs1] < x[rs2]) x[rd] = 1 else x[rd] = 0|NONE|NONE |set register rd to 1 if register rs1 is less than rs2 when both are treated as signed numbers, else 0 is written to rd.|Integer_Register_Register_Operations|
|
||||
|SLTU |[sltu rd, rs1, rs2](#sltu rd, rs1, rs2)|if (x[rs1] <u x[rs2]) x[rd] = 1 else x[rd] = 0|NONE|NONE |set register rd to 1 if register rs1 is less than rs2 when both are treated as unsigned numbers, else 0 is written to rd.|Integer_Register_Register_Operations|
|
||||
|SLL |[sll rd, rs1, rs2](#sll rd, rs1, rs2)|x[rd] = x[rs1] << x[rs2]|NONE|NONE |logical left shift (zeros are shifted into the lower bits).|Integer_Register_Register_Operations|
|
||||
|SRL |[srl rd, rs1, rs2](#srl rd, rs1, rs2)|x[rd] = x[rs1] >> x[rs2]|NONE|NONE |logical right shift (zeros are shifted into the upper bits).|Integer_Register_Register_Operations|
|
||||
|SRA |[sra rd, rs1, rs2](#sra rd, rs1, rs2)|x[rd] = x[rs1] >>s x[rs2]|NONE|NONE |arithmetic right shift (the original sign bit is copied into the vacated upper bits).|Integer_Register_Register_Operations|
|
||||
|JAL |[jal rd, imm[20:1]](#jal rd, imm[20:1])|x[rd] = pc+4; pc += sext(imm[20:1])|NONE|jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception.|offset is sign-extended and added to the pc to form the jump target address (pc is calculated using signed arithmetic), then setting the least-significant bit of the result to zero, and store the address of instruction following the jump (pc+4) into register rd.|Control_Transfer_Operations-Unconditional_Jumps|
|
||||
|JALR |[jalr rd, rs1, imm[11:0]](#jalr rd, rs1, imm[11:0])|t = pc+4; pc = (x[rs1]+sext(imm[11:0]))&∼1 ; x[rd] = t|NONE|jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception.|target address is obtained by adding the 12-bit signed immediate to the register rs1 (pc is calculated using signed arithmetic), then setting the least-significant bit of the result to zero, and store the address of instruction following the jump (pc+4) into register rd.|Control_Transfer_Operations-Unconditional_Jumps|
|
||||
|BEQ |[beq rs1, rs2, imm[12:1]](#beq rs1, rs2, imm[12:1])|if (x[rs1] == x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4|NONE|no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions.|takes the branch (pc is calculated using signed arithmetic) if registers rs1 and rs2 are equal.|Control_Transfer_Operations-Conditional_Branches|
|
||||
|BNE |[bne rs1, rs2, imm[12:1]](#bne rs1, rs2, imm[12:1])|if (x[rs1] != x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4|NONE|no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions.|takes the branch (pc is calculated using signed arithmetic) if registers rs1 and rs2 are not equal.|Control_Transfer_Operations-Conditional_Branches|
|
||||
|BLT |[blt rs1, rs2, imm[12:1]](#blt rs1, rs2, imm[12:1])|if (x[rs1] < x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4|NONE|no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions.|takes the branch (pc is calculated using signed arithmetic) if registers rs1 less than rs2 (using signed comparison).|Control_Transfer_Operations-Conditional_Branches|
|
||||
|BLTU |[bltu rs1, rs2, imm[12:1]](#bltu rs1, rs2, imm[12:1])|if (x[rs1] <u x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4|NONE|no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions.|takes the branch (pc is calculated using signed arithmetic) if registers rs1 less than rs2 (using unsigned comparison).|Control_Transfer_Operations-Conditional_Branches|
|
||||
|BGE |[bge rs1, rs2, imm[12:1]](#bge rs1, rs2, imm[12:1])|if (x[rs1] >= x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4|NONE|no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions.|takes the branch (pc is calculated using signed arithmetic) if registers rs1 is greater than or equal rs2 (using signed comparison).|Control_Transfer_Operations-Conditional_Branches|
|
||||
|BGEU |[bgeu rs1, rs2, imm[12:1]](#bgeu rs1, rs2, imm[12:1])|if (x[rs1] >=u x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4|NONE|no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions.|takes the branch (pc is calculated using signed arithmetic) if registers rs1 is greater than or equal rs2 (using unsigned comparison).|Control_Transfer_Operations-Conditional_Branches|
|
||||
|LB |[lb rd, imm(rs1)](#lb rd, imm(rs1))|x[rd] = sext(M[x[rs1] + sext(imm[11:0])][7:0])|NONE|loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded.|loads a 8-bit value from memory, then sign-extends to 32-bit before storing in rd (rd is calculated using signed arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.|Load_and_Store_Instructions|
|
||||
|LH |[lh rd, imm(rs1)](#lh rd, imm(rs1))|x[rd] = sext(M[x[rs1] + sext(imm[11:0])][15:0])|NONE|loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (2-byte boundary).|loads a 16-bit value from memory, then sign-extends to 32-bit before storing in rd (rd is calculated using signed arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.|Load_and_Store_Instructions|
|
||||
|LW |[lw rd, imm(rs1)](#lw rd, imm(rs1))|x[rd] = sext(M[x[rs1] + sext(imm[11:0])][31:0])|NONE|loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (4-byte boundary).|loads a 32-bit value from memory, then storing in rd (rd is calculated using signed arithmetic). The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.|Load_and_Store_Instructions|
|
||||
|LBU |[lbu rd, imm(rs1)](#lbu rd, imm(rs1))|x[rd] = zext(M[x[rs1] + sext(imm[11:0])][7:0])|NONE|loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded.|loads a 8-bit value from memory, then zero-extends to 32-bit before storing in rd (rd is calculated using unsigned arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.|Load_and_Store_Instructions|
|
||||
|LHU |[lhu rd, imm(rs1)](#lhu rd, imm(rs1))|x[rd] = zext(M[x[rs1] + sext(imm[11:0])][15:0])|NONE|loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (2-byte boundary).|loads a 16-bit value from memory, then zero-extends to 32-bit before storing in rd (rd is calculated using unsigned arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.|Load_and_Store_Instructions|
|
||||
|SB |[sb rs2, imm(rs1)](#sb rs2, imm(rs1))|M[x[rs1] + sext(imm[11:0])][7:0] = x[rs2][7:0]|NONE|NONE |stores a 8-bit value from the low bits of register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.|Load_and_Store_Instructions|
|
||||
|SH |[sh rs2, imm(rs1)](#sh rs2, imm(rs1))|M[x[rs1] + sext(imm[11:0])][15:0] = x[rs2][15:0]|NONE|an exception is raised if the memory address isn't aligned (2-byte boundary).|stores a 16-bit value from the low bits of register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.|Load_and_Store_Instructions|
|
||||
|SW |[sw rs2, imm(rs1)](#sw rs2, imm(rs1))|M[x[rs1] + sext(imm[11:0])][31:0] = x[rs2][31:0]|NONE|an exception is raised if the memory address isn't aligned (4-byte boundary).|stores a 32-bit value from register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.|Load_and_Store_Instructions|
|
||||
|FENCE |[fence pre, succ](#fence pre, succ)|No operation (nop)|NONE|NONE |order device I/O and memory accesses as viewed by other RISC-V harts and external devices or coprocessors. Any combination of device input (I), device output (O), memory reads (R), and memory writes (W) may be ordered with respect to any combination of the same. Informally, no other RISC-V hart or external device can observe any operation in the successor set following a FENCE before any operation in the predecessor set preceding the FENCE, as the core support 1 hart, the fence instruction has no effect so we can considerate it as a nop instruction.|Memory_Ordering|
|
||||
|ECALL |[ecall](#ecall)|RaiseException(EnvironmentCall)|NONE|Raise an Environment Call exception. |make a request to the supporting execution environment, which is usually an operating system. The ABI for the system will define how parameters for the environment request are passed, but usually these will be in defined locations in the integer register file.|Environment_Call_and_Breakpoints|
|
||||
|EBREAK |[ebreak](#ebreak)|x[8 + rd'] = sext(x[8 + rd'][7:0])|NONE|NONE |This instruction takes a single source/destination operand. It sign-extends the least-significant byte in the operand by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support. |Environment_Call_and_Breakpoints|
|
||||
|
||||
### RV32M Multiplication and Division Instructions
|
||||
|
||||
|Name|Format|Pseudocode|Invalid_values|Exception_raised|Description|Op Name|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|MUL |[mul rd, rs1, rs2](#mul rd, rs1, rs2)|x[rd] = x[rs1] * x[rs2]|NONE|NONE |performs a 32-bit × 32-bit multiplication and places the lower 32 bits in the destination register (Both rs1 and rs2 treated as signed numbers).|Multiplication Operations|
|
||||
|MULH |[mulh rd, rs1, rs2](#mulh rd, rs1, rs2)|x[rd] = (x[rs1] s*s x[rs2]) >>s 32|NONE|NONE |performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (Both rs1 and rs2 treated as signed numbers).|Multiplication Operations|
|
||||
|MULHU |[mulhu rd, rs1, rs2](#mulhu rd, rs1, rs2)|x[rd] = (x[rs1] u*u x[rs2]) >>u 32|NONE|NONE |performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (Both rs1 and rs2 treated as unsigned numbers).|Multiplication Operations|
|
||||
|MULHSU |[mulhsu rd, rs1, rs2](#mulhsu rd, rs1, rs2)|x[rd] = (x[rs1] s*u x[rs2]) >>s 32|NONE|NONE |performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (rs1 treated as signed number, rs2 treated as unsigned number).|Multiplication Operations|
|
||||
|DIV |[div rd, rs1, rs2](#div rd, rs1, rs2)|x[rd] = x[rs1] /s x[rs2]|NONE|NONE |perform signed integer division of 32 bits by 32 bits (rounding towards zero).|Division Operations|
|
||||
|DIVU |[divu rd, rs1, rs2](#divu rd, rs1, rs2)|x[rd] = x[rs1] /u x[rs2]|NONE|NONE |perform unsigned integer division of 32 bits by 32 bits (rounding towards zero).|Division Operations|
|
||||
|REM |[rem rd, rs1, rs2](#rem rd, rs1, rs2)|x[rd] = x[rs1] %s x[rs2]|NONE|NONE |provide the remainder of the corresponding division operation DIV (the sign of rd equals the sign of rs1).|Division Operations|
|
||||
|REMU |[rem rd, rs1, rs2](#rem rd, rs1, rs2)|x[rd] = x[rs1] %u x[rs2]|NONE|NONE |provide the remainder of the corresponding division operation DIVU.|Division Operations|
|
||||
|
||||
### RV32C Compressed Instructions
|
||||
|
||||
|Name|Format|Pseudocode|Invalid_values|Exception_raised|Description|Op Name|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|C.LI |[c.li rd, imm[5:0]](#c.li rd, imm[5:0])|x[rd] = sext(imm[5:0])|rd = x0|NONE |loads the sign-extended 6-bit immediate, imm, into register rd.|Integer Computational Instructions|
|
||||
|C.LUI |[c.lui rd, nzimm[17:12]](#c.lui rd, nzimm[17:12])|x[rd] = sext(nzimm[17:12] << 12)|rd = x0 & rd = x2 & nzimm = 0|NONE |loads the non-zero 6-bit immediate field into bits 17–12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination.|Integer Computational Instructions|
|
||||
|C.ADDI |[c.addi rd, nzimm[5:0]](#c.addi rd, nzimm[5:0])|x[rd] = x[rd] + sext(nzimm[5:0])|rd = x0 & nzimm = 0|NONE |adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd.|Integer Computational Instructions|
|
||||
|C.ADDI16SP |[c.addi16sp nzimm[9:4]](#c.addi16sp nzimm[9:4])|x[2] = x[2] + sext(nzimm[9:4])|rd != x2 & nzimm = 0|NONE |adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range (-512,496). C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues. C.ADDI16SP shares the opcode with C.LUI, but has a destination field of x2.|Integer Computational Instructions|
|
||||
|C.ADDI4SPN |[c.addi4spn rd', nzimm[9:2]](#c.addi4spn rd', nzimm[9:2])|x[8 + rd'] = x[2] + zext(nzimm[9:2])|nzimm = 0|NONE |adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd'. This instruction is used to generate pointers to stack-allocated variables.|Integer Computational Instructions|
|
||||
|C.SLLI |[c.slli rd, uimm[5:0]](#c.slli rd, uimm[5:0])|x[rd] = x[rd] << uimm[5:0]|rd = x0 & uimm[5] = 0|NONE |performs a logical left shift (zeros are shifted into the lower bits).|Integer Computational Instructions|
|
||||
|C.SRLI |[c.srli rd', uimm[5:0]](#c.srli rd', uimm[5:0])|x[8 + rd'] = x[8 + rd'] >> uimm[5:0]|uimm[5] = 0|NONE |performs a logical right shift (zeros are shifted into the upper bits).|Integer Computational Instructions|
|
||||
|C.SRAI |[c.srai rd', uimm[5:0]](#c.srai rd', uimm[5:0])|x[8 + rd'] = x[8 + rd'] >>s uimm[5:0]|uimm[5] = 0|NONE |performs an arithmetic right shift (sign bits are shifted into the upper bits).|Integer Computational Instructions|
|
||||
|C.ANDI |[c.andi rd', imm[5:0]](#c.andi rd', imm[5:0])|x[8 + rd'] = x[8 + rd'] & sext(imm[5:0])|NONE|NONE |computes the bitwise AND of the value in register rd', and the sign-extended 6-bit immediate, then writes the result to rd'.|Integer Computational Instructions|
|
||||
|C.ADD |[c.add rd, rs2](#c.add rd, rs2)|x[rd] = x[rd] + x[rs2]|rd = x0 & rs2 = x0|NONE |adds the values in registers rd and rs2 and writes the result to register rd.|Integer Computational Instructions|
|
||||
|C.MV |[c.mv rd, rs2](#c.mv rd, rs2)|x[rd] = x[rs2]|rd = x0 & rs2 = x0|NONE |copies the value in register rs2 into register rd.|Integer Computational Instructions|
|
||||
|C.AND |[c.and rd', rs2'](#c.and rd', rs2')|x[8 + rd'] = x[8 + rd'] & x[8 + rs2']|NONE|NONE |computes the bitwise AND of of the value in register rd', and register rs2', then writes the result to rd'.|Integer Computational Instructions|
|
||||
|C.OR |[c.or rd', rs2'](#c.or rd', rs2')|x[8 + rd'] = x[8 + rd'] \| x[8 + rs2']|NONE|NONE |computes the bitwise OR of of the value in register rd', and register rs2', then writes the result to rd'.|Integer Computational Instructions|
|
||||
|C.XOR |[c.and rd', rs2'](#c.and rd', rs2')|x[8 + rd'] = x[8 + rd'] ^ x[8 + rs2']|NONE|NONE |computes the bitwise XOR of of the value in register rd', and register rs2', then writes the result to rd'.|Integer Computational Instructions|
|
||||
|C.SUB |[c.sub rd', rs2'](#c.sub rd', rs2')|x[8 + rd'] = x[8 + rd'] - x[8 + rs2']|NONE|NONE |subtracts the value in registers rs2' from value in rd' and writes the result to register rd'.|Integer Computational Instructions|
|
||||
|C.EBREAK |[c.ebreak](#c.ebreak)|RaiseException(Breakpoint)|NONE|Raise a Breakpoint exception. |cause control to be transferred back to the debugging environment.|Integer Computational Instructions|
|
||||
|C.J |[c.j imm[11:1]](#c.j imm[11:1])|pc += sext(imm[11:1])|NONE|jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception.|performs an unconditional control transfer. The offset is sign-extended and added to the pc to form the jump target address.|Control Transfer Instructions|
|
||||
|C.JAL |[c.jal imm[11:1]](#c.jal imm[11:1])|x[1] = pc+2; pc += sext(imm[11:1])|NONE|jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception.|performs the same operation as C.J, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1.|Control Transfer Instructions|
|
||||
|C.JR |[c.jr rs1](#c.jr rs1)|pc = x[rs1]|rs1 = x0|jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception.|performs an unconditional control transfer to the address in register rs1.|Control Transfer Instructions|
|
||||
|C.JALR |[c.jalr rs1](#c.jalr rs1)|t = pc+2; pc = x[rs1]; x[1] = t|rs1 = x0|jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception.|performs the same operation as C.JR, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1.|Control Transfer Instructions|
|
||||
|C.BEQZ |[c.beqz rs1', imm[8:1]](#c.beqz rs1', imm[8:1])|if (x[8+rs1'] == 0) pc += sext(imm[8:1])|NONE|no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions.|performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. C.BEQZ takes the branch if the value in register rs1' is zero.|Control Transfer Instructions|
|
||||
|C.BNEZ |[c.bnez rs1', imm[8:1]](#c.bnez rs1', imm[8:1])|if (x[8+rs1'] != 0) pc += sext(imm[8:1])|NONE|no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions.|performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. C.BEQZ takes the branch if the value in register rs1' isn't zero.|Control Transfer Instructions|
|
||||
|C.LWSP |[c.lwsp rd, uimm(x2)](#c.lwsp rd, uimm(x2))|x[rd] = M[x[2] + zext(uimm[7:2])][31:0]|rd = x0|loads with a destination of x0 must still raise any exceptions, also an exception if the memory address isn't aligned (4-byte boundary).|loads a 32-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2.|Load and Store Instructions|
|
||||
|C.SWSP |[c.swsp rd, uimm(x2)](#c.swsp rd, uimm(x2))|M[x[2] + zext(uimm[7:2])][31:0] = x[rs2]|NONE|an exception raised if the memory address isn't aligned (4-byte boundary).|stores a 32-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2.|Load and Store Instructions|
|
||||
|C.LW |[c.lw rd', uimm(rs1')](#c.lw rd', uimm(rs1'))|x[8+rd'] = M[x[8+rs1'] + zext(uimm[6:2])][31:0])|NONE|an exception raised if the memory address isn't aligned (4-byte boundary).|loads a 32-bit value from memory into register rd'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'.|Load and Store Instructions|
|
||||
|C.SW |[c.sw rs2', uimm(rs1')](#c.sw rs2', uimm(rs1'))|M[x[8+rs1'] + zext(uimm[6:2])][31:0] = x[8+rs2']|NONE|an exception raised if the memory address isn't aligned (4-byte boundary).|stores a 32-bit value from memory into register rd'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'.|Load and Store Instructions|
|
||||
|
||||
### RV32Zicsr Control and Status Register Instructions
|
||||
|
||||
|Name|Format|Pseudocode|Invalid_values|Exception_raised|Description|Op Name|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|CSRRW |[csrrw rd, csr, rs1](#csrrw rd, csr, rs1)|t = CSRs[csr]; CSRs[csr] = x[rs1]; x[rd] = t|NONE|Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. |Reads the old value of the CSR, zero-extends the value to 32 bits, then writes it to integer register rd. The initial value in rs1 is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side-effects that might occur on a CSR read. |Control and Status Register Operations|
|
||||
|CSRRS |[csrrs rd, csr, rs1](#csrrs rd, csr, rs1)|t = CSRs[csr]; CSRs[csr] = t \| x[rs1]; x[rd] = t|NONE|Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. |Reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written). If rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, such as raising illegal instruction exceptions on accesses to read-only CSRs. |Control and Status Register Operations|
|
||||
|CSRRC |[csrrc rd, csr, rs1](#csrrc rd, csr, rs1)|t = CSRs[csr]; CSRs[csr] = t & ∼x[rs1]; x[rd] = t|NONE|Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. |Reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written). If rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, such as raising illegal instruction exceptions on accesses to read-only CSRs. |Control and Status Register Operations|
|
||||
|CSRRWI |[csrrwi rd, csr, uimm[4:0]](#csrrwi rd, csr, uimm[4:0])|x[rd] = CSRs[csr]; CSRs[csr] = zext(uimm[4:0])|NONE|Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. |Reads the old value of the CSR, zero-extends the value to 32 bits, then writes it to integer register rd. The zero-extends immediate is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side-effects that might occur on a CSR read. |Control and Status Register Operations|
|
||||
|CSRRSI |[csrrsi rd, csr, uimm[4:0]](#csrrsi rd, csr, uimm[4:0])|t = CSRs[csr]; CSRs[csr] = t \| zext(uimm[4:0]); x[rd] = t|NONE|Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. |Reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The zero-extends immediate value is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in zero-extends immediate will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written). If the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write. |Control and Status Register Operations|
|
||||
|CSRRCI |[csrrci rd, csr, uimm[4:0]](#csrrci rd, csr, uimm[4:0])|t = CSRs[csr]; CSRs[csr] = t & ∼zext(uimm[4:0]); x[rd] = t|NONE|Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. |Reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The zero-extends immediate value is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in zero-extends immediate will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written). If the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write. |Control and Status Register Operations|
|
||||
|
||||
### RVZifencei Instruction Fetch Fence
|
||||
|
||||
|Name|Format|Pseudocode|Invalid_values|Exception_raised|Description|Op Name|
|
||||
| :--- | :--- | :--- | :--- | :--- | :--- | :--- |
|
||||
|FENCE.I |[fence.i](#fence.i)|Fence(Store, Fetch)|NONE|NONE |The FENCE.I instruction is used to synchronize the instruction and data streams. RISC-V does not guarantee that stores to instruction memory will be made visible to instruction fetches on the same RISC-V hart until a FENCE.I instruction is executed. A FENCE.I instruction only ensures that a subsequent instruction fetch on a RISC-V hart will see any previous data stores already visible to the same RISC-V hart. |Fetch Fence Operations|
|
||||
248
config/gen_from_riscv_config/cv32a65x/isa/isa.rst
Normal file
248
config/gen_from_riscv_config/cv32a65x/isa/isa.rst
Normal file
|
|
@ -0,0 +1,248 @@
|
|||
.. ..::
|
||||
|
||||
Copyright (c) 2024 OpenHW Group
|
||||
Copyright (c) 2024 Thales
|
||||
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
Author: Abdessamii Oukalrazqou
|
||||
|
||||
===
|
||||
isa
|
||||
===
|
||||
|
||||
Instructions
|
||||
------------
|
||||
|
||||
+---------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| Subset Name | Name | Description |
|
||||
+===============+=====================================================+===============================================================================================================================================================================================================================================================================================================================================================+
|
||||
| I | RV32I Base Integer Instructions_ | the base integer instruction set, also known as the 'RV32I' or 'RV64I' instruction set , depending on the address space size, provides the core functionality required for general-purpose computing . |
|
||||
| | | it includes instructions for arithmetic, logical, and control operations, as well as memory access |
|
||||
| | | and manipulation |
|
||||
+---------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| M | RV32M Multiplication and Division Instructions_ | the standard integer multiplication and division instruction extension, which is named “M” and contains instructions that multiply or divide values held in two integer registers. |
|
||||
+---------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| C | RV32C Compressed Instructions_ | RVC uses a simple compression scheme that offers shorter 16-bit versions of common 32-bit RISC-V instructions when: |
|
||||
| | | |
|
||||
| | | the immediate or address offset is small; |
|
||||
| | | one of the registers is the zero register (x0), the ABI link register (x1), or the ABI stack pointer (x2); |
|
||||
| | | the destination register and the first source register are identical; |
|
||||
| | | the registers used are the 8 most popular ones. |
|
||||
| | | |
|
||||
| | | The C extension is compatible with all other standard instruction extensions. The C extension allows 16-bit instructions to be freely intermixed with 32-bit instructions, with the latter now able to start on any 16-bit boundary. With the addition of the C extension, JAL and JALR instructions will no longer raise an instruction misaligned exception |
|
||||
+---------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| Zicsr | RV32Zicsr Control and Status Register Instructions_ | All CSR instructions atomically read-modify-write a single CSR, whose CSR specifier is encoded in the 12-bit csr field of the instruction held in bits 31–20. The immediate forms use a 5-bit zero-extended immediate encoded in the rs1 field. |
|
||||
+---------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| Zifencei | RVZifencei Instruction Fetch Fence_ | FENCE.I instruction that provides explicit synchronization between writes to instruction memory and instruction fetches on the same hart. |
|
||||
| | | Currently, this instruction is the only standard mechanism to ensure that stores visible to a hart will also be visible to it instruction fetches. |
|
||||
+---------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| Zicntr | Zicntr_ | No info found yet for extension Zicntr |
|
||||
+---------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
RV32I Base Integer Instructions
|
||||
-------------------------------
|
||||
|
||||
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| Name | Format | pseudocode | invalid_values | exception_raised | Description | Op Name |
|
||||
+========+==========================+===================================================================+==================+================================================================================================================================================================================================================================================================================+=============================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================+==================================================+
|
||||
| ADDI | addi rd, rs1, imm[11:0] | x[rd] = x[rs1] + sext(imm[11:0]) | NONE | NONE | add sign-extended 12-bit immediate to register rs1, and store the result in register rd. | Integer_Register_Immediate_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| ANDI | andi rd, rs1, imm[11:0] | x[rd] = x[rs1] & sext(imm[11:0]) | NONE | NONE | perform bitwise AND on register rs1 and the sign-extended 12-bit immediate and place the result in rd. | Integer_Register_Immediate_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| ORI | ori rd, rs1, imm[11:0] | x[rd] = x[rs1] | sext(imm[11:0]) | NONE | NONE | perform bitwise OR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. | Integer_Register_Immediate_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| XORI | xori rd, rs1, imm[11:0] | x[rd] = x[rs1] ^ sext(imm[11:0]) | NONE | NONE | perform bitwise XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. | Integer_Register_Immediate_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| SLTI | slti rd, rs1, imm[11:0] | if (x[rs1] < sext(imm[11:0])) x[rd] = 1 else x[rd] = 0 | NONE | NONE | set register rd to 1 if register rs1 is less than the sign extended immediate when both are treated as signed numbers, else 0 is written to rd. | Integer_Register_Immediate_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| SLTIU | sltiu rd, rs1, imm[11:0] | if (x[rs1] <u sext(imm[11:0])) x[rd] = 1 else x[rd] = 0 | NONE | NONE | set register rd to 1 if register rs1 is less than the sign extended immediate when both are treated as unsigned numbers, else 0 is written to rd." | Integer_Register_Immediate_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| SLLI | slli rd, rs1, imm[4:0] | x[rd] = x[rs1] << imm[4:0] | NONE | NONE | logical left shift (zeros are shifted into the lower bits). | Integer_Register_Immediate_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| SRLI | srli rd, rs1, imm[4:0] | x[rd] = x[rs1] >> imm[4:0] | NONE | NONE | logical right shift (zeros are shifted into the upper bits). | Integer_Register_Immediate_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| SRAI | srai rd, rs1, imm[4:0] | x[rd] = x[rs1] >>s imm[4:0] | NONE | NONE | arithmetic right shift (the original sign bit is copied into the vacated upper bits). | Integer_Register_Immediate_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| LUI | lui rd, imm[19:0] | x[rd] = sext(imm[31:12] << 12) | NONE | NONE | place the immediate value in the top 20 bits of the destination register rd, filling in the lowest 12 bits with zeros. | Integer_Register_Immediate_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| AUIPC | auipc rd, imm[19:0] | x[rd] = pc + sext(immediate[31:12] << 12) | NONE | NONE | form a 32-bit offset from the 20-bit immediate, filling in the lowest 12 bits with zeros, adds this offset to the pc, then place the result in register rd. | Integer_Register_Immediate_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| ADD | add rd, rs1, rs2 | x[rd] = x[rs1] + x[rs2] | NONE | NONE | add rs2 to register rs1, and store the result in register rd. | Integer_Register_Register_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| SUB | sub rd, rs1, rs2 | x[rd] = x[rs1] - x[rs2] | NONE | NONE | subtract rs2 from register rs1, and store the result in register rd. | Integer_Register_Register_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| AND | and rd, rs1, rs2 | x[rd] = x[rs1] & x[rs2] | NONE | NONE | perform bitwise AND on register rs1 and rs2 and place the result in rd. | Integer_Register_Register_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| OR | or rd, rs1, rs2 | x[rd] = x[rs1] | x[rs2] | NONE | NONE | perform bitwise OR on register rs1 and rs2 and place the result in rd. | Integer_Register_Register_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| XOR | xor rd, rs1, rs2 | x[rd] = x[rs1] ^ x[rs2] | NONE | NONE | perform bitwise XOR on register rs1 and rs2 and place the result in rd. | Integer_Register_Register_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| SLT | slt rd, rs1, rs2 | if (x[rs1] < x[rs2]) x[rd] = 1 else x[rd] = 0 | NONE | NONE | set register rd to 1 if register rs1 is less than rs2 when both are treated as signed numbers, else 0 is written to rd. | Integer_Register_Register_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| SLTU | sltu rd, rs1, rs2 | if (x[rs1] <u x[rs2]) x[rd] = 1 else x[rd] = 0 | NONE | NONE | set register rd to 1 if register rs1 is less than rs2 when both are treated as unsigned numbers, else 0 is written to rd. | Integer_Register_Register_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| SLL | sll rd, rs1, rs2 | x[rd] = x[rs1] << x[rs2] | NONE | NONE | logical left shift (zeros are shifted into the lower bits). | Integer_Register_Register_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| SRL | srl rd, rs1, rs2 | x[rd] = x[rs1] >> x[rs2] | NONE | NONE | logical right shift (zeros are shifted into the upper bits). | Integer_Register_Register_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| SRA | sra rd, rs1, rs2 | x[rd] = x[rs1] >>s x[rs2] | NONE | NONE | arithmetic right shift (the original sign bit is copied into the vacated upper bits). | Integer_Register_Register_Operations |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| JAL | jal rd, imm[20:1] | x[rd] = pc+4; pc += sext(imm[20:1]) | NONE | jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. | offset is sign-extended and added to the pc to form the jump target address (pc is calculated using signed arithmetic), then setting the least-significant bit of the result to zero, and store the address of instruction following the jump (pc+4) into register rd. | Control_Transfer_Operations-Unconditional_Jumps |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| JALR | jalr rd, rs1, imm[11:0] | t = pc+4; pc = (x[rs1]+sext(imm[11:0]))&∼1 ; x[rd] = t | NONE | jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. | target address is obtained by adding the 12-bit signed immediate to the register rs1 (pc is calculated using signed arithmetic), then setting the least-significant bit of the result to zero, and store the address of instruction following the jump (pc+4) into register rd. | Control_Transfer_Operations-Unconditional_Jumps |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| BEQ | beq rs1, rs2, imm[12:1] | if (x[rs1] == x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 | NONE | no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. | takes the branch (pc is calculated using signed arithmetic) if registers rs1 and rs2 are equal. | Control_Transfer_Operations-Conditional_Branches |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| BNE | bne rs1, rs2, imm[12:1] | if (x[rs1] != x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 | NONE | no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. | takes the branch (pc is calculated using signed arithmetic) if registers rs1 and rs2 are not equal. | Control_Transfer_Operations-Conditional_Branches |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| BLT | blt rs1, rs2, imm[12:1] | if (x[rs1] < x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 | NONE | no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. | takes the branch (pc is calculated using signed arithmetic) if registers rs1 less than rs2 (using signed comparison). | Control_Transfer_Operations-Conditional_Branches |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| BLTU | bltu rs1, rs2, imm[12:1] | if (x[rs1] <u x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 | NONE | no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. | takes the branch (pc is calculated using signed arithmetic) if registers rs1 less than rs2 (using unsigned comparison). | Control_Transfer_Operations-Conditional_Branches |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| BGE | bge rs1, rs2, imm[12:1] | if (x[rs1] >= x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 | NONE | no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. | takes the branch (pc is calculated using signed arithmetic) if registers rs1 is greater than or equal rs2 (using signed comparison). | Control_Transfer_Operations-Conditional_Branches |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| BGEU | bgeu rs1, rs2, imm[12:1] | if (x[rs1] >=u x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 | NONE | no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. | takes the branch (pc is calculated using signed arithmetic) if registers rs1 is greater than or equal rs2 (using unsigned comparison). | Control_Transfer_Operations-Conditional_Branches |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| LB | lb rd, imm(rs1) | x[rd] = sext(M[x[rs1] + sext(imm[11:0])][7:0]) | NONE | loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded. | loads a 8-bit value from memory, then sign-extends to 32-bit before storing in rd (rd is calculated using signed arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | Load_and_Store_Instructions |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| LH | lh rd, imm(rs1) | x[rd] = sext(M[x[rs1] + sext(imm[11:0])][15:0]) | NONE | loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (2-byte boundary). | loads a 16-bit value from memory, then sign-extends to 32-bit before storing in rd (rd is calculated using signed arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | Load_and_Store_Instructions |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| LW | lw rd, imm(rs1) | x[rd] = sext(M[x[rs1] + sext(imm[11:0])][31:0]) | NONE | loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (4-byte boundary). | loads a 32-bit value from memory, then storing in rd (rd is calculated using signed arithmetic). The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | Load_and_Store_Instructions |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| LBU | lbu rd, imm(rs1) | x[rd] = zext(M[x[rs1] + sext(imm[11:0])][7:0]) | NONE | loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded. | loads a 8-bit value from memory, then zero-extends to 32-bit before storing in rd (rd is calculated using unsigned arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | Load_and_Store_Instructions |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| LHU | lhu rd, imm(rs1) | x[rd] = zext(M[x[rs1] + sext(imm[11:0])][15:0]) | NONE | loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (2-byte boundary). | loads a 16-bit value from memory, then zero-extends to 32-bit before storing in rd (rd is calculated using unsigned arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | Load_and_Store_Instructions |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| SB | sb rs2, imm(rs1) | M[x[rs1] + sext(imm[11:0])][7:0] = x[rs2][7:0] | NONE | NONE | stores a 8-bit value from the low bits of register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | Load_and_Store_Instructions |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| SH | sh rs2, imm(rs1) | M[x[rs1] + sext(imm[11:0])][15:0] = x[rs2][15:0] | NONE | an exception is raised if the memory address isn't aligned (2-byte boundary). | stores a 16-bit value from the low bits of register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | Load_and_Store_Instructions |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| SW | sw rs2, imm(rs1) | M[x[rs1] + sext(imm[11:0])][31:0] = x[rs2][31:0] | NONE | an exception is raised if the memory address isn't aligned (4-byte boundary). | stores a 32-bit value from register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | Load_and_Store_Instructions |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| FENCE | fence pre, succ | No operation (nop) | NONE | NONE | order device I/O and memory accesses as viewed by other RISC-V harts and external devices or coprocessors. Any combination of device input (I), device output (O), memory reads (R), and memory writes (W) may be ordered with respect to any combination of the same. Informally, no other RISC-V hart or external device can observe any operation in the successor set following a FENCE before any operation in the predecessor set preceding the FENCE, as the core support 1 hart, the fence instruction has no effect so we can considerate it as a nop instruction. | Memory_Ordering |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| ECALL | ecall | RaiseException(EnvironmentCall) | NONE | Raise an Environment Call exception. | make a request to the supporting execution environment, which is usually an operating system. The ABI for the system will define how parameters for the environment request are passed, but usually these will be in defined locations in the integer register file. | Environment_Call_and_Breakpoints |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
| EBREAK | ebreak | x[8 + rd'] = sext(x[8 + rd'][7:0]) | NONE | NONE | This instruction takes a single source/destination operand. It sign-extends the least-significant byte in the operand by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support. | Environment_Call_and_Breakpoints |
|
||||
+--------+--------------------------+-------------------------------------------------------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+
|
||||
|
||||
RV32M Multiplication and Division Instructions
|
||||
----------------------------------------------
|
||||
|
||||
|
||||
+--------+---------------------+------------------------------------+------------------+--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+
|
||||
| Name | Format | pseudocode | invalid_values | exception_raised | Description | Op Name |
|
||||
+========+=====================+====================================+==================+====================+==========================================================================================================================================================================================+===========================+
|
||||
| MUL | mul rd, rs1, rs2 | x[rd] = x[rs1] * x[rs2] | NONE | NONE | performs a 32-bit × 32-bit multiplication and places the lower 32 bits in the destination register (Both rs1 and rs2 treated as signed numbers). | Multiplication Operations |
|
||||
+--------+---------------------+------------------------------------+------------------+--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+
|
||||
| MULH | mulh rd, rs1, rs2 | x[rd] = (x[rs1] s*s x[rs2]) >>s 32 | NONE | NONE | performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (Both rs1 and rs2 treated as signed numbers). | Multiplication Operations |
|
||||
+--------+---------------------+------------------------------------+------------------+--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+
|
||||
| MULHU | mulhu rd, rs1, rs2 | x[rd] = (x[rs1] u*u x[rs2]) >>u 32 | NONE | NONE | performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (Both rs1 and rs2 treated as unsigned numbers). | Multiplication Operations |
|
||||
+--------+---------------------+------------------------------------+------------------+--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+
|
||||
| MULHSU | mulhsu rd, rs1, rs2 | x[rd] = (x[rs1] s*u x[rs2]) >>s 32 | NONE | NONE | performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (rs1 treated as signed number, rs2 treated as unsigned number). | Multiplication Operations |
|
||||
+--------+---------------------+------------------------------------+------------------+--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+
|
||||
| DIV | div rd, rs1, rs2 | x[rd] = x[rs1] /s x[rs2] | NONE | NONE | perform signed integer division of 32 bits by 32 bits (rounding towards zero). | Division Operations |
|
||||
+--------+---------------------+------------------------------------+------------------+--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+
|
||||
| DIVU | divu rd, rs1, rs2 | x[rd] = x[rs1] /u x[rs2] | NONE | NONE | perform unsigned integer division of 32 bits by 32 bits (rounding towards zero). | Division Operations |
|
||||
+--------+---------------------+------------------------------------+------------------+--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+
|
||||
| REM | rem rd, rs1, rs2 | x[rd] = x[rs1] %s x[rs2] | NONE | NONE | provide the remainder of the corresponding division operation DIV (the sign of rd equals the sign of rs1). | Division Operations |
|
||||
+--------+---------------------+------------------------------------+------------------+--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+
|
||||
| REMU | rem rd, rs1, rs2 | x[rd] = x[rs1] %u x[rs2] | NONE | NONE | provide the remainder of the corresponding division operation DIVU. | Division Operations |
|
||||
+--------+---------------------+------------------------------------+------------------+--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+
|
||||
|
||||
RV32C Compressed Instructions
|
||||
-----------------------------
|
||||
|
||||
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| Name | Format | pseudocode | invalid_values | exception_raised | Description | Op Name |
|
||||
+============+============================+==================================================+===============================+================================================================================================================================================================================================================================================================================+=================================================================================================================================================================================================================================================================================================================================================+====================================+
|
||||
| C.LI | c.li rd, imm[5:0] | x[rd] = sext(imm[5:0]) | rd = x0 | NONE | loads the sign-extended 6-bit immediate, imm, into register rd. | Integer Computational Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.LUI | c.lui rd, nzimm[17:12] | x[rd] = sext(nzimm[17:12] << 12) | rd = x0 & rd = x2 & nzimm = 0 | NONE | loads the non-zero 6-bit immediate field into bits 17–12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. | Integer Computational Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.ADDI | c.addi rd, nzimm[5:0] | x[rd] = x[rd] + sext(nzimm[5:0]) | rd = x0 & nzimm = 0 | NONE | adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd. | Integer Computational Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.ADDI16SP | c.addi16sp nzimm[9:4] | x[2] = x[2] + sext(nzimm[9:4]) | rd != x2 & nzimm = 0 | NONE | adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range (-512,496). C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues. C.ADDI16SP shares the opcode with C.LUI, but has a destination field of x2. | Integer Computational Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.ADDI4SPN | c.addi4spn rd', nzimm[9:2] | x[8 + rd'] = x[2] + zext(nzimm[9:2]) | nzimm = 0 | NONE | adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd'. This instruction is used to generate pointers to stack-allocated variables. | Integer Computational Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.SLLI | c.slli rd, uimm[5:0] | x[rd] = x[rd] << uimm[5:0] | rd = x0 & uimm[5] = 0 | NONE | performs a logical left shift (zeros are shifted into the lower bits). | Integer Computational Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.SRLI | c.srli rd', uimm[5:0] | x[8 + rd'] = x[8 + rd'] >> uimm[5:0] | uimm[5] = 0 | NONE | performs a logical right shift (zeros are shifted into the upper bits). | Integer Computational Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.SRAI | c.srai rd', uimm[5:0] | x[8 + rd'] = x[8 + rd'] >>s uimm[5:0] | uimm[5] = 0 | NONE | performs an arithmetic right shift (sign bits are shifted into the upper bits). | Integer Computational Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.ANDI | c.andi rd', imm[5:0] | x[8 + rd'] = x[8 + rd'] & sext(imm[5:0]) | NONE | NONE | computes the bitwise AND of the value in register rd', and the sign-extended 6-bit immediate, then writes the result to rd'. | Integer Computational Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.ADD | c.add rd, rs2 | x[rd] = x[rd] + x[rs2] | rd = x0 & rs2 = x0 | NONE | adds the values in registers rd and rs2 and writes the result to register rd. | Integer Computational Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.MV | c.mv rd, rs2 | x[rd] = x[rs2] | rd = x0 & rs2 = x0 | NONE | copies the value in register rs2 into register rd. | Integer Computational Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.AND | c.and rd', rs2' | x[8 + rd'] = x[8 + rd'] & x[8 + rs2'] | NONE | NONE | computes the bitwise AND of of the value in register rd', and register rs2', then writes the result to rd'. | Integer Computational Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.OR | c.or rd', rs2' | x[8 + rd'] = x[8 + rd'] | x[8 + rs2'] | NONE | NONE | computes the bitwise OR of of the value in register rd', and register rs2', then writes the result to rd'. | Integer Computational Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.XOR | c.and rd', rs2' | x[8 + rd'] = x[8 + rd'] ^ x[8 + rs2'] | NONE | NONE | computes the bitwise XOR of of the value in register rd', and register rs2', then writes the result to rd'. | Integer Computational Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.SUB | c.sub rd', rs2' | x[8 + rd'] = x[8 + rd'] - x[8 + rs2'] | NONE | NONE | subtracts the value in registers rs2' from value in rd' and writes the result to register rd'. | Integer Computational Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.EBREAK | c.ebreak | RaiseException(Breakpoint) | NONE | Raise a Breakpoint exception. | cause control to be transferred back to the debugging environment. | Integer Computational Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.J | c.j imm[11:1] | pc += sext(imm[11:1]) | NONE | jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. | performs an unconditional control transfer. The offset is sign-extended and added to the pc to form the jump target address. | Control Transfer Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.JAL | c.jal imm[11:1] | x[1] = pc+2; pc += sext(imm[11:1]) | NONE | jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. | performs the same operation as C.J, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. | Control Transfer Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.JR | c.jr rs1 | pc = x[rs1] | rs1 = x0 | jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. | performs an unconditional control transfer to the address in register rs1. | Control Transfer Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.JALR | c.jalr rs1 | t = pc+2; pc = x[rs1]; x[1] = t | rs1 = x0 | jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. | performs the same operation as C.JR, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. | Control Transfer Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.BEQZ | c.beqz rs1', imm[8:1] | if (x[8+rs1'] == 0) pc += sext(imm[8:1]) | NONE | no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. | performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. C.BEQZ takes the branch if the value in register rs1' is zero. | Control Transfer Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.BNEZ | c.bnez rs1', imm[8:1] | if (x[8+rs1'] != 0) pc += sext(imm[8:1]) | NONE | no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. | performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. C.BEQZ takes the branch if the value in register rs1' isn't zero. | Control Transfer Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.LWSP | c.lwsp rd, uimm(x2) | x[rd] = M[x[2] + zext(uimm[7:2])][31:0] | rd = x0 | loads with a destination of x0 must still raise any exceptions, also an exception if the memory address isn't aligned (4-byte boundary). | loads a 32-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. | Load and Store Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.SWSP | c.swsp rd, uimm(x2) | M[x[2] + zext(uimm[7:2])][31:0] = x[rs2] | NONE | an exception raised if the memory address isn't aligned (4-byte boundary). | stores a 32-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. | Load and Store Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.LW | c.lw rd', uimm(rs1') | x[8+rd'] = M[x[8+rs1'] + zext(uimm[6:2])][31:0]) | NONE | an exception raised if the memory address isn't aligned (4-byte boundary). | loads a 32-bit value from memory into register rd'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'. | Load and Store Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
| C.SW | c.sw rs2', uimm(rs1') | M[x[8+rs1'] + zext(uimm[6:2])][31:0] = x[8+rs2'] | NONE | an exception raised if the memory address isn't aligned (4-byte boundary). | stores a 32-bit value from memory into register rd'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'. | Load and Store Instructions |
|
||||
+------------+----------------------------+--------------------------------------------------+-------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------+
|
||||
|
||||
RV32Zicsr Control and Status Register Instructions
|
||||
--------------------------------------------------
|
||||
|
||||
|
||||
+--------+---------------------------+------------------------------------------------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
|
||||
| Name | Format | pseudocode | invalid_values | exception_raised | Description | Op Name |
|
||||
+========+===========================+============================================================+==================+========================================================================================================================================================================================================================+===================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================+========================================+
|
||||
| CSRRW | csrrw rd, csr, rs1 | t = CSRs[csr]; CSRs[csr] = x[rs1]; x[rd] = t | NONE | Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. | Reads the old value of the CSR, zero-extends the value to 32 bits, then writes it to integer register rd. The initial value in rs1 is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side-effects that might occur on a CSR read. | Control and Status Register Operations |
|
||||
+--------+---------------------------+------------------------------------------------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
|
||||
| CSRRS | csrrs rd, csr, rs1 | t = CSRs[csr]; CSRs[csr] = t | x[rs1]; x[rd] = t | NONE | Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. | Reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written). If rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, such as raising illegal instruction exceptions on accesses to read-only CSRs. | Control and Status Register Operations |
|
||||
+--------+---------------------------+------------------------------------------------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
|
||||
| CSRRC | csrrc rd, csr, rs1 | t = CSRs[csr]; CSRs[csr] = t & ∼x[rs1]; x[rd] = t | NONE | Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. | Reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written). If rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, such as raising illegal instruction exceptions on accesses to read-only CSRs. | Control and Status Register Operations |
|
||||
+--------+---------------------------+------------------------------------------------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
|
||||
| CSRRWI | csrrwi rd, csr, uimm[4:0] | x[rd] = CSRs[csr]; CSRs[csr] = zext(uimm[4:0]) | NONE | Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. | Reads the old value of the CSR, zero-extends the value to 32 bits, then writes it to integer register rd. The zero-extends immediate is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side-effects that might occur on a CSR read. | Control and Status Register Operations |
|
||||
+--------+---------------------------+------------------------------------------------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
|
||||
| CSRRSI | csrrsi rd, csr, uimm[4:0] | t = CSRs[csr]; CSRs[csr] = t | zext(uimm[4:0]); x[rd] = t | NONE | Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. | Reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The zero-extends immediate value is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in zero-extends immediate will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written). If the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write. | Control and Status Register Operations |
|
||||
+--------+---------------------------+------------------------------------------------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
|
||||
| CSRRCI | csrrci rd, csr, uimm[4:0] | t = CSRs[csr]; CSRs[csr] = t & ∼zext(uimm[4:0]); x[rd] = t | NONE | Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. | Reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The zero-extends immediate value is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in zero-extends immediate will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written). If the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write. | Control and Status Register Operations |
|
||||
+--------+---------------------------+------------------------------------------------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
|
||||
|
||||
RVZifencei Instruction Fetch Fence
|
||||
----------------------------------
|
||||
|
||||
|
||||
+---------+----------+---------------------+------------------+--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+
|
||||
| Name | Format | pseudocode | invalid_values | exception_raised | Description | Op Name |
|
||||
+=========+==========+=====================+==================+====================+==============================================================================================================================================================================================================================================================================================================================================================================================================================+========================+
|
||||
| FENCE.I | fence.i | Fence(Store, Fetch) | NONE | NONE | The FENCE.I instruction is used to synchronize the instruction and data streams. RISC-V does not guarantee that stores to instruction memory will be made visible to instruction fetches on the same RISC-V hart until a FENCE.I instruction is executed. A FENCE.I instruction only ensures that a subsequent instruction fetch on a RISC-V hart will see any previous data stores already visible to the same RISC-V hart. | Fetch Fence Operations |
|
||||
+---------+----------+---------------------+------------------+--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+
|
||||
|
||||
|
||||
+--------+----------+--------------+------------------+--------------------+---------------+-----------+
|
||||
| Name | Format | pseudocode | invalid_values | exception_raised | Description | Op Name |
|
||||
+========+==========+==============+==================+====================+===============+===========+
|
||||
+--------+----------+--------------+------------------+--------------------+---------------+-----------+
|
||||
|
||||
6
config/gen_from_riscv_config/requirements.txt
Normal file
6
config/gen_from_riscv_config/requirements.txt
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
docutils
|
||||
pyyaml
|
||||
mdutils
|
||||
restructuredtext-lint
|
||||
rstcloth
|
||||
regex
|
||||
478
config/gen_from_riscv_config/scripts/.pylintrc
Normal file
478
config/gen_from_riscv_config/scripts/.pylintrc
Normal file
|
|
@ -0,0 +1,478 @@
|
|||
|
||||
|
||||
|
||||
[BASIC]
|
||||
|
||||
# Naming style matching correct argument names.
|
||||
argument-naming-style= any
|
||||
variable-naming-style= any
|
||||
# Regular expression matching correct argument names. Overrides argument-
|
||||
# naming-style. If left empty, argument names will be checked with the set
|
||||
# naming style.
|
||||
#argument-rgx=
|
||||
|
||||
# Naming style matching correct attribute names.
|
||||
attr-naming-style=any
|
||||
|
||||
# Regular expression matching correct attribute names. Overrides attr-naming-
|
||||
# style. If left empty, attribute names will be checked with the set naming
|
||||
# style.
|
||||
#attr-rgx=
|
||||
|
||||
# Bad variable names which should always be refused, separated by a comma.
|
||||
bad-names=foo,
|
||||
bar,
|
||||
baz,
|
||||
toto,
|
||||
tutu,
|
||||
tata
|
||||
|
||||
# Bad variable names regexes, separated by a comma. If names match any regex,
|
||||
# they will always be refused
|
||||
bad-names-rgxs=
|
||||
|
||||
# Naming style matching correct class attribute names.
|
||||
class-attribute-naming-style=any
|
||||
|
||||
# Regular expression matching correct class attribute names. Overrides class-
|
||||
# attribute-naming-style. If left empty, class attribute names will be checked
|
||||
# with the set naming style.
|
||||
#class-attribute-rgx=
|
||||
|
||||
# Naming style matching correct class constant names.
|
||||
class-const-naming-style=UPPER_CASE
|
||||
|
||||
# Regular expression matching correct class constant names. Overrides class-
|
||||
# const-naming-style. If left empty, class constant names will be checked with
|
||||
# the set naming style.
|
||||
#class-const-rgx=
|
||||
|
||||
# Naming style matching correct class names.
|
||||
class-naming-style=PascalCase
|
||||
|
||||
# Regular expression matching correct class names. Overrides class-naming-
|
||||
# style. If left empty, class names will be checked with the set naming style.
|
||||
#class-rgx=
|
||||
|
||||
# Naming style matching correct constant names.
|
||||
const-naming-style= any
|
||||
|
||||
# Regular expression matching correct constant names. Overrides const-naming-
|
||||
# style. If left empty, constant names will be checked with the set naming
|
||||
# style.
|
||||
#const-rgx=
|
||||
|
||||
# Minimum line length for functions/classes that require docstrings, shorter
|
||||
# ones are exempt.
|
||||
docstring-min-length=-1
|
||||
|
||||
# Naming style matching correct function names.
|
||||
function-naming-style=any
|
||||
|
||||
# Regular expression matching correct function names. Overrides function-
|
||||
# naming-style. If left empty, function names will be checked with the set
|
||||
# naming style.
|
||||
#function-rgx=
|
||||
|
||||
# Good variable names which should always be accepted, separated by a comma.
|
||||
good-names=i,
|
||||
j,
|
||||
k,
|
||||
ex,
|
||||
Run,
|
||||
_
|
||||
|
||||
# Good variable names regexes, separated by a comma. If names match any regex,
|
||||
# they will always be accepted
|
||||
good-names-rgxs=
|
||||
|
||||
# Include a hint for the correct naming format with invalid-name.
|
||||
include-naming-hint=no
|
||||
|
||||
# Naming style matching correct inline iteration names.
|
||||
inlinevar-naming-style=any
|
||||
|
||||
# Regular expression matching correct inline iteration names. Overrides
|
||||
# inlinevar-naming-style. If left empty, inline iteration names will be checked
|
||||
# with the set naming style.
|
||||
#inlinevar-rgx=
|
||||
|
||||
# Naming style matching correct method names.
|
||||
method-naming-style= any
|
||||
|
||||
# Regular expression matching correct method names. Overrides method-naming-
|
||||
# style. If left empty, method names will be checked with the set naming style.
|
||||
#method-rgx=
|
||||
|
||||
# Naming style matching correct module names.
|
||||
module-naming-style= any
|
||||
|
||||
|
||||
|
||||
[DESIGN]
|
||||
|
||||
# List of regular expressions of class ancestor names to ignore when counting
|
||||
# public methods (see R0903)
|
||||
exclude-too-few-public-methods= yes
|
||||
|
||||
# List of qualified class names to ignore when counting class parents (see
|
||||
# R0901)
|
||||
ignored-parents=
|
||||
|
||||
# Maximum number of arguments for function / method.
|
||||
max-args=50
|
||||
|
||||
# Maximum number of attributes for a class (see R0902).
|
||||
max-attributes=10
|
||||
|
||||
# Maximum number of boolean expressions in an if statement (see R0916).
|
||||
max-bool-expr=5
|
||||
|
||||
# Maximum number of branch for function / method body.
|
||||
max-branches=50
|
||||
|
||||
# Maximum number of locals for function / method body.
|
||||
max-locals=50
|
||||
|
||||
# Maximum number of parents for a class (see R0901).
|
||||
max-parents=7
|
||||
|
||||
# Maximum number of public methods for a class (see R0904).
|
||||
max-public-methods=20
|
||||
|
||||
# Maximum number of return / yield for function / method body.
|
||||
max-returns=6
|
||||
|
||||
# Maximum number of statements in function / method body.
|
||||
max-statements=150
|
||||
|
||||
# Minimum number of public methods for a class (see R0903).
|
||||
min-public-methods=2
|
||||
|
||||
|
||||
[EXCEPTIONS]
|
||||
|
||||
# Exceptions that will emit a warning when caught.
|
||||
overgeneral-exceptions=builtins.BaseException,builtins.Exception
|
||||
|
||||
|
||||
[FORMAT]
|
||||
|
||||
# Expected format of line ending, e.g. empty (any line ending), LF or CRLF.
|
||||
expected-line-ending-format=
|
||||
|
||||
# Regexp for a line that is allowed to be longer than the limit.
|
||||
ignore-long-lines=^\s*(# )?<?https?://\S+>?$
|
||||
|
||||
# Number of spaces of indent required inside a hanging or continued line.
|
||||
indent-after-paren=4
|
||||
|
||||
# String used as indentation unit. This is usually " " (4 spaces) or "\t" (1
|
||||
# tab).
|
||||
indent-string=' '
|
||||
|
||||
# Maximum number of characters on a single line.
|
||||
max-line-length=3000
|
||||
|
||||
# Maximum number of lines in a module.
|
||||
max-module-lines=1000
|
||||
|
||||
# Allow the body of a class to be on the same line as the declaration if body
|
||||
# contains single statement.
|
||||
single-line-class-stmt=no
|
||||
|
||||
# Allow the body of an if to be on the same line as the test if there is no
|
||||
# else.
|
||||
single-line-if-stmt=no
|
||||
|
||||
|
||||
[IMPORTS]
|
||||
|
||||
# List of modules that can be imported at any level, not just the top level
|
||||
# one.
|
||||
allow-any-import-level=
|
||||
|
||||
# Allow explicit reexports by alias from a package __init__.
|
||||
allow-reexport-from-package=no
|
||||
|
||||
# Allow wildcard imports from modules that define __all__.
|
||||
allow-wildcard-with-all=no
|
||||
|
||||
# Deprecated modules which should not be used, separated by a comma.
|
||||
deprecated-modules=
|
||||
|
||||
# Output a graph (.gv or any supported image format) of external dependencies
|
||||
# to the given file (report RP0402 must not be disabled).
|
||||
ext-import-graph=
|
||||
|
||||
# Output a graph (.gv or any supported image format) of all (i.e. internal and
|
||||
# external) dependencies to the given file (report RP0402 must not be
|
||||
# disabled).
|
||||
import-graph=
|
||||
|
||||
# Output a graph (.gv or any supported image format) of internal dependencies
|
||||
# to the given file (report RP0402 must not be disabled).
|
||||
int-import-graph=
|
||||
|
||||
# Force import order to recognize a module as part of the standard
|
||||
# compatibility libraries.
|
||||
known-standard-library=
|
||||
|
||||
# Force import order to recognize a module as part of a third party library.
|
||||
known-third-party=enchant
|
||||
|
||||
# Couples of modules and preferred modules, separated by a comma.
|
||||
preferred-modules=
|
||||
|
||||
|
||||
[LOGGING]
|
||||
|
||||
# The type of string formatting that logging methods do. `old` means using %
|
||||
# formatting, `new` is for `{}` formatting.
|
||||
logging-format-style=old
|
||||
|
||||
# Logging modules to check that the string format arguments are in logging
|
||||
# function parameter format.
|
||||
logging-modules=logging
|
||||
|
||||
|
||||
[MESSAGES CONTROL]
|
||||
|
||||
# Only show warnings with the listed confidence levels. Leave empty to show
|
||||
# all. Valid levels: HIGH, CONTROL_FLOW, INFERENCE, INFERENCE_FAILURE,
|
||||
# UNDEFINED.
|
||||
confidence=HIGH,
|
||||
CONTROL_FLOW,
|
||||
INFERENCE,
|
||||
INFERENCE_FAILURE,
|
||||
UNDEFINED
|
||||
|
||||
# Disable the message, report, category or checker with the given id(s). You
|
||||
# can either give multiple identifiers separated by comma (,) or put this
|
||||
# option multiple times (only on the command line, not in the configuration
|
||||
# file where it should appear only once). You can also use "--disable=all" to
|
||||
# disable everything first and then re-enable specific checks. For example, if
|
||||
# you want to run only the similarities checker, you can use "--disable=all
|
||||
# --enable=similarities". If you want to run only the classes checker, but have
|
||||
# no Warning level messages displayed, use "--disable=all --enable=classes
|
||||
# --disable=W".
|
||||
disable=raw-checker-failed,
|
||||
bad-inline-option,
|
||||
locally-disabled,
|
||||
file-ignored,
|
||||
suppressed-message,
|
||||
useless-suppression,
|
||||
deprecated-pragma,
|
||||
use-symbolic-message-instead,
|
||||
use-implicit-booleaness-not-comparison-to-string,
|
||||
use-implicit-booleaness-not-comparison-to-zero
|
||||
|
||||
# Enable the message, report, category or checker with the given id(s). You can
|
||||
# either give multiple identifier separated by comma (,) or put this option
|
||||
# multiple time (only on the command line, not in the configuration file where
|
||||
# it should appear only once). See also the "--disable" option for examples.
|
||||
enable=
|
||||
|
||||
|
||||
[METHOD_ARGS]
|
||||
|
||||
# List of qualified names (i.e., library.method) which require a timeout
|
||||
# parameter e.g. 'requests.api.get,requests.api.post'
|
||||
timeout-methods=requests.api.delete,requests.api.get,requests.api.head,requests.api.options,requests.api.patch,requests.api.post,requests.api.put,requests.api.request
|
||||
|
||||
|
||||
[MISCELLANEOUS]
|
||||
|
||||
# List of note tags to take in consideration, separated by a comma.
|
||||
notes=FIXME,
|
||||
XXX,
|
||||
TODO
|
||||
|
||||
# Regular expression of note tags to take in consideration.
|
||||
notes-rgx=
|
||||
|
||||
|
||||
[REFACTORING]
|
||||
|
||||
# Maximum number of nested blocks for function / method body
|
||||
max-nested-blocks=25
|
||||
|
||||
# Complete name of functions that never returns. When checking for
|
||||
# inconsistent-return-statements if a never returning function is called then
|
||||
# it will be considered as an explicit return statement and no message will be
|
||||
# printed.
|
||||
never-returning-functions=sys.exit,argparse.parse_error
|
||||
|
||||
# Let 'consider-using-join' be raised when the separator to join on would be
|
||||
# non-empty (resulting in expected fixes of the type: ``"- " + " -
|
||||
# ".join(items)``)
|
||||
suggest-join-with-non-empty-separator=yes
|
||||
|
||||
|
||||
[REPORTS]
|
||||
|
||||
# Python expression which should return a score less than or equal to 10. You
|
||||
# have access to the variables 'fatal', 'error', 'warning', 'refactor',
|
||||
# 'convention', and 'info' which contain the number of messages in each
|
||||
# category, as well as 'statement' which is the total number of statements
|
||||
# analyzed. This score is used by the global evaluation report (RP0004).
|
||||
evaluation=max(0, 0 if fatal else 10.0 - ((float(5 * error + warning + refactor + convention) / statement) * 10))
|
||||
|
||||
# Template used to display messages. This is a python new-style format string
|
||||
# used to format the message information. See doc for all details.
|
||||
msg-template=
|
||||
|
||||
# Set the output format. Available formats are: text, parseable, colorized,
|
||||
# json2 (improved json format), json (old json format) and msvs (visual
|
||||
# studio). You can also give a reporter class, e.g.
|
||||
# mypackage.mymodule.MyReporterClass.
|
||||
#output-format=
|
||||
|
||||
# Tells whether to display a full report or only the messages.
|
||||
reports=no
|
||||
|
||||
# Activate the evaluation score.
|
||||
score=yes
|
||||
|
||||
|
||||
[SIMILARITIES]
|
||||
|
||||
# Comments are removed from the similarity computation
|
||||
ignore-comments=yes
|
||||
|
||||
# Docstrings are removed from the similarity computation
|
||||
ignore-docstrings=yes
|
||||
|
||||
# Imports are removed from the similarity computation
|
||||
ignore-imports=yes
|
||||
|
||||
# Signatures are removed from the similarity computation
|
||||
ignore-signatures=yes
|
||||
|
||||
# Minimum lines number of a similarity.
|
||||
min-similarity-lines=4
|
||||
|
||||
|
||||
[SPELLING]
|
||||
|
||||
# Limits count of emitted suggestions for spelling mistakes.
|
||||
max-spelling-suggestions=4
|
||||
|
||||
# Spelling dictionary name. No available dictionaries : You need to install
|
||||
# both the python package and the system dependency for enchant to work.
|
||||
spelling-dict=
|
||||
|
||||
# List of comma separated words that should be considered directives if they
|
||||
# appear at the beginning of a comment and should not be checked.
|
||||
spelling-ignore-comment-directives=fmt: on,fmt: off,noqa:,noqa,nosec,isort:skip,mypy:
|
||||
|
||||
# List of comma separated words that should not be checked.
|
||||
spelling-ignore-words=
|
||||
|
||||
# A path to a file that contains the private dictionary; one word per line.
|
||||
spelling-private-dict-file=
|
||||
|
||||
# Tells whether to store unknown words to the private dictionary (see the
|
||||
# --spelling-private-dict-file option) instead of raising a message.
|
||||
spelling-store-unknown-words=no
|
||||
|
||||
|
||||
[STRING]
|
||||
|
||||
# This flag controls whether inconsistent-quotes generates a warning when the
|
||||
# character used as a quote delimiter is used inconsistently within a module.
|
||||
check-quote-consistency=no
|
||||
|
||||
# This flag controls whether the implicit-str-concat should generate a warning
|
||||
# on implicit string concatenation in sequences defined over several lines.
|
||||
check-str-concat-over-line-jumps=no
|
||||
|
||||
|
||||
[TYPECHECK]
|
||||
|
||||
# List of decorators that produce context managers, such as
|
||||
# contextlib.contextmanager. Add to this list to register other decorators that
|
||||
# produce valid context managers.
|
||||
contextmanager-decorators=contextlib.contextmanager
|
||||
|
||||
# List of members which are set dynamically and missed by pylint inference
|
||||
# system, and so shouldn't trigger E1101 when accessed. Python regular
|
||||
# expressions are accepted.
|
||||
generated-members=
|
||||
|
||||
# Tells whether to warn about missing members when the owner of the attribute
|
||||
# is inferred to be None.
|
||||
ignore-none=yes
|
||||
|
||||
# This flag controls whether pylint should warn about no-member and similar
|
||||
# checks whenever an opaque object is returned when inferring. The inference
|
||||
# can return multiple potential results while evaluating a Python object, but
|
||||
# some branches might not be evaluated, which results in partial inference. In
|
||||
# that case, it might be useful to still emit no-member and other checks for
|
||||
# the rest of the inferred objects.
|
||||
ignore-on-opaque-inference=yes
|
||||
|
||||
# List of symbolic message names to ignore for Mixin members.
|
||||
ignored-checks-for-mixins=no-member,
|
||||
not-async-context-manager,
|
||||
not-context-manager,
|
||||
attribute-defined-outside-init
|
||||
|
||||
# List of class names for which member attributes should not be checked (useful
|
||||
# for classes with dynamically set attributes). This supports the use of
|
||||
# qualified names.
|
||||
ignored-classes=optparse.Values,thread._local,_thread._local,argparse.Namespace
|
||||
|
||||
# Show a hint with possible names when a member name was not found. The aspect
|
||||
# of finding the hint is based on edit distance.
|
||||
missing-member-hint=yes
|
||||
|
||||
# The minimum edit distance a name should have in order to be considered a
|
||||
# similar match for a missing member name.
|
||||
missing-member-hint-distance=1
|
||||
|
||||
# The total number of similar names that should be taken in consideration when
|
||||
# showing a hint for a missing member.
|
||||
missing-member-max-choices=1
|
||||
|
||||
# Regex pattern to define which classes are considered mixins.
|
||||
mixin-class-rgx=.*[Mm]ixin
|
||||
|
||||
# List of decorators that change the signature of a decorated function.
|
||||
signature-mutators=
|
||||
|
||||
|
||||
[VARIABLES]
|
||||
|
||||
# List of additional names supposed to be defined in builtins. Remember that
|
||||
# you should avoid defining new builtins when possible.
|
||||
additional-builtins=
|
||||
|
||||
# Tells whether unused global variables should be treated as a violation.
|
||||
allow-global-unused-variables=yes
|
||||
|
||||
# List of names allowed to shadow builtins
|
||||
allowed-redefined-builtins=
|
||||
|
||||
# List of strings which can identify a callback function by name. A callback
|
||||
# name must start or end with one of those strings.
|
||||
callbacks=cb_,
|
||||
_cb
|
||||
|
||||
# A regular expression matching the name of dummy variables (i.e. expected to
|
||||
# not be used).
|
||||
dummy-variables-rgx=_+$|(_[a-zA-Z0-9_]*[a-zA-Z0-9]+?$)|dummy|^ignored_|^unused_
|
||||
|
||||
# Argument names that match this expression will be ignored.
|
||||
ignored-argument-names=_.*|^ignored_|^unused_
|
||||
|
||||
# Tells whether we should check for unused import in __init__ files.
|
||||
init-import=no
|
||||
|
||||
# List of qualified module names which can have objects that can redefine
|
||||
# builtins.
|
||||
redefining-builtins-modules=six.moves,past.builtins,future.builtins,builtins,io
|
||||
|
||||
|
||||
[MASTER]
|
||||
disable = C0116,
|
||||
149
config/gen_from_riscv_config/scripts/libs/csr_factorizer.py
Normal file
149
config/gen_from_riscv_config/scripts/libs/csr_factorizer.py
Normal file
|
|
@ -0,0 +1,149 @@
|
|||
# Copyright 2024 Thales DIS France SAS
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# Original Author: Oukalrazqou Abdessamii
|
||||
""" Module is used to factorize multiples registers with the same name
|
||||
to a specific format of registers """
|
||||
import re
|
||||
|
||||
|
||||
def address_to_key(address):
|
||||
return int(address, 16)
|
||||
|
||||
|
||||
def factorizer(yaml_data):
|
||||
privname = None
|
||||
fieldname = []
|
||||
regname = []
|
||||
regdescr = []
|
||||
regadress = []
|
||||
reg_number = []
|
||||
new_regname = []
|
||||
data = []
|
||||
field_suffix = []
|
||||
suffix_name = []
|
||||
suffix_descr = []
|
||||
suffix_address = []
|
||||
suffix_number = []
|
||||
key_to_remove = []
|
||||
for key, value in yaml_data["hart0"].items():
|
||||
if isinstance(value, dict):
|
||||
regelement = yaml_data["hart0"].get(key, {})
|
||||
if regelement.get("address", None):
|
||||
regaddress = hex(regelement.get("address", None))
|
||||
else:
|
||||
regaddress = ""
|
||||
if regelement.get("description", ""):
|
||||
desc = regelement.get("description", "")
|
||||
else:
|
||||
desc = ""
|
||||
if regelement.get("rv32", "")["accessible"]:
|
||||
pattern = r"(\D+)(\d+)(.*)"
|
||||
match = re.search(pattern, key)
|
||||
if match:
|
||||
key_to_remove.append(key)
|
||||
if privname and match.group(1) == privname.group(1):
|
||||
if len(match.group(3)) > 0:
|
||||
suffix_name.append(match.group(0))
|
||||
field_suffix.append(match.group(1))
|
||||
suffix_number.append(match.group(2))
|
||||
suffix_descr.append(desc)
|
||||
suffix_address.append((regaddress))
|
||||
else:
|
||||
fieldname.append(match.group(1))
|
||||
regname.append(match.group(0))
|
||||
reg_number.append(match.group(2))
|
||||
regdescr.append(desc)
|
||||
regadress.append(regaddress)
|
||||
else:
|
||||
if regname:
|
||||
regadress = sorted(regadress, key=address_to_key)
|
||||
regname = sorted(
|
||||
regname, key=lambda x: int(x.lstrip(fieldname[0]))
|
||||
)
|
||||
start_address = hex(int(regadress[0], 16))
|
||||
desc = str(regdescr[0])
|
||||
desc = re.sub(str(regname[0]), fieldname[0], desc)
|
||||
modified_data = yaml_data["hart0"][regname[0]].copy()
|
||||
modified_data["address"] = (
|
||||
f"{str(start_address)}-{str(regadress[-1])}"
|
||||
)
|
||||
new_regname.append(
|
||||
f"{fieldname[0]}[{reg_number[0]}-{reg_number[-1]}]"
|
||||
)
|
||||
data.append(modified_data)
|
||||
regname = [match.group(0)]
|
||||
fieldname = [match.group(1)]
|
||||
reg_number = [match.group(2)]
|
||||
regdescr = []
|
||||
regadress = [regaddress]
|
||||
if suffix_name:
|
||||
suffix_name = sorted(
|
||||
suffix_name,
|
||||
key=lambda x: int(
|
||||
x.lstrip(field_suffix[0]).rstrip("h")
|
||||
),
|
||||
)
|
||||
suffix_address = sorted(suffix_address, key=address_to_key)
|
||||
desc = str(suffix_descr[0])
|
||||
desc = re.sub(str(suffix_name[0]), field_suffix[0], desc)
|
||||
modified_data = yaml_data["hart0"][suffix_name[0]].copy()
|
||||
modified_data["address"] = (
|
||||
f"{str(suffix_address[0])}-{str(suffix_address[-1])}"
|
||||
)
|
||||
new_regname.append(
|
||||
f"{field_suffix[0]}[{suffix_number[0]}-{suffix_number[-1]}]h"
|
||||
)
|
||||
data.append(modified_data)
|
||||
suffix_name = []
|
||||
field_suffix = []
|
||||
regdescr = []
|
||||
suffix_number = [match.group(2)]
|
||||
suffix_address = []
|
||||
privname = match
|
||||
if regname:
|
||||
start_address = hex(int(regadress[0], 16))
|
||||
end_address = str(regadress[-1])
|
||||
desc = str(regdescr[0])
|
||||
desc = re.sub(str(regname[0]), fieldname[0], desc)
|
||||
modified_data = yaml_data["hart0"][regname[0]].copy()
|
||||
modified_data["description"] = desc
|
||||
modified_data["address"] = f"{str(start_address)}-{str(end_address)}"
|
||||
new_regname.append(f"{fieldname[0]}[{reg_number[0]}-{reg_number[-1]}]")
|
||||
data.append(modified_data)
|
||||
regname = []
|
||||
regdescr = []
|
||||
regadress = []
|
||||
fieldname = []
|
||||
if suffix_name:
|
||||
desc = str(suffix_descr[0])
|
||||
desc = re.sub(str(suffix_name[0]), field_suffix[0], desc)
|
||||
modified_data = yaml_data["hart0"][suffix_name[0]].copy()
|
||||
modified_data["description"] = desc
|
||||
modified_data["address"] = (
|
||||
f"{str(hex(int(suffix_address[0],16)))}-{str(suffix_address[-1])}"
|
||||
)
|
||||
new_regname.append(
|
||||
f"{field_suffix[0]}[{suffix_number[0]}-{suffix_number[-1]}]h"
|
||||
)
|
||||
data.append(modified_data)
|
||||
suffix_name = []
|
||||
field_suffix = []
|
||||
regdescr = []
|
||||
regadress = []
|
||||
for index, reg in enumerate(new_regname):
|
||||
yaml_data["hart0"][reg] = data[index]
|
||||
for key in key_to_remove:
|
||||
del yaml_data["hart0"][key]
|
||||
return yaml_data["hart0"]
|
||||
100
config/gen_from_riscv_config/scripts/libs/csr_updater.py
Normal file
100
config/gen_from_riscv_config/scripts/libs/csr_updater.py
Normal file
|
|
@ -0,0 +1,100 @@
|
|||
# Copyright 2024 Thales DIS France SAS
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# Original Author: Oukalrazqou Abdessamii
|
||||
""" Module is used to update csr based on yaml file called csr updater"""
|
||||
import yaml
|
||||
|
||||
|
||||
def csr_recursive_update(original_dict, csr_update):
|
||||
"""
|
||||
Gets the data of the RISC-V Config Yaml file and
|
||||
update the value of sub key in RISC-V Config Yaml file
|
||||
(ex: reset-val , shadow_type)
|
||||
:param original_dict : parsed data of RISC-V Config Yaml file
|
||||
csr_update : parsed data of CSR updater
|
||||
:return: data of RISC-V Config Yaml file updated
|
||||
"""
|
||||
for key, value in csr_update.items():
|
||||
if key in original_dict.keys():
|
||||
print(key)
|
||||
if isinstance(value, dict):
|
||||
csr_recursive_update(original_dict[key], value)
|
||||
elif isinstance(value, bool):
|
||||
if isinstance(original_dict[key], dict):
|
||||
for k in original_dict[key]:
|
||||
if isinstance(original_dict[key][k], dict):
|
||||
for sub_key in original_dict[key][k]:
|
||||
original_dict[key][k][sub_key] = value
|
||||
else:
|
||||
original_dict[key][k] = value
|
||||
else:
|
||||
original_dict[key] = value
|
||||
else:
|
||||
original_dict[key] = value
|
||||
|
||||
|
||||
def csr_formatter(srcfile, modifile):
|
||||
# Read original dictionary from YAML Source file
|
||||
with open(srcfile, "r", encoding="utf-8") as file:
|
||||
original_dict = yaml.safe_load(file)
|
||||
updated_values = {}
|
||||
if modifile is not None:
|
||||
with open(modifile, "r", encoding="utf-8") as file:
|
||||
updated_values = yaml.safe_load(file)
|
||||
# Update original_dict with values from updated_values recursively
|
||||
csr_recursive_update(original_dict["hart0"], updated_values)
|
||||
|
||||
# Identify and remove keys within the range specified for each register
|
||||
keys_to_remove = []
|
||||
for key, value in updated_values.items():
|
||||
if "range" in value:
|
||||
range_value = value["range"]
|
||||
pattern = rf"{key}(\d+)"
|
||||
for k in original_dict["hart0"].keys():
|
||||
match = re.search(pattern, str(k))
|
||||
if match:
|
||||
index = int(match.group(1))
|
||||
if index >= range_value:
|
||||
keys_to_remove.append(k)
|
||||
# Remove excluded keys based on the condition
|
||||
exclude_data = updated_values.get("exclude")
|
||||
if exclude_data:
|
||||
exclude_key = exclude_data.get("key")
|
||||
sub_key = exclude_data.get("sub_key")
|
||||
cond = exclude_data.get("cond")
|
||||
|
||||
def remove_keys_recursive(dictionary):
|
||||
keys_to_remove = []
|
||||
for k, v in dictionary.items():
|
||||
if isinstance(v, dict):
|
||||
if sub_key:
|
||||
if v.get(exclude_key, {}).get(sub_key) == cond:
|
||||
keys_to_remove.append(k)
|
||||
else:
|
||||
if v.get(exclude_key) == cond:
|
||||
keys_to_remove.append(k)
|
||||
remove_keys_recursive(v)
|
||||
for k in keys_to_remove:
|
||||
dictionary.pop(k)
|
||||
|
||||
remove_keys_recursive(original_dict["hart0"])
|
||||
remove_keys_recursive(original_dict["hart0"])
|
||||
# Remove keys from original_dict
|
||||
for k in keys_to_remove:
|
||||
original_dict["hart0"].pop(k, None)
|
||||
# Remove keys from original_dict
|
||||
for k in keys_to_remove:
|
||||
original_dict.pop(k, None)
|
||||
return original_dict
|
||||
130
config/gen_from_riscv_config/scripts/libs/isa_updater.py
Normal file
130
config/gen_from_riscv_config/scripts/libs/isa_updater.py
Normal file
|
|
@ -0,0 +1,130 @@
|
|||
# Copyright 2024 Thales DIS France SAS
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# Original Author: Oukalrazqou Abdessamii
|
||||
|
||||
""" Module is used to update isa based on yaml file called isa updater"""
|
||||
|
||||
|
||||
import re
|
||||
import yaml
|
||||
|
||||
|
||||
def extension_update(isa_dict, isa_list, yaml_ext):
|
||||
"""
|
||||
Gets the data of the updater and detect if you want to add or remove an extension
|
||||
:param isa_dict : parsed data of updater
|
||||
isa_list : list of extension read from ISA String(default supported extension)
|
||||
yaml_ext : list of extensions subset names read from isa template
|
||||
:return: list of updated extensions
|
||||
"""
|
||||
# print(extension_update.__doc__)
|
||||
for element, value in isa_dict.items():
|
||||
if isinstance(value, bool):
|
||||
if isa_dict.get(element, False):
|
||||
if element in yaml_ext:
|
||||
isa_list.append(element)
|
||||
else:
|
||||
print(f"No info found yet for extension {element}")
|
||||
else:
|
||||
if element in isa_list:
|
||||
isa_list.remove(element)
|
||||
|
||||
|
||||
def isa_recursive_update(original_dict, isa_dict):
|
||||
"""
|
||||
Gets the data of the isa template and update the value of sub key in isa_template
|
||||
(ex: format , legal_values)
|
||||
:param original_dict : parsed data of isa template
|
||||
isa_dict : parsed data of updater
|
||||
:return: isa template updated
|
||||
"""
|
||||
for key, value in isa_dict.items():
|
||||
if key in original_dict.keys():
|
||||
if isinstance(value, dict):
|
||||
isa_recursive_update(original_dict[key], value)
|
||||
elif isinstance(value, bool):
|
||||
if isinstance(original_dict[key], dict):
|
||||
for k in original_dict[key]:
|
||||
if isinstance(original_dict[key][k], dict):
|
||||
for sub_key in original_dict[key][k]:
|
||||
original_dict[key][k][sub_key] = value
|
||||
else:
|
||||
original_dict[key][k] = value
|
||||
else:
|
||||
original_dict[key] = value
|
||||
else:
|
||||
original_dict[key] = value
|
||||
|
||||
|
||||
# Extracting subset names from the YAML data
|
||||
def isa_filter(parsed_data, updater, template):
|
||||
"""
|
||||
create dict of filtred data from isa_template based on supported extensions
|
||||
read from ISA String from RISC-V Yaml file
|
||||
:param parsed_data : parsed data of RISC-V Config Yaml file
|
||||
updater : parsed data of updater
|
||||
template : parsed data of isa_template
|
||||
:return: dict of filtred data from isa_template
|
||||
"""
|
||||
# Define the regular expression pattern
|
||||
isa_regex = re.compile(
|
||||
r"""
|
||||
RV(32|64|128)([IE] # Match RV32, RV64, or RV128 followed by I or E
|
||||
[ACDFGHJLMNPQSTUV]*) # Match zero or more letters
|
||||
((Z\w+)|([^\W_]+))* # Match zero or more occurrences of extensions starting with Z (e.g., Zifencei)
|
||||
# or other non-word characters except underscore (e.g., letters)
|
||||
(X[a-z0-9]*)* # Match zero or more occurrences of X followed by lowercase letters or digits
|
||||
(_X[a-z0-9]*)*$ # Match zero or more occurrences of underscore followed by X and lowercase letters or digits
|
||||
""",
|
||||
re.VERBOSE,
|
||||
)
|
||||
# Use search to find the pattern in the string
|
||||
extensions = []
|
||||
# If a match is found, extract the extensions
|
||||
match = isa_regex.match(parsed_data["hart0"]["ISA"])
|
||||
if match:
|
||||
character_data = match.group(2)
|
||||
characters = list(character_data)
|
||||
extensions.extend(characters)
|
||||
extension_list = match.group(3).split("_")
|
||||
extensions.extend(extension_list)
|
||||
print("Extensions:", extensions)
|
||||
else:
|
||||
print("No extensions found.")
|
||||
# Open and load the template YAML file
|
||||
data = {}
|
||||
if template is not None:
|
||||
with open(template, "r", encoding="utf-8") as file:
|
||||
data = yaml.safe_load(file)
|
||||
# Open and load the updater YAML file if exists
|
||||
modif_dict = {}
|
||||
if updater is not None:
|
||||
with open(updater, "r", encoding="utf-8") as file:
|
||||
modif_dict = yaml.safe_load(file)
|
||||
isa_recursive_update(data, modif_dict)
|
||||
yaml_extensions = [data[key]["Subset_Name"] for key in data]
|
||||
extension_update(modif_dict, extensions, yaml_extensions)
|
||||
subset_data = {}
|
||||
for ext in extensions:
|
||||
for key in data:
|
||||
if data[key]["Subset_Name"] == ext:
|
||||
subset_data[key] = data[key]
|
||||
missing_extensions = [ext for ext in extensions if ext not in yaml_extensions]
|
||||
for ext in missing_extensions:
|
||||
subset_data[ext] = {
|
||||
"Description": f"No info found yet for extension {ext}",
|
||||
"Subset_Name": ext,
|
||||
}
|
||||
return subset_data
|
||||
883
config/gen_from_riscv_config/scripts/libs/utils.py
Normal file
883
config/gen_from_riscv_config/scripts/libs/utils.py
Normal file
|
|
@ -0,0 +1,883 @@
|
|||
# Copyright 2024 Thales DIS France SAS
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# Original Author: Oukalrazqou Abdessamii
|
||||
|
||||
""" Module is used to gather all utils and function to generate the csr and isa documents"""
|
||||
|
||||
import io
|
||||
import os
|
||||
import re
|
||||
import yaml
|
||||
import rstcloth
|
||||
import libs.isa_updater
|
||||
import libs.csr_updater
|
||||
import libs.csr_factorizer
|
||||
from rstcloth import RstCloth
|
||||
from mdutils.mdutils import MdUtils
|
||||
from libs.isa_updater import isa_filter
|
||||
from libs.csr_updater import csr_formatter
|
||||
from libs.csr_factorizer import factorizer
|
||||
|
||||
pattern_warl = r"\b(?:warl|wlrl|ro_constant|ro_variable)\b" #pattern to detect warl in field
|
||||
pattern_legal_dict = r"\[(0x[0-9A-Fa-f]+)(.*?(0x[0-9A-Fa-f]+))?\]" # pattern to detect if warl field is dict
|
||||
pattern_legal_list = r"\[(0x[0-9A-Fa-f]+)(.*?(0x[0-9A-Fa-f]+))?\]" #pattern to detect if warl field is a list
|
||||
Factorizer_pattern = r".*(\d).*" # pattern to detect factorized fields
|
||||
|
||||
|
||||
class DocumentClass:
|
||||
"""Document class"""
|
||||
|
||||
def __init__(self, name):
|
||||
self.name = name
|
||||
self.memoryMapList = []
|
||||
|
||||
def addMemoryMap(self, memoryMap):
|
||||
self.memoryMapList.append(memoryMap)
|
||||
|
||||
|
||||
class MemoryMapClass:
|
||||
"""memory map class"""
|
||||
|
||||
def __init__(self, name):
|
||||
self.name = name
|
||||
self.addressBlockList = []
|
||||
|
||||
def addAddressBlock(self, addressBlock):
|
||||
self.addressBlockList.append(addressBlock)
|
||||
|
||||
|
||||
class AddressBlockClass:
|
||||
"""address block class"""
|
||||
|
||||
def __init__(self, name):
|
||||
self.name = name
|
||||
self.registerList = []
|
||||
self.suffix = ""
|
||||
|
||||
def addRegister(self, reg):
|
||||
assert isinstance(reg, RegisterClass)
|
||||
self.registerList.append(reg)
|
||||
|
||||
def setRegisterList(self, registerList):
|
||||
self.registerList = registerList
|
||||
|
||||
def returnAsString(self):
|
||||
raise NotImplementedError(
|
||||
"method returnAsString() is virutal and must be overridden."
|
||||
)
|
||||
|
||||
|
||||
class RegisterClass:
|
||||
"""register class"""
|
||||
|
||||
def __init__(
|
||||
self, name, address, resetValue, size, access, desc, RV32, RV64, field
|
||||
):
|
||||
self.name = name
|
||||
self.address = address
|
||||
self.resetValue = resetValue
|
||||
self.size = size
|
||||
self.access = access
|
||||
self.desc = desc
|
||||
self.RV32 = RV32
|
||||
self.RV64 = RV64
|
||||
self.field = field
|
||||
|
||||
|
||||
class Field:
|
||||
"""field class"""
|
||||
|
||||
def __init__(
|
||||
self, name, bitlegal, bitmask, bitmsb, bitlsb, bitWidth, fieldDesc, fieldaccess
|
||||
):
|
||||
self.name = name
|
||||
self.bitlegal = bitlegal
|
||||
self.bitmask = bitmask
|
||||
self.bitmsb = bitmsb
|
||||
self.bitlsb = bitlsb
|
||||
self.bitWidth = bitWidth
|
||||
self.fieldDesc = fieldDesc
|
||||
self.fieldaccess = fieldaccess
|
||||
|
||||
|
||||
# --------------------------------------------------------------#
|
||||
class ISAdocumentClass:
|
||||
"""ISA document class"""
|
||||
|
||||
def __init__(self, name):
|
||||
self.name = name
|
||||
self.instructions = []
|
||||
|
||||
def addInstructionMapBlock(self, InstructionMap):
|
||||
self.instructions.append(InstructionMap)
|
||||
|
||||
|
||||
class InstructionMapClass:
|
||||
"""ISA instruction map class"""
|
||||
|
||||
def __init__(self, name):
|
||||
self.name = name
|
||||
self.InstructionBlockList = []
|
||||
|
||||
def addInstructionBlock(self, InstructionBlock):
|
||||
self.InstructionBlockList.append(InstructionBlock)
|
||||
|
||||
|
||||
class Instruction:
|
||||
"""ISA instruction class"""
|
||||
|
||||
def __init__(
|
||||
self,
|
||||
key,
|
||||
Extension_Name,
|
||||
descr,
|
||||
OperationName,
|
||||
Name,
|
||||
Format,
|
||||
Description,
|
||||
pseudocode,
|
||||
invalid_values,
|
||||
exception_raised,
|
||||
):
|
||||
self.key = key
|
||||
self.Extension_Name = Extension_Name
|
||||
self.descr = descr
|
||||
self.OperationName = OperationName
|
||||
self.Name = Name
|
||||
self.Format = Format
|
||||
self.Description = Description
|
||||
self.invalid_values = invalid_values
|
||||
self.pseudocode = pseudocode
|
||||
self.exception_raised = exception_raised
|
||||
|
||||
|
||||
class InstructionBlockClass:
|
||||
"""ISA instruction block class"""
|
||||
|
||||
def __init__(self, name):
|
||||
self.name = name
|
||||
self.Instructionlist = []
|
||||
self.suffix = ""
|
||||
|
||||
def addInstruction(self, Inst):
|
||||
assert isinstance(Inst, Instruction)
|
||||
self.Instructionlist.append(Inst)
|
||||
|
||||
def setInstructionList(self, Instructionlist):
|
||||
self.Instructionlist = Instructionlist
|
||||
|
||||
def returnAsString(self):
|
||||
raise NotImplementedError(
|
||||
"method returnAsString() is virutal and must be overridden."
|
||||
)
|
||||
|
||||
|
||||
class RstAddressBlock(AddressBlockClass):
|
||||
"""Generates a ReStructuredText file from a IP-XACT register description"""
|
||||
|
||||
def __init__(self, name):
|
||||
super().__init__("csr")
|
||||
self.name = name
|
||||
self.registerList = []
|
||||
self.suffix = ".rst"
|
||||
|
||||
def sort_address(self):
|
||||
for reg in self.registerList:
|
||||
if "-" in reg.address:
|
||||
start, end = reg.address.split("-")
|
||||
return int(start, 16), int(end, 16)
|
||||
return int(reg.address, 16), int(reg.address, 16)
|
||||
|
||||
def returnAsString(self):
|
||||
registerlist = sorted(self.registerList, key=lambda reg: reg.address)
|
||||
r = RstCloth(io.StringIO()) # with default parameter, sys.stdout is used
|
||||
regNameList = [reg.name for reg in registerlist]
|
||||
regAddressList = [reg.address for reg in registerlist]
|
||||
regDescrList = [reg.desc for reg in registerlist]
|
||||
regRV32List = [reg.RV32 for reg in registerlist]
|
||||
regRV64List = [reg.RV64 for reg in registerlist]
|
||||
r.directive('..', content= ["Copyright (c) 2024 OpenHW Group",
|
||||
"Copyright (c) 2024 Thales",
|
||||
"SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1",
|
||||
"Author: Abdessamii Oukalrazqou"])
|
||||
r.title(self.name) # Use the name of the addressBlock as title
|
||||
r.newline()
|
||||
r.h2("Register Summary")
|
||||
summary_table = []
|
||||
for i, _ in enumerate(regNameList):
|
||||
if regRV32List[i] | regRV64List[i]:
|
||||
summary_table.append(
|
||||
[regAddressList[i], str(regNameList[i]), str(regDescrList[i])]
|
||||
)
|
||||
r.table(header=["Address", "Register Name", "Description"], data=summary_table)
|
||||
|
||||
r.h2("Register Description")
|
||||
for reg in registerlist:
|
||||
if reg.RV32 | reg.RV64:
|
||||
reg_table = []
|
||||
r.h2(reg.name)
|
||||
r.newline()
|
||||
r.field("Address", (reg.address))
|
||||
if reg.resetValue:
|
||||
# display the resetvalue in hex notation in the full length of the register
|
||||
r.field(
|
||||
"Reset Value",
|
||||
"0x" + f"{reg.resetValue[2:].zfill(int(reg.size/4))}",
|
||||
)
|
||||
r.field("priviliege mode", reg.access)
|
||||
r.field("Description", reg.desc)
|
||||
for field in reg.field:
|
||||
if field.bitWidth == 1: # only one bit -> no range needed
|
||||
bits = f"{field.bitlsb}"
|
||||
else:
|
||||
bits = f"[{field.bitmsb}:{field.bitlsb}]"
|
||||
_line = [
|
||||
bits,
|
||||
field.name,
|
||||
field.bitlegal,
|
||||
field.bitmask,
|
||||
field.fieldaccess,
|
||||
]
|
||||
_line.append(field.fieldDesc)
|
||||
reg_table.append(_line)
|
||||
_headers = ["Bits", "Field name", "Legalvalues", "Mask", "Access"]
|
||||
_headers.append("Description")
|
||||
# table of the register
|
||||
r.table(header=_headers, data=reg_table)
|
||||
return r.data
|
||||
|
||||
|
||||
class InstrstBlock(InstructionBlockClass):
|
||||
"""Generates a ISA ReStructuredText file from RISC V Config Yaml register description"""
|
||||
|
||||
def __init__(self, name):
|
||||
super().__init__("isa")
|
||||
self.name = name
|
||||
self.Instructionlist = []
|
||||
self.suffix = ".rst"
|
||||
|
||||
def returnAsString(self):
|
||||
r = rstcloth.RstCloth(
|
||||
io.StringIO()
|
||||
) # with default parameter, sys.stdout is used
|
||||
InstrNameList = [reg.key for reg in self.Instructionlist]
|
||||
InstrDescrList = [reg.descr for reg in self.Instructionlist]
|
||||
InstrExtList = [reg.Extension_Name for reg in self.Instructionlist]
|
||||
r.directive('..', content= ["Copyright (c) 2024 OpenHW Group",
|
||||
"Copyright (c) 2024 Thales",
|
||||
"SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1",
|
||||
"Author: Abdessamii Oukalrazqou"])
|
||||
r.title(self.name) # Use the name of the addressBlock as title
|
||||
r.newline()
|
||||
r.h2("Instructions")
|
||||
summary_table = []
|
||||
for i, _ in enumerate(InstrNameList):
|
||||
summary_table.append(
|
||||
[
|
||||
str(InstrExtList[i]),
|
||||
str(InstrNameList[i]) + "_",
|
||||
str(InstrDescrList[i]),
|
||||
]
|
||||
)
|
||||
r.table(header=["Subset Name", "Name ", "Description"], data=summary_table)
|
||||
for reg in self.Instructionlist:
|
||||
reg_table = []
|
||||
_headers = [
|
||||
"Name",
|
||||
"Format",
|
||||
"pseudocode",
|
||||
"invalid_values",
|
||||
"exception_raised",
|
||||
"Description",
|
||||
"Op Name",
|
||||
]
|
||||
if len(reg.Name) > 0:
|
||||
r.h2(reg.key)
|
||||
r.newline()
|
||||
for fieldIndex in list(range(len(reg.Name))):
|
||||
_line = [
|
||||
reg.Name[fieldIndex],
|
||||
reg.Format[fieldIndex],
|
||||
reg.pseudocode[fieldIndex],
|
||||
reg.invalid_values[fieldIndex],
|
||||
reg.exception_raised[fieldIndex],
|
||||
reg.Description[fieldIndex],
|
||||
]
|
||||
_line.append(reg.OperationName[fieldIndex])
|
||||
reg_table.append(_line)
|
||||
# table of the register
|
||||
r.table(header=_headers, data=reg_table)
|
||||
return r.data
|
||||
|
||||
|
||||
class InstmdBlock(InstructionBlockClass):
|
||||
"""Generates a ISA Markdown file from a RISC Config Yaml register description"""
|
||||
|
||||
def __init__(self, name):
|
||||
super().__init__("isa")
|
||||
self.name = name
|
||||
self.Instructionlist = []
|
||||
self.suffix = ".md"
|
||||
self.mdFile = MdUtils(file_name="none", title="")
|
||||
|
||||
def returnAsString(self):
|
||||
InstrNameList = [reg.key for reg in self.Instructionlist]
|
||||
InstrDescrList = [reg.descr for reg in self.Instructionlist]
|
||||
InstrExtList = [reg.Extension_Name for reg in self.Instructionlist]
|
||||
licence = ["<!--Copyright (c) 2024 OpenHW Group","Copyright (c) 2024 Thales","SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 ","Author: Abdessamii Oukalrazqou" ,"-->"]
|
||||
for l in licence :
|
||||
self.mdFile.write(l + '\n')
|
||||
self.mdFile.new_header(
|
||||
level=1, title=self.name
|
||||
) # Use the name of the addressBlock as title
|
||||
self.mdFile.new_paragraph()
|
||||
self.mdFile.new_header(level=2, title="Instructions")
|
||||
|
||||
# summary
|
||||
header = ["Subset Name", "Name ", "Description"]
|
||||
rows = []
|
||||
for i, _ in enumerate(InstrNameList):
|
||||
InstrDescrList[i] = str(InstrDescrList[i]).replace("\n", " ")
|
||||
rows.extend(
|
||||
[
|
||||
str(InstrExtList[i]),
|
||||
f"[{InstrNameList[i]}](#{InstrNameList[i]})",
|
||||
str(InstrDescrList[i]),
|
||||
]
|
||||
)
|
||||
self.mdFile.new_table(
|
||||
columns=len(header),
|
||||
rows=len(InstrNameList) + 1, # header + data
|
||||
text=header + rows,
|
||||
text_align="left",
|
||||
)
|
||||
|
||||
# all registers
|
||||
for reg in self.Instructionlist:
|
||||
if len(reg.Name) > 0:
|
||||
headers = [
|
||||
"Name",
|
||||
"Format",
|
||||
"Pseudocode",
|
||||
"Invalid_values",
|
||||
"Exception_raised",
|
||||
"Description",
|
||||
"Op Name",
|
||||
]
|
||||
self.returnMdRegDesc(reg.key)
|
||||
reg_table = []
|
||||
for fieldIndex in list(range(len(reg.Name))):
|
||||
reg_table.append(reg.Name[fieldIndex].ljust(15))
|
||||
reg.Format[fieldIndex] = (
|
||||
f"[{reg.Format[fieldIndex]}](#{reg.Format[fieldIndex]})"
|
||||
)
|
||||
reg_table.append(reg.Format[fieldIndex])
|
||||
reg.pseudocode[fieldIndex] = str(
|
||||
reg.pseudocode[fieldIndex]
|
||||
).replace("\n", " ")
|
||||
reg_table.append(reg.pseudocode[fieldIndex])
|
||||
reg_table.append(reg.invalid_values[fieldIndex])
|
||||
reg.exception_raised[fieldIndex] = str(
|
||||
reg.exception_raised[fieldIndex]
|
||||
).replace("\n", " ")
|
||||
reg_table.append(reg.exception_raised[fieldIndex].ljust(40))
|
||||
reg.Description[fieldIndex] = str(
|
||||
reg.Description[fieldIndex]
|
||||
).replace("\n", " ")
|
||||
reg_table.append(reg.Description[fieldIndex])
|
||||
reg_table.append(reg.OperationName[fieldIndex])
|
||||
self.mdFile.new_table(
|
||||
columns=len(headers),
|
||||
rows=len(reg.Description) + 1,
|
||||
text=headers + reg_table,
|
||||
text_align="left",
|
||||
)
|
||||
return self.mdFile.file_data_text
|
||||
|
||||
def returnMdRegDesc(self, name):
|
||||
self.mdFile.new_header(level=3, title=name)
|
||||
|
||||
|
||||
class MdAddressBlock(AddressBlockClass):
|
||||
"""Generates a CSR Markdown file from a RISC Config Yaml register description"""
|
||||
|
||||
def __init__(self, name):
|
||||
super().__init__("csr")
|
||||
self.name = name
|
||||
self.registerList = []
|
||||
self.suffix = ".md"
|
||||
self.mdFile = MdUtils(file_name="none", title="")
|
||||
|
||||
def returnAsString(self):
|
||||
registerlist = sorted(self.registerList, key=lambda reg: reg.address)
|
||||
regNameList = [reg.name for reg in registerlist if reg.RV32 | reg.RV64]
|
||||
regAddressList = [reg.address for reg in registerlist if reg.RV32 | reg.RV64]
|
||||
regDescrList = [reg.desc for reg in registerlist if reg.RV32 | reg.RV64]
|
||||
licence = ["<!--Copyright (c) 2024 OpenHW Group","Copyright (c) 2024 Thales","SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 ","Author: Abdessamii Oukalrazqou" ,"-->"]
|
||||
for l in licence :
|
||||
self.mdFile.write(l + '\n')
|
||||
self.mdFile.new_header(
|
||||
level=1, title=self.name
|
||||
) # Use the name of the addressBlock as title
|
||||
self.mdFile.new_paragraph()
|
||||
self.mdFile.new_header(level=2, title="Registers Summary")
|
||||
# summary
|
||||
header = ["Address", "Register Name", "Description"]
|
||||
rows = []
|
||||
for i, _ in enumerate(regNameList):
|
||||
regDescrList[i] = str(regDescrList[i]).replace("\n", " ")
|
||||
rows.extend(
|
||||
[
|
||||
regAddressList[i],
|
||||
f"[{regNameList[i]}](#{regNameList[i]})",
|
||||
str(regDescrList[i]),
|
||||
]
|
||||
)
|
||||
self.mdFile.new_table(
|
||||
columns=len(header),
|
||||
rows=len(regNameList) + 1, # header + data
|
||||
text=header + rows,
|
||||
text_align="left",
|
||||
)
|
||||
# all registers
|
||||
self.mdFile.new_header(level=3, title="Registers Description")
|
||||
for reg in registerlist:
|
||||
if reg.RV64 | reg.RV32:
|
||||
headers = ["Bits", "Field name", "legal values", "Mask", "Access"]
|
||||
headers.append("Description")
|
||||
self.returnMdRegDesc(
|
||||
reg.name, reg.address, reg.resetValue, reg.desc, reg.access
|
||||
)
|
||||
reg_table = []
|
||||
for field in reg.field:
|
||||
if field.bitWidth == 1: # only one bit -> no range needed
|
||||
bits = f"{field.bitlsb}"
|
||||
else:
|
||||
bits = f"[{field.bitmsb}:{field.bitlsb}]"
|
||||
reg_table.append(bits)
|
||||
reg_table.append(field.name)
|
||||
reg_table.append(field.bitlegal)
|
||||
reg_table.append(field.bitmask)
|
||||
reg_table.append(field.fieldaccess)
|
||||
reg_table.append(field.fieldDesc)
|
||||
self.mdFile.new_table(
|
||||
columns=len(headers),
|
||||
rows=len(reg.field) + 1,
|
||||
text=headers + reg_table,
|
||||
text_align="left",
|
||||
)
|
||||
|
||||
return self.mdFile.file_data_text
|
||||
|
||||
def returnMdRegDesc(self, name, address, resetValue, desc, access):
|
||||
self.mdFile.new_header(level=4, title=name)
|
||||
self.mdFile.new_line("---")
|
||||
self.mdFile.new_line("**Address** " + str(address))
|
||||
if resetValue:
|
||||
# display the resetvalue in hex notation in the full length of the register
|
||||
self.mdFile.new_line("**Reset Value**" + resetValue)
|
||||
self.mdFile.new_line("**Priviliege mode** " + access)
|
||||
self.mdFile.new_line("**Description** " + desc)
|
||||
|
||||
|
||||
# -----------------------------------------------------------------------------------------------------------------------#
|
||||
class CsrParser:
|
||||
"""parse CSR risc-v config yaml file"""
|
||||
|
||||
def __init__(self, srcFile, target, modiFile=None):
|
||||
self.srcFile = srcFile
|
||||
self.modiFile = modiFile
|
||||
self.target = target
|
||||
|
||||
def returnRegister(
|
||||
self,
|
||||
regName,
|
||||
registerElem,
|
||||
regAddress,
|
||||
resetValue,
|
||||
size,
|
||||
access,
|
||||
regDesc,
|
||||
fields,
|
||||
RV32,
|
||||
RV64,
|
||||
):
|
||||
fieldList = fields
|
||||
field = []
|
||||
if len(fieldList) > 0:
|
||||
for item in fieldList:
|
||||
if not isinstance(item, list):
|
||||
fieldDesc = registerElem.get("rv32", "")[item].get(
|
||||
"description", ""
|
||||
)
|
||||
bitWidth = (
|
||||
int(registerElem.get("rv32", "")[item].get("msb", ""))
|
||||
- int(registerElem.get("rv32", "")[item].get("lsb", ""))
|
||||
+ 1
|
||||
)
|
||||
bitmsb = int(registerElem.get("rv32", "")[item].get("msb", ""))
|
||||
bitlsb = int(registerElem.get("rv32", "")[item].get("lsb", ""))
|
||||
fieldaccess = (
|
||||
registerElem.get("rv32", "")[item]
|
||||
.get("shadow_type", "")
|
||||
.upper()
|
||||
)
|
||||
legal = registerElem.get("rv32", "")[item].get("type", None)
|
||||
if legal is None:
|
||||
bitlegal = ""
|
||||
bitmask = ""
|
||||
else:
|
||||
warl = re.findall(pattern_warl, str(legal.keys()))
|
||||
if warl:
|
||||
legal_2 = (
|
||||
registerElem.get("rv32", "")[item]
|
||||
.get("type", None)
|
||||
.get(warl[0], None)
|
||||
)
|
||||
if legal_2 is None:
|
||||
bitlegal = "No Legal values"
|
||||
else:
|
||||
if isinstance(legal_2, dict):
|
||||
pattern = r"([\w\[\]:]+\s*\w+\s*)(\[\s*((?:0x)?[0-9A-Fa-f]+)\s*\D+\s*(?:((?:0x)?[0-9A-Fa-f]+))?\s*])"
|
||||
matches = re.search(
|
||||
pattern, str(legal_2["legal"][0])
|
||||
)
|
||||
if matches:
|
||||
legal_value = matches.group(3)
|
||||
mask = matches.group(4)
|
||||
bitmask = mask
|
||||
bitlegal = legal_value
|
||||
elif isinstance(legal_2, list):
|
||||
pattern = r"\s*((?:0x)?[0-9A-Fa-f]+)\s*(.)\s*((?:0x)?[0-9A-Fa-f]+)\s*"
|
||||
matches = re.search(pattern, legal_2[0])
|
||||
if matches:
|
||||
legal_value = matches.group(1)
|
||||
mask = matches.group(3)
|
||||
bitmask = mask
|
||||
bitlegal = legal_value
|
||||
else:
|
||||
mask = 0
|
||||
legal_value = hex(legal_2)
|
||||
bitmask = mask
|
||||
bitlegal = legal_value
|
||||
pattern = r"((\D+)\d+(.*))-\d+"
|
||||
match = re.match(pattern, regName)
|
||||
if match:
|
||||
match_field = re.search(Factorizer_pattern, str(item))
|
||||
if match_field:
|
||||
fieldName = re.sub(
|
||||
match_field.group(1),
|
||||
f"[i*4 + {match_field.group(1)}]",
|
||||
item,
|
||||
)
|
||||
else :
|
||||
fieldName = item
|
||||
elif isinstance(item, list):
|
||||
for item_ in item:
|
||||
fieldName = f"Reserved_{item_[0]}"
|
||||
bitlsb = item_[0]
|
||||
bitmsb = item_[len(item_) - 1]
|
||||
legal = ""
|
||||
fieldaccess = "Reserved"
|
||||
bitWidth = int(item_[len(item_) - 1]) - int(item_[0]) + 1
|
||||
fieldDesc = "Reserved"
|
||||
bitlegal = legal
|
||||
bitmask = ""
|
||||
f = Field(
|
||||
fieldName,
|
||||
bitlegal,
|
||||
bitmask,
|
||||
bitmsb,
|
||||
bitlsb,
|
||||
bitWidth,
|
||||
fieldDesc,
|
||||
fieldaccess,
|
||||
)
|
||||
field.append(f)
|
||||
elif len(fieldList) == 0:
|
||||
pattern = r"(\D+)\[(\d+)\-\d+\](.*)"
|
||||
match = re.match(pattern, regName)
|
||||
if match:
|
||||
if len(match.group(3)) > 0:
|
||||
name = f"{match.group(1)}[i]{match.group(3)}"
|
||||
regDesc = re.sub(
|
||||
match.group(1) + match.group(2) + match.group(3),
|
||||
match.group(1) + match.group(3),
|
||||
regDesc,
|
||||
)
|
||||
else:
|
||||
name = f"{match.group(1)}[i]"
|
||||
regDesc = re.sub(
|
||||
match.group(1) + match.group(2), match.group(1), regDesc
|
||||
)
|
||||
fieldName = name
|
||||
fieldDesc = regDesc
|
||||
else:
|
||||
fieldName = regName
|
||||
bitmsb = registerElem.get("rv32", None).get("msb", None)
|
||||
bitlsb = registerElem.get("rv32", None).get("lsb", None)
|
||||
legal = registerElem.get("rv32", "").get("type", None)
|
||||
if legal is None:
|
||||
bitlegal = ""
|
||||
bitmask = ""
|
||||
else:
|
||||
warl = re.findall(pattern_warl, str(legal.keys()))
|
||||
if warl:
|
||||
legal_2 = (
|
||||
registerElem.get("rv32", "")
|
||||
.get("type", None)
|
||||
.get(warl[0], None)
|
||||
)
|
||||
if legal_2 is None:
|
||||
bitlegal = "No Legal values"
|
||||
else:
|
||||
if isinstance(legal_2, dict):
|
||||
pattern = r"([\w\[\]:]+\s*\w+\s*)(\[\s*((?:0x)?[0-9A-Fa-f]+)\s*\D+\s*(?:((?:0x)?[0-9A-Fa-f]+))?\s*])"
|
||||
matches = re.search(pattern, str(legal_2["legal"][0]))
|
||||
if matches:
|
||||
legal_value = matches.group(3)
|
||||
mask = matches.group(4)
|
||||
bitmask = mask
|
||||
bitlegal = legal_value
|
||||
elif isinstance(legal_2, list):
|
||||
pattern = r"([0-9A-Fa-f]+).*([0-9A-Fa-f]+)"
|
||||
matches = re.search(pattern, legal_2[0])
|
||||
if matches:
|
||||
legal_value = matches.group(1)
|
||||
mask = matches.group(2)
|
||||
bitmask = mask
|
||||
bitlegal = hex(legal_value)
|
||||
else:
|
||||
bitmask = 0
|
||||
bitlegal = hex(legal_2)
|
||||
fieldaccess = registerElem.get("rv32", "").get("shadow_type", "").upper()
|
||||
fieldDesc = regDesc
|
||||
if bitlsb is None:
|
||||
bitlsb = 0
|
||||
if bitmsb is None:
|
||||
bitmsb = 31
|
||||
bitWidth = ""
|
||||
else:
|
||||
bitWidth = int(bitmsb) + 1
|
||||
f = Field(
|
||||
fieldName,
|
||||
bitlegal,
|
||||
bitmask,
|
||||
bitmsb,
|
||||
bitlsb,
|
||||
bitWidth,
|
||||
fieldDesc,
|
||||
fieldaccess,
|
||||
)
|
||||
field.append(f)
|
||||
reg = RegisterClass(
|
||||
regName, regAddress, resetValue, size, access, regDesc, RV32, RV64, field
|
||||
)
|
||||
return reg
|
||||
|
||||
def returnDocument(self):
|
||||
with open(self.srcFile, "r", encoding="utf-8") as f:
|
||||
data = yaml.safe_load(f)
|
||||
data = csr_formatter(self.srcFile, self.modiFile)
|
||||
Registers = factorizer(data)
|
||||
docName = data["hart0"]
|
||||
d = DocumentClass(docName)
|
||||
m = MemoryMapClass(docName)
|
||||
a = AddressBlockClass("csr")
|
||||
for register in Registers:
|
||||
if isinstance(Registers.get(register, {}), dict):
|
||||
RegElement = Registers.get(register, {})
|
||||
regName = register
|
||||
regAddress = (
|
||||
(RegElement.get("address", None))
|
||||
if isinstance(RegElement.get("address", None), str)
|
||||
else hex(RegElement.get("address", None))
|
||||
)
|
||||
reset = hex(RegElement.get("reset-val", ""))
|
||||
size = int(data["hart0"].get("supported_xlen", "")[0])
|
||||
access = RegElement.get("priv_mode", "")
|
||||
if Registers.get(register, {}).get("description", "") is not None:
|
||||
desc = Registers.get(register, {}).get("description", "")
|
||||
else:
|
||||
desc = ""
|
||||
RV32 = RegElement.get("rv32", "").get("accessible", [])
|
||||
RV64 = RegElement.get("rv64", "").get("accessible", [])
|
||||
if RV32:
|
||||
fields = RegElement.get("rv32", "").get("fields", [])
|
||||
else:
|
||||
fields = []
|
||||
r = self.returnRegister(
|
||||
regName,
|
||||
RegElement,
|
||||
regAddress,
|
||||
reset,
|
||||
size,
|
||||
access,
|
||||
desc,
|
||||
fields,
|
||||
RV32,
|
||||
RV64,
|
||||
)
|
||||
a.addRegister(r)
|
||||
m.addAddressBlock(a)
|
||||
d.addMemoryMap(m)
|
||||
|
||||
return d
|
||||
|
||||
|
||||
class IsaParser:
|
||||
"""parse CSR risc-v config yaml file catch isa string"""
|
||||
|
||||
def __init__(self, srcFile, templatefile, target, modiFile=None):
|
||||
self.srcFile = srcFile
|
||||
self.modiFile = modiFile
|
||||
self.templatefile = templatefile
|
||||
self.target = target
|
||||
|
||||
def returnDocument(self):
|
||||
with open(self.srcFile, "r", encoding="utf-8") as file:
|
||||
yaml_data = yaml.safe_load(file)
|
||||
d = ISAdocumentClass("MAP")
|
||||
m = InstructionMapClass("ISA_B")
|
||||
a = InstructionBlockClass("isa")
|
||||
yaml_data = isa_filter(yaml_data, self.modiFile, self.templatefile)
|
||||
for key in yaml_data:
|
||||
Extension_Name = yaml_data[key].get("Subset_Name", None)
|
||||
Descr = yaml_data[key].get("Description", None)
|
||||
instructions_data = yaml_data[key].get("Instructions", None)
|
||||
instruction = self.returnRegister(
|
||||
key, Extension_Name, Descr, instructions_data
|
||||
)
|
||||
a.addInstruction(instruction)
|
||||
m.addInstructionBlock(a)
|
||||
d.addInstructionMapBlock(m)
|
||||
return d
|
||||
|
||||
def returnRegister(self, key, Extension_Name, Descr, instructions_data):
|
||||
OperationName = []
|
||||
Name = []
|
||||
Format = []
|
||||
Description = []
|
||||
pseudocode = []
|
||||
invalid_values = []
|
||||
exception_raised = []
|
||||
if instructions_data:
|
||||
for instruction_name, instruction_data in instructions_data.items():
|
||||
for instruction, data in instruction_data.items():
|
||||
OperationName.append(instruction_name)
|
||||
if instruction is not None:
|
||||
Name.append(instruction)
|
||||
else:
|
||||
Name.append("")
|
||||
description = data.get("Description", "")
|
||||
# handle no or an empty description
|
||||
if description is not None:
|
||||
Description.append(description)
|
||||
else:
|
||||
Description.append("")
|
||||
format_str = data.get("Format", "")
|
||||
if format_str is not None:
|
||||
Format.append(format_str)
|
||||
else:
|
||||
Format.append("")
|
||||
pseudocode_str = data.get("Pseudocode", "")
|
||||
if pseudocode_str is not None:
|
||||
pseudocode.append(pseudocode_str)
|
||||
else:
|
||||
pseudocode.append("")
|
||||
exception_raised_str = data.get("Exception_Raised", "")
|
||||
if exception_raised_str is not None:
|
||||
exception_raised.append(exception_raised_str)
|
||||
else:
|
||||
exception_raised.append("")
|
||||
invalid_values_str = data.get("Invalid_Values", "")
|
||||
if invalid_values_str is not None:
|
||||
invalid_values.append(invalid_values_str)
|
||||
else:
|
||||
invalid_values.append("")
|
||||
Inst = Instruction(
|
||||
key,
|
||||
Extension_Name,
|
||||
Descr,
|
||||
OperationName,
|
||||
Name,
|
||||
Format,
|
||||
Description,
|
||||
pseudocode,
|
||||
invalid_values,
|
||||
exception_raised,
|
||||
)
|
||||
return Inst
|
||||
|
||||
|
||||
class IsaGenerator:
|
||||
"""generate isa folder with isa docs"""
|
||||
|
||||
def __init__(self, target):
|
||||
self.target = target
|
||||
|
||||
def write(self, file_name, string):
|
||||
path = f"./{self.target}/isa/"
|
||||
if not os.path.exists(path):
|
||||
os.makedirs(path)
|
||||
_dest = os.path.join(path, file_name)
|
||||
print("writing file " + _dest)
|
||||
if not os.path.exists(os.path.dirname(_dest)):
|
||||
os.makedirs(os.path.dirname(_dest))
|
||||
|
||||
with open(_dest, "w", encoding="utf-8") as f:
|
||||
f.write(string)
|
||||
|
||||
def generateISA(self, generatorClass, document):
|
||||
for InstructionMap in document.instructions:
|
||||
for InstructionBlock in InstructionMap.InstructionBlockList:
|
||||
blockName = InstructionBlock.name
|
||||
|
||||
block = generatorClass(InstructionBlock.name)
|
||||
|
||||
block.setInstructionList(InstructionBlock.Instructionlist)
|
||||
s = block.returnAsString()
|
||||
file_name = blockName + block.suffix
|
||||
self.write(file_name, s)
|
||||
|
||||
|
||||
class CsrGenerator:
|
||||
"""generate csr folder with csr docs"""
|
||||
|
||||
def __init__(self, target):
|
||||
self.target = target
|
||||
|
||||
def write(self, file_name, string):
|
||||
path = f"./{self.target}/csr/"
|
||||
print(path)
|
||||
if not os.path.exists(path):
|
||||
os.makedirs(path)
|
||||
_dest = os.path.join(path, file_name)
|
||||
print("writing file " + _dest)
|
||||
if not os.path.exists(os.path.dirname(_dest)):
|
||||
os.makedirs(os.path.dirname(_dest))
|
||||
with open(_dest, "w", encoding="utf-8") as f:
|
||||
f.write(string)
|
||||
|
||||
def generateCSR(self, generatorClass, document):
|
||||
for memoryMap in document.memoryMapList:
|
||||
for addressBlock in memoryMap.addressBlockList:
|
||||
blockName = addressBlock.name
|
||||
block = generatorClass(addressBlock.name)
|
||||
|
||||
block.setRegisterList(addressBlock.registerList)
|
||||
s = block.returnAsString()
|
||||
file_name = blockName + block.suffix
|
||||
self.write(file_name, s)
|
||||
48
config/gen_from_riscv_config/scripts/riscv_config_gen.py
Normal file
48
config/gen_from_riscv_config/scripts/riscv_config_gen.py
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
# Copyright 2024 Thales DIS France SAS
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# Original Author: Oukalrazqou Abdessamii
|
||||
""" Module is used to factorize multiples registers with the same name to
|
||||
a specific format of registers """
|
||||
|
||||
import argparse
|
||||
from libs.utils import CsrParser
|
||||
from libs.utils import IsaParser
|
||||
from libs.utils import IsaGenerator
|
||||
from libs.utils import CsrGenerator
|
||||
from libs.utils import RstAddressBlock
|
||||
from libs.utils import MdAddressBlock
|
||||
from libs.utils import InstrstBlock
|
||||
from libs.utils import InstmdBlock
|
||||
|
||||
if __name__ == "__main__":
|
||||
parser = argparse.ArgumentParser(description="ipxact2rst")
|
||||
parser.add_argument("-s", "--srcFile", help="yaml input file")
|
||||
parser.add_argument("-d", "--destDir", help="write generated file to dir")
|
||||
parser.add_argument("-m", "--modif", help="ISA Formatter if existe")
|
||||
parser.add_argument("-i", "--temp", help="Full ISA Template")
|
||||
parser.add_argument("-t", "--target", help="Specifiy Config Name")
|
||||
args, unknown_args = parser.parse_known_args()
|
||||
if args.temp:
|
||||
e = IsaParser(args.srcFile, args.temp, args.target, args.modif)
|
||||
document = e.returnDocument()
|
||||
generator = IsaGenerator(args.target)
|
||||
generator.generateISA(InstrstBlock, document)
|
||||
generator.generateISA(InstmdBlock, document)
|
||||
else:
|
||||
e = CsrParser(args.srcFile, args.target, args.modif)
|
||||
document = e.returnDocument()
|
||||
generator = CsrGenerator(args.target)
|
||||
generator.generateCSR(RstAddressBlock, document)
|
||||
generator.generateCSR(MdAddressBlock, document)
|
||||
1266
config/gen_from_riscv_config/templates/isa_template.yaml
Normal file
1266
config/gen_from_riscv_config/templates/isa_template.yaml
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,18 @@
|
|||
# Copyright (c) 2024 OpenHW Group
|
||||
# Copyright (c) 2024 Thales
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
# Author: Abdessamii Oukalrazqou
|
||||
|
||||
|
||||
misa:
|
||||
reset-val: 123475
|
||||
mcycle:
|
||||
reset-val: 123475
|
||||
mvendorid:
|
||||
description: ''
|
||||
misa:
|
||||
rv32:
|
||||
mxl:
|
||||
shadow_type: ''
|
||||
pmp :
|
||||
reset-val: 123475
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
# Copyright (c) 2024 OpenHW Group
|
||||
# Copyright (c) 2024 Thales
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
# Author: Abdessamii Oukalrazqou
|
||||
|
||||
Zicond : True
|
||||
|
||||
m0 : True
|
||||
|
||||
I : True
|
||||
|
||||
Zcmp : False
|
||||
|
||||
RV32I Base Integer Instructions:
|
||||
Instructions :
|
||||
Integer_Register_Immediate_Operations:
|
||||
ADDI:
|
||||
Format: addi
|
||||
Loading…
Add table
Add a link
Reference in a new issue