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Disable floating point tests in CI update README

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Florian Zaruba 2018-10-13 16:26:20 +02:00
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4
README.md
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@ -81,6 +81,10 @@ $ make simc riscv-test-dir=$RISCV/riscv64-unknown-elf/bin riscv-test=pk target-o
> Be patient! RTL simulation is way slower than Spike. If you think that you ran into problems you can inspect the trace files.
### FPU Support
> There is preliminary support for floating point extensions F and D. At the moment floating point support will only be available in QuestaSim as the FPU is written in VHDL. This is likely to change. The floating point extensions can be enabled by setting `RVF` and `RVD` to `1'b1` in the `include/ariane_pkg.sv` file.
## FPGA Emulation
Coming.

38
ci/riscv-asm-tests.list
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@ -127,44 +127,6 @@ rv64um-v-divw
rv64um-v-divuw
rv64um-v-remw
rv64um-v-remuw
rv64uf-p-fadd
rv64uf-p-fclass
rv64uf-p-fcmp
rv64uf-p-fcvt
rv64uf-p-fcvt_w
rv64uf-p-fdiv
rv64uf-p-fmadd
rv64uf-p-fmin
rv64uf-p-ldst
rv64uf-p-move
rv64uf-p-recoding
rv64uf-v-fadd
rv64uf-v-fclass
rv64uf-v-fcmp
rv64uf-v-fcvt
rv64uf-v-fcvt_w
rv64uf-v-fdiv
rv64uf-v-fmadd
rv64uf-v-fmin
rv64uf-v-ldst
rv64uf-v-move
rv64uf-v-recoding
rv64ud-p-fadd
rv64ud-p-fclass
rv64ud-p-fcmp
rv64ud-p-fcvt
rv64ud-p-fcvt_w
rv64ud-p-fdiv
rv64ud-p-fmadd
rv64ud-p-fmin
rv64ud-v-fadd
rv64ud-v-fclass
rv64ud-v-fcmp
rv64ud-v-fcvt
rv64ud-v-fcvt_w
rv64ud-v-fdiv
rv64ud-v-fmadd
rv64ud-v-fmin
rv64ua-p-amoadd_d
rv64ua-p-amoadd_w
rv64ua-p-amoor_d