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https://github.com/openhwgroup/cva6.git
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🐛 Fix potential AXI ordering issue
This commit is contained in:
Florian Zaruba
parent
932ef8a351
commit
91d7babc87
4 changed files with 28 additions and 25 deletions
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@ -1,4 +1,4 @@
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## Buttons
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\## Buttons
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set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports cpu_resetn]
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## PMOD Header JC
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@ -55,7 +55,7 @@ open_run synth_1
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exec mkdir -p reports/
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exec rm -rf reports/*
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check_timing -file reports/$project.check_timing.rpt
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check_timing -verbose -file reports/$project.check_timing.rpt
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report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/$project.timing_WORST_100.rpt
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report_timing -nworst 1 -delay_type max -sort_by group -file reports/$project.timing.rpt
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report_utilization -hierarchical -file reports/$project.utilization.rpt
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@ -7,7 +7,7 @@ create_project $ipName . -part $partNumber
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set_property board_part $boardName [current_project]
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create_ip -name axi_gpio -vendor xilinx.com -library ip -module_name $ipName
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set_property -dict [list CONFIG.C_GPIO_WIDTH {8} CONFIG.C_GPIO2_WIDTH {8} CONFIG.C_IS_DUAL {1} CONFIG.C_ALL_INPUTS_2 {1} CONFIG.C_INTERRUPT_PRESENT {0} CONFIG.GPIO_BOARD_INTERFACE {led_8bits} CONFIG.GPIO2_BOARD_INTERFACE {dip_switches_8bits}] [get_ips $ipName]
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set_property -dict [list CONFIG.C_GPIO_WIDTH {8} CONFIG.C_GPIO2_WIDTH {8} CONFIG.C_IS_DUAL {1} CONFIG.C_ALL_INPUTS_2 {1} CONFIG.C_INTERRUPT_PRESENT {0}] [get_ips $ipName]
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generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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@ -101,8 +101,9 @@ module std_cache_subsystem #(
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// -----------------------
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// Arbitrate AXI Ports
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// -----------------------
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logic [1:0] w_select, w_id;
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logic full;
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logic [1:0] w_select, w_select_fifo, w_select_arbiter;
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logic w_fifo_empty;
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// AR Channel
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stream_arbiter #(
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@ -127,7 +128,7 @@ module std_cache_subsystem #(
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.clk_i,
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.rst_ni,
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.inp_data_i ( {axi_req_icache.aw, axi_req_bypass.aw, axi_req_data.aw} ),
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.inp_valid_i ( {axi_req_icache.aw_valid & ~full, axi_req_bypass.aw_valid & ~full, axi_req_data.aw_valid & ~full} ),
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.inp_valid_i ( {axi_req_icache.aw_valid, axi_req_bypass.aw_valid, axi_req_data.aw_valid} ),
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.inp_ready_o ( {axi_resp_icache.aw_ready, axi_resp_bypass.aw_ready, axi_resp_data.aw_ready} ),
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.oup_data_o ( axi_req_o.aw ),
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.oup_valid_o ( axi_req_o.aw_valid ),
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@ -139,42 +140,47 @@ module std_cache_subsystem #(
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always_comb begin
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w_select = 0;
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unique case (axi_req_o.aw.id)
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4'b1111: w_select = 0; // dcache
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4'b1100: w_select = 2; // dcache
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4'b1000, 4'b1001, 4'b1010, 4'b1011: w_select = 1; // bypass
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4'b0000: w_select = 2; // icache
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default: w_select = 0;
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default: w_select = 0; // icache
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endcase
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end
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// TODO(zarubaf): This causes a cycle delay, might be optimize-able, FALL_THROUGH
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// option made problems during synthesis (timing loop)
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fifo_v3 #(
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.FALL_THROUGH ( 1'b1 ),
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.DATA_WIDTH ( 2 ),
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// we can have a maximum of 4 oustanding transactions as each port is blocking
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.DEPTH ( 4 )
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) i_fifo_w_channel (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.flush_i ( 1'b0 ),
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.testmode_i ( 1'b0 ),
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.full_o ( full ),
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.empty_o ( ), // leave open
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.full_o ( ), // leave open
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.empty_o ( w_fifo_empty ),
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.usage_o ( ), // leave open
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.data_i ( w_select ),
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// a new transaction was requested
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.push_i ( axi_req_o.aw_valid & axi_resp_i.aw_ready & ~full ),
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// a new transaction was requested and granted
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.push_i ( axi_req_o.aw_valid & axi_resp_i.aw_ready ),
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// write ID to select the output MUX
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.data_o ( w_id ),
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.data_o ( w_select_fifo ),
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// transaction has finished
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.pop_i ( axi_req_o.w_valid & axi_resp_i.w_ready & axi_req_o.w.last )
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);
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// icache will never write so select it as default (e.g.: when no arbitration is active)
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// this is equal to setting it to zero
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assign w_select_arbiter = (w_fifo_empty) ? 0 : w_select_fifo;
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stream_mux #(
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.DATA_T ( ariane_axi::w_chan_t ),
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.N_INP ( 3 )
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) i_stream_mux_w (
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.inp_data_i ( {axi_req_icache.w, axi_req_bypass.w, axi_req_data.w} ),
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.inp_valid_i ( {axi_req_icache.w_valid, axi_req_bypass.w_valid, axi_req_data.w_valid} ),
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.inp_ready_o ( {axi_resp_icache.w_ready, axi_resp_bypass.w_ready, axi_resp_data.w_ready} ),
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.inp_sel_i ( w_id ),
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.inp_data_i ( {axi_req_data.w, axi_req_bypass.w, axi_req_icache.w} ),
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.inp_valid_i ( {axi_req_data.w_valid, axi_req_bypass.w_valid, axi_req_icache.w_valid} ),
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.inp_ready_o ( {axi_resp_data.w_ready, axi_resp_bypass.w_ready, axi_resp_icache.w_ready} ),
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.inp_sel_i ( w_select_arbiter ),
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.oup_data_o ( axi_req_o.w ),
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.oup_valid_o ( axi_req_o.w_valid ),
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.oup_ready_i ( axi_resp_i.w_ready )
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@ -183,7 +189,7 @@ module std_cache_subsystem #(
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// Route responses based on ID
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// 0000 -> I$
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// 10[00|10|01|11] -> Bypass
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// 1111 -> D$
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// 1100 -> D$
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// R Channel
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assign axi_resp_icache.r = axi_resp_i.r;
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assign axi_resp_bypass.r = axi_resp_i.r;
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@ -194,7 +200,7 @@ module std_cache_subsystem #(
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always_comb begin
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r_select = 0;
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unique case (axi_resp_i.r.id)
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4'b1111: r_select = 0; // dcache
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4'b1100: r_select = 0; // dcache
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4'b1000, 4'b1001, 4'b1010, 4'b1011: r_select = 1; // bypass
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4'b0000: r_select = 2; // icache
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default: r_select = 0;
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@ -221,7 +227,7 @@ module std_cache_subsystem #(
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always_comb begin
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b_select = 0;
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unique case (axi_resp_i.b.id)
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4'b1111: b_select = 0; // dcache
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4'b1100: b_select = 0; // dcache
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4'b1000, 4'b1001, 4'b1010, 4'b1011: b_select = 1; // bypass
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4'b0000: b_select = 2; // icache
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default: b_select = 0;
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@ -238,7 +244,6 @@ module std_cache_subsystem #(
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.oup_ready_i ( {axi_req_icache.b_ready, axi_req_bypass.b_ready, axi_req_data.b_ready} )
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);
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///////////////////////////////////////////////////////
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// assertions
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///////////////////////////////////////////////////////
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@ -266,6 +271,4 @@ module std_cache_subsystem #(
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`endif
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//pragma translate_on
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endmodule // std_cache_subsystem
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