Update device tree and fix possible LSU deadlock

Makefile

@@ -15,6 +15,8 @@ test_case ?= core_test
 questa_version ?=
 # verilator version
 verilator ?= verilator
+# traget option
+target-options ?=
 # Sources
 # Ariane PKG
 ariane_pkg := include/riscv_pkg.sv src/debug/dm_pkg.sv include/ariane_pkg.sv include/nbdcache_pkg.sv include/axi_if.sv
@@ -85,13 +87,13 @@ $(library):
 # +jtag_rbb_enable=1
 sim: build $(library)/ariane_dpi.so
 	vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
-	 +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=HIGH" -coverage -classdebug  +jtag_rbb_enable=1 \
-	 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" ${top_level}_optimized +permissive-off ++$(riscv-test)
+	 +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug  +jtag_rbb_enable=0 \
+	 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" ${top_level}_optimized +permissive-off ++$(riscv-test) ++$(target-options)
 
 simc: build $(library)/ariane_dpi.so
 	vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
-	 +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=HIGH" -coverage -classdebug +jtag_rbb_enable=1 \
-	 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" ${top_level}_optimized +permissive-off ++$(riscv-test)
+	 +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
+	 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" ${top_level}_optimized +permissive-off ++$(riscv-test) ++$(target-options)
 
 run-asm-tests: build
 	$(foreach test, $(riscv-ci-tests), vsim$(questa_version) +permissive -64 +BASEDIR=$(riscv-test-dir) +max-cycles=$(max_cycles) \

bootrom/ariane.dts

@@ -26,7 +26,7 @@
   };
   memory@80000000 {
     device_type = "memory";
-    reg = <0x0 0x80000000 0x0 0x80000000>;
+    reg = <0x0 0x80000000 0x0 0x1000000>;
   };
   soc {
     #address-cells = <2>;

bootrom/bootrom.sv

@@ -23,7 +23,7 @@ module bootrom (
     localparam int RomSize = 141;
 
     const logic [RomSize-1:0][63:0] mem = {
-        64'h_0064,
+        64'h0064,
         64'h65646e65_7478652d,
         64'h73747075_72726574,
         64'h6e690073_65676e61,
@@ -80,7 +80,7 @@ module bootrom (
         64'h02000000_00000000,
         64'h04000000_03000000,
         64'h00636f73_01000000,
-        64'h02000000_00000080,
+        64'h02000000_00000001,
         64'h00000000_00000080,
         64'h00000000_4b000000,
         64'h10000000_03000000,

src/icache.sv

@@ -261,6 +261,7 @@ module icache #(
                 // -------
                 // Hit
                 // -------
+                // disabling the icache just makes it fetch on every request
                 if (|hit && fetch_valid_i && (en_cache_i || (state_q != TAG_CMP))) begin
                     ready_o = 1'b1;
                     valid_o = 1'b1;
@@ -287,14 +288,21 @@ module icache #(
                     evict_way_d = hit;
                     // save tag
                     tag_d       = fetch_paddr_i[TAG_WIDTH+INDEX_WIDTH-1:INDEX_WIDTH];
-                    miss_o      = 1'b1;
+                    miss_o      = en_cache_i; // only count misses if the cache is enabled
                     // get way which to replace
-                    if (repl_w_random) begin
-                        evict_way_d = random_way;
-                        // shift the lfsr
-                        update_lfsr = 1'b1;
-                    end else if (!(|hit)) begin
-                        evict_way_d[repl_invalid] = 1'b1;
+                    // only if there is no hit we should fall back to real replacement. If there was a hit then
+                    // it means we are in bypass mode (!en_cache_i) and should update the cache-line with the most recent
+                    // value fetched from memory.
+                    if (!(|hit)) begin
+                        // all ways are currently full, randomly replace one of them
+                        if (repl_w_random) begin
+                            evict_way_d = random_way;
+                            // shift the lfsr
+                            update_lfsr = 1'b1;
+                        // there is still one cache-line which is not valid ~> replace that one
+                        end else begin
+                            evict_way_d[repl_invalid] = 1'b1;
+                        end
                     end
                 end
                 // if we didn't hit on the TLB we need to wait until the request has been completed

src/miss_handler.sv

@@ -946,13 +946,21 @@ module axi_adapter #(
                         state_d = COMPLETE_READ;
                     end
 
+                    // *work-around* so that the missing critical_word_valid is not violating the
+                    // protocol between miss_handler and load_unit. TODO(zarubaf) In general this needs proper
+                    // handling as an access fault
+                    if (axi.r_last && axi.r_resp != '0) begin
+                        critical_word_valid_o = 1'b1;
+                        // in the case of a bus erro (SIGBUS)r this is garbage anyway
+                        critical_word_o       = axi.r_data;
+                    end
+
                     // save the word
                     if (state_q == WAIT_R_VALID_MULTIPLE) begin
                         cache_line_d[index] = axi.r_data;
-
-                    end else
+                    end else begin
                         cache_line_d[0] = axi.r_data;
-
+                    end
                     // Decrease the counter
                     cnt_d = cnt_q - 1;
                 end