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csr_file: Fix propper setting of sd flag

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This commit is contained in:
Florian Zaruba 2019-05-14 17:00:06 +02:00
parent 3d09828552
commit 93e27812c7
3 changed files with 4 additions and 6 deletions
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2
include/riscv_pkg.sv
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@ -40,7 +40,7 @@ package riscv;
} xs_t;
typedef struct packed {
logic sd; // signal dirty - read-only - hardwired zero
logic sd; // signal dirty state - read-only
logic [62:36] wpri4; // writes preserved reads ignored
xlen_t sxl; // variable supervisor mode xlen - hardwired to zero
xlen_t uxl; // variable user mode xlen - hardwired to zero

2
src/commit_stage.sv
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@ -77,7 +77,7 @@ module commit_stage #(
always_comb begin : dirty_fp_state
dirty_fp_state_o = 1'b0;
for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
dirty_fp_state_o |= commit_ack_o[i] & (commit_instr_i[i].fu inside {FPU, FPU_VEC} || is_rd_fpr(commit_instr_i[0].op));
dirty_fp_state_o |= commit_ack_o[i] & (commit_instr_i[i].fu inside {FPU, FPU_VEC} || is_rd_fpr(commit_instr_i[i].op));
end
end

6
src/csr_regfile.sv
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@ -423,8 +423,6 @@ module csr_regfile #(
if (!FP_PRESENT) begin
mstatus_d.fs = riscv::Off;
end
// hardwired extension registers
mstatus_d.sd = (&mstatus_q.xs) | (&mstatus_q.fs);
// this instruction has side-effects
flush_o = 1'b1;
end
@ -466,8 +464,6 @@ module csr_regfile #(
riscv::CSR_MSTATUS: begin
mstatus_d = csr_wdata;
// hardwired zero registers
mstatus_d.sd = (&mstatus_q.xs) | (&mstatus_q.fs);
mstatus_d.xs = riscv::Off;
if (!FP_PRESENT) begin
mstatus_d.fs = riscv::Off;
@ -567,6 +563,8 @@ module csr_regfile #(
if (FP_PRESENT && (dirty_fp_state_csr || dirty_fp_state_i)) begin
mstatus_d.fs = riscv::Dirty;
end
// hardwired extension registers
mstatus_d.sd = (mstatus_q.xs == riscv::Dirty) | (mstatus_q.fs == riscv::Dirty);
// write the floating point status register
if (csr_write_fflags_i) begin