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[cva6_mmu]: always latch misaligned load/store exceptions (#2976)

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Prior to this change, the MMU only captured LSU misalignment faults when
Hypervisor extensions (RVH) were enabled. If RVH was disabled, misaligned
loads/stores would silently bypass exception handling, violating the
RISC-V privilege spec. This patch moves the [misaligned_ex_q] update
outside the (RVH) guard so that misaligned exceptions are always registered
and prioritized over translation.

Fixes rv32mi-ma_addr & rv32i-I-MISALIGN_LDST_01 tests.
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Bill94l 2025-05-22 07:23:26 +02:00 • committed by GitHub
parent c39333bdac
commit 94dfdb008b
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1 changed files with 7 additions and 7 deletions
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core/cva6_mmu/cva6_mmu.sv
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@ -749,13 +749,13 @@ module cva6_mmu
dtlb_hit_q <= dtlb_hit_n; dtlb_hit_q <= dtlb_hit_n;
lsu_is_store_q <= lsu_is_store_n; lsu_is_store_q <= lsu_is_store_n;
dtlb_is_page_q <= dtlb_is_page_n; dtlb_is_page_q <= dtlb_is_page_n;
misaligned_ex_q <= misaligned_ex_n;
if (CVA6Cfg.RVH) begin if (CVA6Cfg.RVH) begin
lsu_tinst_q <= lsu_tinst_n; lsu_tinst_q <= lsu_tinst_n;
hs_ld_st_inst_q <= hs_ld_st_inst_n; hs_ld_st_inst_q <= hs_ld_st_inst_n;
dtlb_gpte_q <= dtlb_gpte_n; dtlb_gpte_q <= dtlb_gpte_n;
lsu_gpaddr_q <= lsu_gpaddr_n; lsu_gpaddr_q <= lsu_gpaddr_n;
misaligned_ex_q <= misaligned_ex_n;
end end
end end
end end