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FPGA folder clean-up

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This commit is contained in:
Florian Zaruba 2018-11-18 15:32:41 +01:00
parent cb54ccfb7a
commit 9733876bfe
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GPG key ID: E742FFE8EC38A792
20 changed files with 503 additions and 1146 deletions
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2
Makefile
View file

@ -294,7 +294,7 @@ verilate_command := $(verilator)
verilate:
@echo "[Verilator] Building Model"
@$(verilate_command)
cd $(ver-library) && $(MAKE) -j${NUM_JOBS} -f Variane_testharness.mk > /dev/zero
cd $(ver-library) && $(MAKE) -j${NUM_JOBS} -f Variane_testharness.mk
sim-verilator: verilate
$(ver-library)/Variane_testharness $(elf-bin)

182
fpga/ariane.srcs/sources_1/ip/axi_protocol_checker_0/axi_protocol_checker_0.xci
View file

@ -1,182 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>axi_protocol_checker_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_protocol_checker" spirit:version="2.0"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
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</spirit:design>

129
fpga/ariane.srcs/sources_1/ip/axi_protocol_converter_0/axi_protocol_converter_0.xci
View file

@ -1,129 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SUPPORTS_READ">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SUPPORTS_USER_SIGNALS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SUPPORTS_WRITE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IGNORE_ID">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_PROTOCOL">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_PROTOCOL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRANSLATION_MODE">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axi_protocol_converter_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MI_PROTOCOL">AXI4LITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SI_PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRANSLATION_MODE">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD">digilentinc.com:genesys2:part0:1.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">17</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2018.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>

71
fpga/mig-genesys-2.ucf
View file

@ -1,71 +0,0 @@
NET "ddr3_dq[0]" LOC = "AD3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[1]" LOC = "AC2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[2]" LOC = "AC1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[3]" LOC = "AC5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[4]" LOC = "AC4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[5]" LOC = "AD6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[6]" LOC = "AE6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[7]" LOC = "AC7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[8]" LOC = "AF2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[9]" LOC = "AE1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[10]" LOC = "AF1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[11]" LOC = "AE4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[12]" LOC = "AE3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[13]" LOC = "AE5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[14]" LOC = "AF5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[15]" LOC = "AF6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[16]" LOC = "AJ4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[17]" LOC = "AH6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[18]" LOC = "AH5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[19]" LOC = "AH2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[20]" LOC = "AJ2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[21]" LOC = "AJ1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[22]" LOC = "AK1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[23]" LOC = "AJ3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[24]" LOC = "AF7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[25]" LOC = "AG7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[26]" LOC = "AJ6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[27]" LOC = "AK6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[28]" LOC = "AJ8" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[29]" LOC = "AK8" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[30]" LOC = "AK5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[31]" LOC = "AK4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dm[0]" LOC = "AD4" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_dm[1]" LOC = "AF3" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_dm[2]" LOC = "AH4" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_dm[3]" LOC = "AF8" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_p[0]" LOC = "AD2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_n[0]" LOC = "AD1" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_p[1]" LOC = "AG4" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_n[1]" LOC = "AG3" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_p[2]" LOC = "AG2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_n[2]" LOC = "AH1" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_p[3]" LOC = "AH7" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_n[3]" LOC = "AJ7" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_addr[14]" LOC = "AH9" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[13]" LOC = "AA12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[12]" LOC = "AB12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[11]" LOC = "AA8" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[10]" LOC = "AB8" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[9]" LOC = "Y11" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[8]" LOC = "Y10" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[7]" LOC = "AA11" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[6]" LOC = "AA10" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[5]" LOC = "AA13" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[4]" LOC = "AD9" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[3]" LOC = "AC10" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[2]" LOC = "AD8" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[1]" LOC = "AE8" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[0]" LOC = "AC12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ba[2]" LOC = "AC11" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ba[1]" LOC = "AB10" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ba[0]" LOC = "AE9" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ck_p[0]" LOC = "AB9" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ck_n[0]" LOC = "AC9" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ras_n" LOC = "AE11" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_cas_n" LOC = "AF11" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_we_n" LOC = "AG13" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_reset_n" LOC = "AG5" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = HIGH ;
NET "ddr3_cke[0]" LOC = "AJ9" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_odt[0]" LOC = "AK9" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_cs_n[0]" LOC = "AH12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;

423
fpga/src/ariane_peripherals.sv
View file

@ -14,7 +14,7 @@ module ariane_peripherals #(
parameter int AxiDataWidth = -1,
parameter int AxiIdWidth = -1,
parameter int AxiUserWidth = 1,
parameter bit DummyUART = 1,
parameter bit InclUART = 1,
parameter bit InclSPI = 0,
parameter bit InclEthernet = 0
) (
@ -49,7 +49,7 @@ module ariane_peripherals #(
);
// ---------------
// PLIC
// 1. PLIC
// ---------------
logic [ariane_soc::NumSources-1:0] irq_sources;
@ -148,12 +148,10 @@ module ariane_peripherals #(
);
plic #(
.ADDR_WIDTH ( 32 ),
.DATA_WIDTH ( 32 ),
.ID_BITWIDTH ( 3 ), // TODO (zarubaf): Find propper width
.PARAMETER_BITWIDTH ( 3 ), // TODO (zarubaf): Find propper width
.NUM_TARGETS ( ariane_soc::NumTargets ),
.NUM_SOURCES ( ariane_soc::NumSources )
.ID_BITWIDTH ( ariane_soc::PLICIdWidth ),
.PARAMETER_BITWIDTH ( ariane_soc::ParameterBitwidth ),
.NUM_TARGETS ( ariane_soc::NumTargets ),
.NUM_SOURCES ( ariane_soc::NumSources )
) i_plic (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
@ -163,7 +161,7 @@ module ariane_peripherals #(
);
// ---------------
// UART
// 2. UART
// ---------------
logic uart_penable;
logic uart_pwrite;
@ -240,24 +238,7 @@ module ariane_peripherals #(
.PSLVERR ( uart_pslverr )
);
if (DummyUART) begin
/* pragma translate_off */
`ifndef VERILATOR
mock_uart i_mock_uart (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.penable_i ( uart_penable ),
.pwrite_i ( uart_pwrite ),
.paddr_i ( uart_paddr ),
.psel_i ( uart_psel ),
.pwdata_i ( uart_pwdata ),
.prdata_o ( uart_prdata ),
.pready_o ( uart_pready ),
.pslverr_o ( uart_pslverr )
);
/* pragma translate_on */
`endif
end else begin
if (InclUART) begin : gen_uart
apb_uart i_apb_uart (
.CLK ( clk_i ),
.RSTN ( rst_ni ),
@ -281,184 +262,28 @@ module ariane_peripherals #(
.SIN ( rx_i ),
.SOUT ( tx_o )
);
end
// ---------------
// Ethernet
// ---------------
wire mdio_i, mdio_o, mdio_t;
if (InclEthernet) begin : gen_ethernet
logic [3:0] s_axi_eth_awid;
logic [12:0] s_axi_eth_awaddr;
logic [7:0] s_axi_eth_awlen;
logic [2:0] s_axi_eth_awsize;
logic [1:0] s_axi_eth_awburst;
logic [3:0] s_axi_eth_awcache;
logic s_axi_eth_awvalid;
logic s_axi_eth_awready;
logic [31:0] s_axi_eth_wdata;
logic [3:0] s_axi_eth_wstrb;
logic s_axi_eth_wlast;
logic s_axi_eth_wvalid;
logic s_axi_eth_wready;
logic [3:0] s_axi_eth_bid;
logic [1:0] s_axi_eth_bresp;
logic s_axi_eth_bvalid;
logic s_axi_eth_bready;
logic [3:0] s_axi_eth_arid;
logic [12:0] s_axi_eth_araddr;
logic [7:0] s_axi_eth_arlen;
logic [2:0] s_axi_eth_arsize;
logic [1:0] s_axi_eth_arburst;
logic [3:0] s_axi_eth_arcache;
logic s_axi_eth_arvalid;
logic s_axi_eth_arready;
logic [3:0] s_axi_eth_rid;
logic [31:0] s_axi_eth_rdata;
logic [1:0] s_axi_eth_rresp;
logic s_axi_eth_rlast;
logic s_axi_eth_rvalid;
axi_dwidth_converter_0 i_axi_dwidth_converter_0 (
.s_axi_aclk ( clk_i ), // input wire s_axi_aclk
.s_axi_aresetn ( rst_ni ), // input wire s_axi_aresetn
.s_axi_awid (s_axi_awid ), // input wire [3 : 0] s_axi_awid
.s_axi_awaddr (s_axi_awaddr ), // input wire [31 : 0] s_axi_awaddr
.s_axi_awlen (s_axi_awlen ), // input wire [7 : 0] s_axi_awlen
.s_axi_awsize (s_axi_awsize ), // input wire [2 : 0] s_axi_awsize
.s_axi_awburst (s_axi_awburst ), // input wire [1 : 0] s_axi_awburst
.s_axi_awlock (s_axi_awlock ), // input wire [0 : 0] s_axi_awlock
.s_axi_awcache (s_axi_awcache ), // input wire [3 : 0] s_axi_awcache
.s_axi_awprot (s_axi_awprot ), // input wire [2 : 0] s_axi_awprot
.s_axi_awregion(s_axi_awregion), // input wire [3 : 0] s_axi_awregion
.s_axi_awqos (s_axi_awqos ), // input wire [3 : 0] s_axi_awqos
.s_axi_awvalid (s_axi_awvalid ), // input wire s_axi_awvalid
.s_axi_awready (s_axi_awready ), // output wire s_axi_awready
.s_axi_wdata (s_axi_wdata ), // input wire [63 : 0] s_axi_wdata
.s_axi_wstrb (s_axi_wstrb ), // input wire [7 : 0] s_axi_wstrb
.s_axi_wlast (s_axi_wlast ), // input wire s_axi_wlast
.s_axi_wvalid (s_axi_wvalid ), // input wire s_axi_wvalid
.s_axi_wready (s_axi_wready ), // output wire s_axi_wready
.s_axi_bid (s_axi_bid ), // output wire [3 : 0] s_axi_bid
.s_axi_bresp (s_axi_bresp ), // output wire [1 : 0] s_axi_bresp
.s_axi_bvalid (s_axi_bvalid ), // output wire s_axi_bvalid
.s_axi_bready (s_axi_bready ), // input wire s_axi_bready
.s_axi_arid (s_axi_arid ), // input wire [3 : 0] s_axi_arid
.s_axi_araddr (s_axi_araddr ), // input wire [31 : 0] s_axi_araddr
.s_axi_arlen (s_axi_arlen ), // input wire [7 : 0] s_axi_arlen
.s_axi_arsize (s_axi_arsize ), // input wire [2 : 0] s_axi_arsize
.s_axi_arburst (s_axi_arburst ), // input wire [1 : 0] s_axi_arburst
.s_axi_arlock (s_axi_arlock ), // input wire [0 : 0] s_axi_arlock
.s_axi_arcache (s_axi_arcache ), // input wire [3 : 0] s_axi_arcache
.s_axi_arprot (s_axi_arprot ), // input wire [2 : 0] s_axi_arprot
.s_axi_arregion(s_axi_arregion), // input wire [3 : 0] s_axi_arregion
.s_axi_arqos (s_axi_arqos ), // input wire [3 : 0] s_axi_arqos
.s_axi_arvalid (s_axi_arvalid ), // input wire s_axi_arvalid
.s_axi_arready (s_axi_arready ), // output wire s_axi_arready
.s_axi_rid (s_axi_rid ), // output wire [3 : 0] s_axi_rid
.s_axi_rdata (s_axi_rdata ), // output wire [63 : 0] s_axi_rdata
.s_axi_rresp (s_axi_rresp ), // output wire [1 : 0] s_axi_rresp
.s_axi_rlast (s_axi_rlast ), // output wire s_axi_rlast
.s_axi_rvalid (s_axi_rvalid ), // output wire s_axi_rvalid
.s_axi_rready (s_axi_rready ), // input wire s_axi_rready
.m_axi_awaddr (m_axi_awaddr ), // output wire [31 : 0] m_axi_awaddr
.m_axi_awlen (m_axi_awlen ), // output wire [7 : 0] m_axi_awlen
.m_axi_awsize (m_axi_awsize ), // output wire [2 : 0] m_axi_awsize
.m_axi_awburst (m_axi_awburst ), // output wire [1 : 0] m_axi_awburst
.m_axi_awlock (m_axi_awlock ), // output wire [0 : 0] m_axi_awlock
.m_axi_awcache (m_axi_awcache ), // output wire [3 : 0] m_axi_awcache
.m_axi_awprot (m_axi_awprot ), // output wire [2 : 0] m_axi_awprot
.m_axi_awregion(m_axi_awregion), // output wire [3 : 0] m_axi_awregion
.m_axi_awqos (m_axi_awqos ), // output wire [3 : 0] m_axi_awqos
.m_axi_awvalid (m_axi_awvalid ), // output wire m_axi_awvalid
.m_axi_awready (m_axi_awready ), // input wire m_axi_awready
.m_axi_wdata (m_axi_wdata ), // output wire [31 : 0] m_axi_wdata
.m_axi_wstrb (m_axi_wstrb ), // output wire [3 : 0] m_axi_wstrb
.m_axi_wlast (m_axi_wlast ), // output wire m_axi_wlast
.m_axi_wvalid (m_axi_wvalid ), // output wire m_axi_wvalid
.m_axi_wready (m_axi_wready ), // input wire m_axi_wready
.m_axi_bresp (m_axi_bresp ), // input wire [1 : 0] m_axi_bresp
.m_axi_bvalid (m_axi_bvalid ), // input wire m_axi_bvalid
.m_axi_bready (m_axi_bready ), // output wire m_axi_bready
.m_axi_araddr (m_axi_araddr ), // output wire [31 : 0] m_axi_araddr
.m_axi_arlen (m_axi_arlen ), // output wire [7 : 0] m_axi_arlen
.m_axi_arsize (m_axi_arsize ), // output wire [2 : 0] m_axi_arsize
.m_axi_arburst (m_axi_arburst ), // output wire [1 : 0] m_axi_arburst
.m_axi_arlock (m_axi_arlock ), // output wire [0 : 0] m_axi_arlock
.m_axi_arcache (m_axi_arcache ), // output wire [3 : 0] m_axi_arcache
.m_axi_arprot (m_axi_arprot ), // output wire [2 : 0] m_axi_arprot
.m_axi_arregion(m_axi_arregion), // output wire [3 : 0] m_axi_arregion
.m_axi_arqos (m_axi_arqos ), // output wire [3 : 0] m_axi_arqos
.m_axi_arvalid (m_axi_arvalid ), // output wire m_axi_arvalid
.m_axi_arready (m_axi_arready ), // input wire m_axi_arready
.m_axi_rdata (m_axi_rdata ), // input wire [31 : 0] m_axi_rdata
.m_axi_rresp (m_axi_rresp ), // input wire [1 : 0] m_axi_rresp
.m_axi_rlast (m_axi_rlast ), // input wire m_axi_rlast
.m_axi_rvalid (m_axi_rvalid ), // input wire m_axi_rvalid
.m_axi_rready (m_axi_rready ) // output wire m_axi_rready
);
xlnx_axi_ethernetlite i_xlnx_axi_ethernetlite (
.s_axi_aclk ( clk_i ),
.s_axi_aresetn ( rst_ni ),
.ip2intc_irpt ( irq_sources[2] ),
.s_axi_awid ( s_axi_eth_awid ),
.s_axi_awaddr ( s_axi_eth_awaddr ),
.s_axi_awlen ( s_axi_eth_awlen ),
.s_axi_awsize ( s_axi_eth_awsize ),
.s_axi_awburst ( s_axi_eth_awburst ),
.s_axi_awcache ( s_axi_eth_awcache ),
.s_axi_awvalid ( s_axi_eth_awvalid ),
.s_axi_awready ( s_axi_eth_awready ),
.s_axi_wdata ( s_axi_eth_wdata ),
.s_axi_wstrb ( s_axi_eth_wstrb ),
.s_axi_wlast ( s_axi_eth_wlast ),
.s_axi_wvalid ( s_axi_eth_wvalid ),
.s_axi_wready ( s_axi_eth_wready ),
.s_axi_bid ( s_axi_eth_bid ),
.s_axi_bresp ( s_axi_eth_bresp ),
.s_axi_bvalid ( s_axi_eth_bvalid ),
.s_axi_bready ( s_axi_eth_bready ),
.s_axi_arid ( s_axi_eth_arid ),
.s_axi_araddr ( s_axi_eth_araddr ),
.s_axi_arlen ( s_axi_eth_arlen ),
.s_axi_arsize ( s_axi_eth_arsize ),
.s_axi_arburst ( s_axi_eth_arburst ),
.s_axi_arcache ( s_axi_eth_arcache ),
.s_axi_arvalid ( s_axi_eth_arvalid ),
.s_axi_arready ( s_axi_eth_arready ),
.s_axi_rid ( s_axi_eth_rid ),
.s_axi_rdata ( s_axi_eth_rdata ),
.s_axi_rresp ( s_axi_eth_rresp ),
.s_axi_rlast ( s_axi_eth_rlast ),
.s_axi_rvalid ( s_axi_eth_rvalid ),
.s_axi_rready ( s_axi_eth_rready ),
.phy_tx_clk ( eth_txck ),
.phy_rx_clk ( eth_rxck ),
.phy_crs ( 1'b0 ),
.phy_dv ( eth_rxctl ),
.phy_rx_data ( eth_rxd ),
.phy_col ( 1'b0 ),
.phy_rx_er ( 1'b0 ),
.phy_rst_n ( eth_rst_n ),
.phy_tx_en ( eth_tx_en ),
.phy_tx_data ( eth_txd ),
.phy_mdio_i ( mdio_i ),
.phy_mdio_o ( mdio_o ),
.phy_mdio_t ( mdio_t ),
.phy_mdc ( eth_mdc )
);
IOBUF mdio_io_iobuf (.I (mdio_o), .IO(mdio), .O (mdio_i), .T (mdio_t));
end else begin
/* pragma translate_off */
`ifndef VERILATOR
mock_uart i_mock_uart (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.penable_i ( uart_penable ),
.pwrite_i ( uart_pwrite ),
.paddr_i ( uart_paddr ),
.psel_i ( uart_psel ),
.pwdata_i ( uart_pwdata ),
.prdata_o ( uart_prdata ),
.pready_o ( uart_pready ),
.pslverr_o ( uart_pslverr )
);
/* pragma translate_on */
`endif
end
// ---------------
// SPI
// 3. SPI
// ---------------
if (InclSPI) begin : gen_spi
logic [31:0] s_axi_spi_awaddr;
logic [7:0] s_axi_spi_awlen;
@ -496,7 +321,7 @@ module ariane_peripherals #(
logic s_axi_spi_rvalid;
logic s_axi_spi_rready;
axi_dwidth_converter_0 i_axi_dwidth_converter_spi (
xlnx_axi_clock_converter i_xlnx_axi_clock_converter_spi (
.s_axi_aclk ( clk_i ),
.s_axi_aresetn ( rst_ni ),
@ -577,7 +402,7 @@ module ariane_peripherals #(
.m_axi_rready ( s_axi_spi_rready )
);
axi_quad_spi_0 i_axi_spi (
xlnx_axi_quad_spi i_xlnx_axi_quad_spi (
.ext_spi_clk ( clk_i ),
.s_axi4_aclk ( clk_i ),
.s_axi4_aresetn ( rst_ni ),
@ -648,18 +473,194 @@ module ariane_peripherals #(
assign spi.r_resp = axi_pkg::RESP_SLVERR;
assign spi.r_data = 'hdeadbeef;
assign spi.r_last = 1'b1;
end
// assign s_axi_spi_awready = 1'b1;
// assign s_axi_spi_wready = 1'b1;
// ---------------
// 4. Ethernet
// ---------------
if (InclEthernet) begin : gen_ethernet
wire mdio_i, mdio_o, mdio_t;
logic [3:0] s_axi_eth_awid;
logic [31:0] s_axi_eth_awaddr;
logic [7:0] s_axi_eth_awlen;
logic [2:0] s_axi_eth_awsize;
logic [1:0] s_axi_eth_awburst;
logic [3:0] s_axi_eth_awcache;
logic s_axi_eth_awvalid;
logic s_axi_eth_awready;
logic [31:0] s_axi_eth_wdata;
logic [3:0] s_axi_eth_wstrb;
logic s_axi_eth_wlast;
logic s_axi_eth_wvalid;
logic s_axi_eth_wready;
logic [3:0] s_axi_eth_bid;
logic [1:0] s_axi_eth_bresp;
logic s_axi_eth_bvalid;
logic s_axi_eth_bready;
logic [3:0] s_axi_eth_arid;
logic [31:0] s_axi_eth_araddr;
logic [7:0] s_axi_eth_arlen;
logic [2:0] s_axi_eth_arsize;
logic [1:0] s_axi_eth_arburst;
logic [3:0] s_axi_eth_arcache;
logic s_axi_eth_arvalid;
logic s_axi_eth_arready;
logic [3:0] s_axi_eth_rid;
logic [31:0] s_axi_eth_rdata;
logic [1:0] s_axi_eth_rresp;
logic s_axi_eth_rlast;
logic s_axi_eth_rvalid;
// assign s_axi_spi_bresp = '0;
// assign s_axi_spi_bvalid = 1'b1;
assign s_axi_eth_awid = '0;
assign s_axi_eth_arid = '0;
// assign s_axi_spi_arready = 1'b1;
// assign s_axi_spi_rdata = '0;
// assign s_axi_spi_rresp = '0;
// assign s_axi_spi_rlast = 1'b1;
// assign s_axi_spi_rvalid = 1'b1;
// system-bus is 64-bit, convert down to 32 bit
xlnx_axi_clock_converter i_xlnx_axi_clock_converter_ethernet (
.s_axi_aclk ( clk_i ),
.s_axi_aresetn ( rst_ni ),
.s_axi_awid ( ethernet.aw_id ),
.s_axi_awaddr ( ethernet.aw_addr[31:0] ),
.s_axi_awlen ( ethernet.aw_len ),
.s_axi_awsize ( ethernet.aw_size ),
.s_axi_awburst ( ethernet.aw_burst ),
.s_axi_awlock ( ethernet.aw_lock ),
.s_axi_awcache ( ethernet.aw_cache ),
.s_axi_awprot ( ethernet.aw_prot ),
.s_axi_awregion ( ethernet.aw_region ),
.s_axi_awqos ( ethernet.aw_qos ),
.s_axi_awvalid ( ethernet.aw_valid ),
.s_axi_awready ( ethernet.aw_ready ),
.s_axi_wdata ( ethernet.w_data ),
.s_axi_wstrb ( ethernet.w_strb ),
.s_axi_wlast ( ethernet.w_last ),
.s_axi_wvalid ( ethernet.w_valid ),
.s_axi_wready ( ethernet.w_ready ),
.s_axi_bid ( ethernet.b_id ),
.s_axi_bresp ( ethernet.b_resp ),
.s_axi_bvalid ( ethernet.b_valid ),
.s_axi_bready ( ethernet.b_ready ),
.s_axi_arid ( ethernet.ar_id ),
.s_axi_araddr ( ethernet.ar_addr[31:0] ),
.s_axi_arlen ( ethernet.ar_len ),
.s_axi_arsize ( ethernet.ar_size ),
.s_axi_arburst ( ethernet.ar_burst ),
.s_axi_arlock ( ethernet.ar_lock ),
.s_axi_arcache ( ethernet.ar_cache ),
.s_axi_arprot ( ethernet.ar_prot ),
.s_axi_arregion ( ethernet.ar_region ),
.s_axi_arqos ( ethernet.ar_qos ),
.s_axi_arvalid ( ethernet.ar_valid ),
.s_axi_arready ( ethernet.ar_ready ),
.s_axi_rid ( ethernet.r_id ),
.s_axi_rdata ( ethernet.r_data ),
.s_axi_rresp ( ethernet.r_resp ),
.s_axi_rlast ( ethernet.r_last ),
.s_axi_rvalid ( ethernet.r_valid ),
.s_axi_rready ( ethernet.r_ready ),
.m_axi_awaddr ( s_axi_eth_awaddr ),
.m_axi_awlen ( s_axi_eth_awlen ),
.m_axi_awsize ( s_axi_eth_awsize ),
.m_axi_awburst ( s_axi_eth_awburst ),
.m_axi_awlock ( ),
.m_axi_awcache ( s_axi_eth_awcache ),
.m_axi_awprot ( ),
.m_axi_awregion ( ),
.m_axi_awqos ( ),
.m_axi_awvalid ( s_axi_eth_awvalid ),
.m_axi_awready ( s_axi_eth_awready ),
.m_axi_wdata ( s_axi_eth_wdata ),
.m_axi_wstrb ( s_axi_eth_wstrb ),
.m_axi_wlast ( s_axi_eth_wlast ),
.m_axi_wvalid ( s_axi_eth_wvalid ),
.m_axi_wready ( s_axi_eth_wready ),
.m_axi_bresp ( s_axi_eth_bresp ),
.m_axi_bvalid ( s_axi_eth_bvalid ),
.m_axi_bready ( s_axi_eth_bready ),
.m_axi_araddr ( s_axi_eth_araddr ),
.m_axi_arlen ( s_axi_eth_arlen ),
.m_axi_arsize ( s_axi_eth_arsize ),
.m_axi_arburst ( s_axi_eth_arburst ),
.m_axi_arlock ( ),
.m_axi_arcache ( s_axi_eth_arcache ),
.m_axi_arprot ( ),
.m_axi_arregion ( ),
.m_axi_arqos ( ),
.m_axi_arvalid ( s_axi_eth_arvalid ),
.m_axi_arready ( s_axi_eth_arready ),
.m_axi_rdata ( s_axi_eth_rdata ),
.m_axi_rresp ( s_axi_eth_rresp ),
.m_axi_rlast ( s_axi_eth_rlast ),
.m_axi_rvalid ( s_axi_eth_rvalid ),
.m_axi_rready ( m_axi_rready )
);
xlnx_axi_ethernetlite i_xlnx_axi_ethernetlite (
.s_axi_aclk ( clk_i ),
.s_axi_aresetn ( rst_ni ),
.ip2intc_irpt ( irq_sources[2] ),
.s_axi_awid ( s_axi_eth_awid ),
.s_axi_awaddr ( s_axi_eth_awaddr[12:0] ),
.s_axi_awlen ( s_axi_eth_awlen ),
.s_axi_awsize ( s_axi_eth_awsize ),
.s_axi_awburst ( s_axi_eth_awburst ),
.s_axi_awcache ( s_axi_eth_awcache ),
.s_axi_awvalid ( s_axi_eth_awvalid ),
.s_axi_awready ( s_axi_eth_awready ),
.s_axi_wdata ( s_axi_eth_wdata ),
.s_axi_wstrb ( s_axi_eth_wstrb ),
.s_axi_wlast ( s_axi_eth_wlast ),
.s_axi_wvalid ( s_axi_eth_wvalid ),
.s_axi_wready ( s_axi_eth_wready ),
.s_axi_bid ( s_axi_eth_bid ),
.s_axi_bresp ( s_axi_eth_bresp ),
.s_axi_bvalid ( s_axi_eth_bvalid ),
.s_axi_bready ( s_axi_eth_bready ),
.s_axi_arid ( s_axi_eth_arid ),
.s_axi_araddr ( s_axi_eth_araddr[12:0] ),
.s_axi_arlen ( s_axi_eth_arlen ),
.s_axi_arsize ( s_axi_eth_arsize ),
.s_axi_arburst ( s_axi_eth_arburst ),
.s_axi_arcache ( s_axi_eth_arcache ),
.s_axi_arvalid ( s_axi_eth_arvalid ),
.s_axi_arready ( s_axi_eth_arready ),
.s_axi_rid ( s_axi_eth_rid ),
.s_axi_rdata ( s_axi_eth_rdata ),
.s_axi_rresp ( s_axi_eth_rresp ),
.s_axi_rlast ( s_axi_eth_rlast ),
.s_axi_rvalid ( s_axi_eth_rvalid ),
.s_axi_rready ( s_axi_eth_rready ),
.phy_tx_clk ( eth_txck ),
.phy_rx_clk ( eth_rxck ),
.phy_crs ( 1'b0 ),
.phy_dv ( eth_rxctl ),
.phy_rx_data ( eth_rxd ),
.phy_col ( 1'b0 ),
.phy_rx_er ( 1'b0 ),
.phy_rst_n ( eth_rst_n ),
.phy_tx_en ( eth_tx_en ),
.phy_tx_data ( eth_txd ),
.phy_mdio_i ( mdio_i ),
.phy_mdio_o ( mdio_o ),
.phy_mdio_t ( mdio_t ),
.phy_mdc ( eth_mdc )
);
IOBUF mdio_io_iobuf (.I (mdio_o), .IO(mdio), .O (mdio_i), .T (mdio_t));
end else begin
assign irq_sources [2] = 1'b0;
assign ethernet.aw_ready = 1'b1;
assign ethernet.ar_ready = 1'b1;
assign ethernet.w_ready = 1'b1;
assign ethernet.b_valid = ethernet.aw_valid;
assign ethernet.b_id = ethernet.aw_id;
assign ethernet.b_resp = axi_pkg::RESP_SLVERR;
assign ethernet.b_user = '0;
assign ethernet.r_valid = ethernet.ar_valid;
assign ethernet.r_resp = axi_pkg::RESP_SLVERR;
assign ethernet.r_data = 'hdeadbeef;
assign ethernet.r_last = 1'b1;
end
endmodule

468
fpga/src/ariane_xilinx.sv
View file

@ -10,32 +10,7 @@
// Xilinx FPGA top-level
module ariane_xilinx (
`ifdef VCU118
input wire c0_sys_clk_p , // 250 MHz Clock for DDR
input wire c0_sys_clk_n , // 250 MHz Clock for DDR
input wire sys_clk_p , // 100 MHz Clock for PCIe
input wire sys_clk_n , // 100 MHz Clock for PCIE
input wire sys_rst_n , // PCIe Reset
input logic cpu_reset , // CPU subsystem reset
output wire [16 : 0] c0_ddr4_adr ,
output wire [1 : 0] c0_ddr4_ba ,
output wire [0 : 0] c0_ddr4_cke ,
output wire [0 : 0] c0_ddr4_cs_n ,
inout wire [7 : 0] c0_ddr4_dm_dbi_n,
inout wire [63 : 0] c0_ddr4_dq ,
inout wire [7 : 0] c0_ddr4_dqs_c ,
inout wire [7 : 0] c0_ddr4_dqs_t ,
output wire [0 : 0] c0_ddr4_odt ,
output wire [0 : 0] c0_ddr4_bg ,
output wire c0_ddr4_reset_n ,
output wire c0_ddr4_act_n ,
output wire [0 : 0] c0_ddr4_ck_c ,
output wire [0 : 0] c0_ddr4_ck_t ,
output wire [7 : 0] pci_exp_txp ,
output wire [7 : 0] pci_exp_txn ,
input wire [7 : 0] pci_exp_rxp ,
input wire [7 : 0] pci_exp_rxn ,
`elsif GENESYSII
`ifdef GENESYSII
input logic sys_clk_p ,
input logic sys_clk_n ,
input logic cpu_resetn ,
@ -54,9 +29,45 @@ module ariane_xilinx (
output logic [ 0:0] ddr3_cs_n ,
output logic [ 3:0] ddr3_dm ,
output logic [ 0:0] ddr3_odt ,
input wire eth_txck ,
input wire eth_rxck ,
input wire eth_rxctl ,
input wire [3:0] eth_rxd ,
output wire eth_rst_n ,
output wire eth_tx_en ,
output wire [3:0] eth_txd ,
inout wire phy_mdio ,
output logic eth_mdc ,
inout mdio ,
output mdc ,
output logic [ 7:0] led ,
input logic [ 7:0] sw ,
output logic fan_pwm ,
`elsif VCU118
input wire c0_sys_clk_p , // 250 MHz Clock for DDR
input wire c0_sys_clk_n , // 250 MHz Clock for DDR
input wire sys_clk_p , // 100 MHz Clock for PCIe
input wire sys_clk_n , // 100 MHz Clock for PCIE
input wire sys_rst_n , // PCIe Reset
input logic cpu_reset , // CPU subsystem reset
output wire [16:0] c0_ddr4_adr ,
output wire [1:0] c0_ddr4_ba ,
output wire [0:0] c0_ddr4_cke ,
output wire [0:0] c0_ddr4_cs_n ,
inout wire [7:0] c0_ddr4_dm_dbi_n,
inout wire [63:0] c0_ddr4_dq ,
inout wire [7:0] c0_ddr4_dqs_c ,
inout wire [7:0] c0_ddr4_dqs_t ,
output wire [0:0] c0_ddr4_odt ,
output wire [0:0] c0_ddr4_bg ,
output wire c0_ddr4_reset_n ,
output wire c0_ddr4_act_n ,
output wire [0:0] c0_ddr4_ck_c ,
output wire [0:0] c0_ddr4_ck_t ,
output wire [7:0] pci_exp_txp ,
output wire [7:0] pci_exp_txn ,
input wire [7:0] pci_exp_rxp ,
input wire [7:0] pci_exp_rxn ,
`endif
// SPI
output logic spi_mosi ,
@ -78,12 +89,12 @@ module ariane_xilinx (
);
// 24 MByte in 8 byte words
localparam NumWords = (24 * 1024 * 1024) / 8;
localparam NBSlave = 4; // debug, Instruction fetch, data bypass, data
localparam NBSlave = 2; // debug, ariane
localparam CacheStartAddr = (1 << 31);
localparam AxiAddrWidth = 64;
localparam AxiDataWidth = 64;
localparam AxiIdWidthMaster = 2;
localparam AxiIdWidthSlaves = AxiIdWidthMaster + $clog2(NBSlave); // 4
localparam AxiIdWidthMaster = 4;
localparam AxiIdWidthSlaves = AxiIdWidthMaster + $clog2(NBSlave); // 5
localparam AxiUserWidth = 1;
AXI_BUS #(
@ -100,13 +111,6 @@ AXI_BUS #(
.AXI_USER_WIDTH ( AxiUserWidth )
) dummy_slave();
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidthMaster ),
.AXI_USER_WIDTH ( AxiUserWidth )
) slave_slice[NBSlave-1:0]();
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
@ -170,74 +174,6 @@ assign ndmreset_n = ~ndmreset ;
logic [NBSlave-1:0] pc_asserted;
// Slice the AXI Masters (slave ports on the XBar)
for (genvar i = 0; i < NBSlave; i++) begin : slave_cut_gen
axi_cut #(
.ADDR_WIDTH ( AxiAddrWidth ),
.DATA_WIDTH ( AxiDataWidth ),
.ID_WIDTH ( AxiIdWidthMaster ),
.USER_WIDTH ( AxiUserWidth )
) i_axi_cut (
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
.in ( slave_slice[i] ),
.out ( slave[i] )
);
if (ariane_soc::GenProtocolChecker) begin : gen_protocol_check
axi_protocol_checker_0 i_axi_protocol_checker (
.pc_status( ), // debug probe
.pc_asserted(pc_asserted[i]),
.aclk(clk),
.aresetn(ndmreset_n),
.pc_axi_awid(slave[i].aw_id),
.pc_axi_awaddr(slave[i].aw_addr),
.pc_axi_awlen(slave[i].aw_len),
.pc_axi_awsize(slave[i].aw_size),
.pc_axi_awburst(slave[i].aw_burst),
.pc_axi_awlock(slave[i].aw_lock),
.pc_axi_awcache(slave[i].aw_cache),
.pc_axi_awprot(slave[i].aw_prot),
.pc_axi_awqos(slave[i].aw_qos),
.pc_axi_awregion(slave[i].aw_region),
.pc_axi_awready(slave[i].aw_ready),
.pc_axi_awvalid(slave[i].aw_valid),
.pc_axi_awuser(slave[i].aw_user),
.pc_axi_wlast(slave[i].w_last),
.pc_axi_wdata(slave[i].w_data),
.pc_axi_wstrb(slave[i].w_strb),
.pc_axi_wuser(slave[i].w_user),
.pc_axi_wvalid(slave[i].w_valid),
.pc_axi_wready(slave[i].w_ready),
.pc_axi_bid(slave[i].b_id),
.pc_axi_bresp(slave[i].b_resp),
.pc_axi_buser(slave[i].b_user),
.pc_axi_bvalid(slave[i].b_valid),
.pc_axi_bready(slave[i].b_ready),
.pc_axi_arid(slave[i].ar_id),
.pc_axi_araddr(slave[i].ar_addr),
.pc_axi_arlen(slave[i].ar_len),
.pc_axi_arsize(slave[i].ar_size),
.pc_axi_arburst(slave[i].ar_burst),
.pc_axi_arlock(slave[i].ar_lock),
.pc_axi_arcache(slave[i].ar_cache),
.pc_axi_arprot(slave[i].ar_prot),
.pc_axi_arqos(slave[i].ar_qos),
.pc_axi_arregion(slave[i].ar_region),
.pc_axi_aruser(slave[i].ar_user),
.pc_axi_arvalid(slave[i].ar_valid),
.pc_axi_arready(slave[i].ar_ready),
.pc_axi_rid(slave[i].r_id),
.pc_axi_rlast(slave[i].r_last),
.pc_axi_rdata(slave[i].r_data),
.pc_axi_rresp(slave[i].r_resp),
.pc_axi_ruser(slave[i].r_user),
.pc_axi_rvalid(slave[i].r_valid),
.pc_axi_rready(slave[i].r_ready)
);
end
end
// ---------------
// AXI Xbar
// ---------------
@ -264,26 +200,18 @@ axi_node_wrap_with_slices #(
ariane_soc::PLICBase,
ariane_soc::UARTBase,
ariane_soc::SPIBase,
`ifdef INCL_SRAM
ariane_soc::SRAMBase,
ariane_soc::EthernetBase,
ariane_soc::DRAMBase
`else
ariane_soc::DRAMBase
`endif
}),
.end_addr_i ({
ariane_soc::DebugBase + ariane_soc::DebugLength - 1,
ariane_soc::ROMBase + ariane_soc::ROMLength - 1,
ariane_soc::CLINTBase + ariane_soc::CLINTLength - 1,
ariane_soc::PLICBase + ariane_soc::PLICLength - 1,
ariane_soc::UARTBase + ariane_soc::UARTLength - 1,
ariane_soc::SPIBase + ariane_soc::SPILength - 1,
`ifdef INCL_SRAM
ariane_soc::SRAMBase + ariane_soc::SRAMLength - 1,
ariane_soc::DRAMBase + ariane_soc::DRAMLength - 1
`else
ariane_soc::DRAMBase + ariane_soc::DRAMLength - 1
`endif
ariane_soc::DebugBase + ariane_soc::DebugLength - 1,
ariane_soc::ROMBase + ariane_soc::ROMLength - 1,
ariane_soc::CLINTBase + ariane_soc::CLINTLength - 1,
ariane_soc::PLICBase + ariane_soc::PLICLength - 1,
ariane_soc::UARTBase + ariane_soc::UARTLength - 1,
ariane_soc::SPIBase + ariane_soc::SPILength - 1,
ariane_soc::EthernetBase + ariane_soc::EthernetLength -1,
ariane_soc::DRAMBase + ariane_soc::DRAMLength - 1
})
);
@ -308,61 +236,63 @@ dmi_jtag i_dmi_jtag (
.tdo_oe_o ( )
);
ariane_axi::req_t axi_sba_req;
ariane_axi::resp_t axi_sba_resp;
// debug module
dm_top #(
// current implementation only supports 1 hart
.NrHarts ( 1 ),
.AxiIdWidth ( AxiIdWidthSlaves ),
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
.AxiUserWidth ( AxiUserWidth )
.NrHarts ( 1 ),
.AxiIdWidth ( AxiIdWidthSlaves ),
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
.AxiUserWidth ( AxiUserWidth )
) i_dm_top (
.clk_i ( clk ),
.rst_ni ( rst_n ), // PoR
.testmode_i ( test_en ),
.ndmreset_o ( ndmreset ),
.dmactive_o ( dmactive ), // active debug session
.debug_req_o ( debug_req_irq ),
.unavailable_i ( '0 ),
.axi_master ( dummy_slave ),
.axi_slave ( master[ariane_soc::Debug] ),
.dmi_rst_ni ( rst_n ),
.dmi_req_valid_i ( debug_req_valid ),
.dmi_req_ready_o ( debug_req_ready ),
.dmi_req_i ( debug_req ),
.dmi_resp_valid_o ( debug_resp_valid ),
.dmi_resp_ready_i ( debug_resp_ready ),
.dmi_resp_o ( debug_resp )
.clk_i ( clk ),
.rst_ni ( rst_n ), // PoR
.testmode_i ( test_en ),
.ndmreset_o ( ndmreset ),
.dmactive_o ( dmactive ), // active debug session
.debug_req_o ( debug_req_irq ),
.unavailable_i ( '0 ),
.axi_slave ( master[ariane_soc::Debug] ),
.axi_req_o ( axi_sba_req ),
.axi_resp_i ( axi_sba_resp ),
.dmi_rst_ni ( rst_n ),
.dmi_req_valid_i ( debug_req_valid ),
.dmi_req_ready_o ( debug_req_ready ),
.dmi_req_i ( debug_req ),
.dmi_resp_valid_o ( debug_resp_valid ),
.dmi_resp_ready_i ( debug_resp_ready ),
.dmi_resp_o ( debug_resp )
);
assign dummy_slave.aw_ready = 1'b0;
assign dummy_slave.ar_ready = 1'b0;
assign dummy_slave.w_ready = 1'b0;
assign dummy_slave.b_valid = 1'b0;
assign dummy_slave.r_valid = 1'b0;
assign axi_sba_resp = '0;
// ---------------
// Core
// ---------------
ariane_axi::req_t axi_ariane_req;
ariane_axi::resp_t axi_ariane_resp;
ariane #(
.CACHE_START_ADDR ( CacheStartAddr ),
.AXI_ID_WIDTH ( AxiIdWidthMaster ),
.AXI_USER_WIDTH ( AxiUserWidth )
) i_ariane (
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
.boot_addr_i ( ariane_soc::ROMBase ), // start fetching from ROM
.core_id_i ( '0 ),
.cluster_id_i ( '0 ),
.irq_i ( irq ),
.ipi_i ( ipi ),
.time_irq_i ( timer_irq ),
.debug_req_i ( debug_req_irq ),
.data_if ( slave_slice[2] ),
.bypass_if ( slave_slice[1] ),
.instr_if ( slave_slice[0] )
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
.boot_addr_i ( ariane_soc::ROMBase ), // start fetching from ROM
.hart_id_i ( '0 ),
.irq_i ( irq ),
.ipi_i ( ipi ),
.time_irq_i ( timer_irq ),
.debug_req_i ( debug_req_irq ),
.axi_req_o ( axi_ariane_req ),
.axi_resp_i ( axi_ariane_resp )
);
axi_connect i_axi_connect_ariane (.axi_req_i(axi_ariane_req), .axi_resp_o(axi_ariane_resp), .master(slave[0]));
// ---------------
// CLINT
// ---------------
@ -410,37 +340,53 @@ axi2mem #(
);
bootrom i_bootrom (
.clk_i ( clk ),
.req_i ( rom_req ),
.addr_i ( rom_addr ),
.rdata_o ( rom_rdata )
.clk_i ( clk ),
.req_i ( rom_req ),
.addr_i ( rom_addr ),
.rdata_o ( rom_rdata )
);
// ---------------
// Peripherals
// ---------------
ariane_peripherals #(
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
.AxiIdWidth ( AxiIdWidthSlaves ),
.AxiUserWidth ( AxiUserWidth ),
.InclUART ( 1'b1 ),
`ifdef GENESYSII
.InclSPI ( 1'b1 ),
.InclEthernet ( 1'b1 )
`elsif VCU118
.InclSPI ( 1'b0 ),
.InclEthernet ( 1'b0 )
`endif
.DummyUART ( 1'b0 )
) i_ariane_peripherals (
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
.plic ( master[ariane_soc::PLIC] ),
.uart ( master[ariane_soc::UART] ),
.spi ( master[ariane_soc::SPI] ),
.irq_o ( irq ),
.rx_i ( rx ),
.tx_o ( tx ),
.spi_clk_o ( spi_clk_o ),
.spi_mosi ( spi_mosi ),
.spi_miso ( spi_miso ),
.spi_ss ( spi_ss )
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
.plic ( master[ariane_soc::PLIC] ),
.uart ( master[ariane_soc::UART] ),
.spi ( master[ariane_soc::SPI] ),
.ethernet ( master[ariane_soc::Ethernet] ),
.irq_o ( irq ),
.rx_i ( rx ),
.tx_o ( tx ),
.eth_txck,
.eth_rxck,
.eth_rxctl,
.eth_rxd,
.eth_rst_n,
.eth_tx_en,
.eth_txd,
.phy_mdio,
.eth_mdc,
.mdio,
.mdc,
.spi_clk_o ( spi_clk_o ),
.spi_mosi ( spi_mosi ),
.spi_miso ( spi_miso ),
.spi_ss ( spi_ss )
);
// ---------------------
@ -492,7 +438,7 @@ logic s_axi_rready;
assign master[ariane_soc::DRAM].r_user = '0;
assign master[ariane_soc::DRAM].b_user = '0;
axi_clock_converter_0 axi_clock_converter (
xlnx_axi_clock_converter i_xlnx_axi_clock_converter (
.s_axi_aclk ( clk ),
.s_axi_aresetn ( ndmreset_n ),
.s_axi_awid ( master[ariane_soc::DRAM].aw_id ),
@ -578,83 +524,13 @@ axi_clock_converter_0 axi_clock_converter (
.m_axi_rready ( s_axi_rready )
);
clk_wiz_0 i_clk_gen (
xlnx_clk_gen i_xlnx_clk_gen (
.clk_out1 ( clk ),
.reset ( cpu_reset ),
.locked ( ), // keep open
.clk_in1 ( ddr_clock_out )
);
`ifdef INCL_SRAM
logic req;
logic we;
logic [AxiAddrWidth-1:0] addr;
logic [AxiDataWidth/8-1:0] be;
logic [AxiDataWidth-1:0] wdata;
logic [AxiDataWidth-1:0] rdata;
axi2mem #(
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_USER_WIDTH ( AxiUserWidth )
) i_axi2mem (
.clk_i ( clk ),
.rst_ni ( ndmreset_n ),
.slave ( master[ariane_soc::DRAM] ),
.req_o ( req ),
.we_o ( we ),
.addr_o ( addr ),
.be_o ( be ),
.data_o ( wdata ),
.data_i ( rdata )
);
// sram #(
// .DATA_WIDTH ( AxiDataWidth ),
// .NUM_WORDS ( NumWords )
// ) i_sram (
// .clk_i ( clk ),
// .rst_ni ( rst_ni ),
// .req_i ( req ),
// .we_i ( we ),
// .addr_i ( addr[$clog2(NumWords)-1+$clog2(AxiDataWidth/8):$clog2(AxiDataWidth/8)] ),
// .wdata_i ( wdata ),
// .be_i ( be ),
// .rdata_o ( rdata )
// );
xpm_memory_spram #(
.ADDR_WIDTH_A ( $clog2(NumWords) ),
.AUTO_SLEEP_TIME ( 0 ),
.BYTE_WRITE_WIDTH_A ( 8 ),
.ECC_MODE ( "no_ecc" ),
.MEMORY_OPTIMIZATION ( "true" ),
.MEMORY_PRIMITIVE ( "auto" ),
.MEMORY_SIZE ( NumWords * 64 ),
.MESSAGE_CONTROL ( 0 ),
.READ_DATA_WIDTH_A ( 64 ),
.READ_LATENCY_A ( 1 ),
.USE_MEM_INIT ( 0 ),
.WAKEUP_TIME ( "disable_sleep" ),
.WRITE_DATA_WIDTH_A ( 64 ),
.WRITE_MODE_A ( "read_first" )
) xpm_memory_spram_inst (
.dbiterra ( ),
.douta ( rdata ),
.sbiterra ( ),
.addra ( addr[$clog2(NumWords)-1+$clog2(AxiDataWidth/8):$clog2(AxiDataWidth/8)] ),
.clka ( clk ),
.dina ( wdata ),
.ena ( req ),
.injectdbiterra ( '0 ),
.injectsbiterra ( '0 ),
.regcea ( 1'b1 ),
.rsta ( rst ),
.sleep ( 1'b0 ),
.wea ( we )
);
`endif
`ifdef GENESYSII
fan_ctrl i_fan_ctrl (
.clk_i ( clk ),
@ -1159,59 +1035,59 @@ axi_dwidth_converter_512_64 i_axi_dwidth_converter_512_64 (
);
assign slave_slice[3].aw_user = '0;
assign slave_slice[3].ar_user = '0;
assign slave_slice[3].w_user = '0;
assign slave[1].aw_user = '0;
assign slave[1].ar_user = '0;
assign slave[1].w_user = '0;
logic [3:0] slave_slice_b_id;
logic [3:0] slave_slice_r_id;
logic [3:0] slave_b_id;
logic [3:0] slave_r_id;
assign slave_slice[3].b_id = slave_slice_b_id[1:0];
assign slave_slice[3].r_id = slave_slice_r_id[1:0];
assign slave[1].b_id = slave_b_id[1:0];
assign slave[1].r_id = slave_r_id[1:0];
// PCIe Clock Converter
axi_clock_converter_0 pcie_axi_clock_converter (
.m_axi_aclk ( clk ),
.m_axi_aresetn ( ndmreset_n ),
.m_axi_awid ( {2'b0, slave_slice[3].aw_id} ),
.m_axi_awaddr ( slave_slice[3].aw_addr ),
.m_axi_awlen ( slave_slice[3].aw_len ),
.m_axi_awsize ( slave_slice[3].aw_size ),
.m_axi_awburst ( slave_slice[3].aw_burst ),
.m_axi_awlock ( slave_slice[3].aw_lock ),
.m_axi_awcache ( slave_slice[3].aw_cache ),
.m_axi_awprot ( slave_slice[3].aw_prot ),
.m_axi_awregion ( slave_slice[3].aw_region ),
.m_axi_awqos ( slave_slice[3].aw_qos ),
.m_axi_awvalid ( slave_slice[3].aw_valid ),
.m_axi_awready ( slave_slice[3].aw_ready ),
.m_axi_wdata ( slave_slice[3].w_data ),
.m_axi_wstrb ( slave_slice[3].w_strb ),
.m_axi_wlast ( slave_slice[3].w_last ),
.m_axi_wvalid ( slave_slice[3].w_valid ),
.m_axi_wready ( slave_slice[3].w_ready ),
.m_axi_bid ( slave_slice_b_id ),
.m_axi_bresp ( slave_slice[3].b_resp ),
.m_axi_bvalid ( slave_slice[3].b_valid ),
.m_axi_bready ( slave_slice[3].b_ready ),
.m_axi_arid ( {2'b0, slave_slice[3].ar_id} ),
.m_axi_araddr ( slave_slice[3].ar_addr ),
.m_axi_arlen ( slave_slice[3].ar_len ),
.m_axi_arsize ( slave_slice[3].ar_size ),
.m_axi_arburst ( slave_slice[3].ar_burst ),
.m_axi_arlock ( slave_slice[3].ar_lock ),
.m_axi_arcache ( slave_slice[3].ar_cache ),
.m_axi_arprot ( slave_slice[3].ar_prot ),
.m_axi_arregion ( slave_slice[3].ar_region ),
.m_axi_arqos ( slave_slice[3].ar_qos ),
.m_axi_arvalid ( slave_slice[3].ar_valid ),
.m_axi_arready ( slave_slice[3].ar_ready ),
.m_axi_rid ( slave_slice_r_id ),
.m_axi_rdata ( slave_slice[3].r_data ),
.m_axi_rresp ( slave_slice[3].r_resp ),
.m_axi_rlast ( slave_slice[3].r_last ),
.m_axi_rvalid ( slave_slice[3].r_valid ),
.m_axi_rready ( slave_slice[3].r_ready ),
.m_axi_awid ( {2'b0, slave[1].aw_id} ),
.m_axi_awaddr ( slave[1].aw_addr ),
.m_axi_awlen ( slave[1].aw_len ),
.m_axi_awsize ( slave[1].aw_size ),
.m_axi_awburst ( slave[1].aw_burst ),
.m_axi_awlock ( slave[1].aw_lock ),
.m_axi_awcache ( slave[1].aw_cache ),
.m_axi_awprot ( slave[1].aw_prot ),
.m_axi_awregion ( slave[1].aw_region ),
.m_axi_awqos ( slave[1].aw_qos ),
.m_axi_awvalid ( slave[1].aw_valid ),
.m_axi_awready ( slave[1].aw_ready ),
.m_axi_wdata ( slave[1].w_data ),
.m_axi_wstrb ( slave[1].w_strb ),
.m_axi_wlast ( slave[1].w_last ),
.m_axi_wvalid ( slave[1].w_valid ),
.m_axi_wready ( slave[1].w_ready ),
.m_axi_bid ( slave_b_id ),
.m_axi_bresp ( slave[1].b_resp ),
.m_axi_bvalid ( slave[1].b_valid ),
.m_axi_bready ( slave[1].b_ready ),
.m_axi_arid ( {2'b0, slave[1].ar_id} ),
.m_axi_araddr ( slave[1].ar_addr ),
.m_axi_arlen ( slave[1].ar_len ),
.m_axi_arsize ( slave[1].ar_size ),
.m_axi_arburst ( slave[1].ar_burst ),
.m_axi_arlock ( slave[1].ar_lock ),
.m_axi_arcache ( slave[1].ar_cache ),
.m_axi_arprot ( slave[1].ar_prot ),
.m_axi_arregion ( slave[1].ar_region ),
.m_axi_arqos ( slave[1].ar_qos ),
.m_axi_arvalid ( slave[1].ar_valid ),
.m_axi_arready ( slave[1].ar_ready ),
.m_axi_rid ( slave_r_id ),
.m_axi_rdata ( slave[1].r_data ),
.m_axi_rresp ( slave[1].r_resp ),
.m_axi_rlast ( slave[1].r_last ),
.m_axi_rvalid ( slave[1].r_valid ),
.m_axi_rready ( slave[1].r_ready ),
// from size converter
.s_axi_aclk ( pcie_axi_clk ),
.s_axi_aresetn ( ndmreset_n ),

1
fpga/src/genesysii.svh
View file

@ -12,4 +12,3 @@
// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
`define GENESYSII
`define FPGA_TARGET_XILINX

1
fpga/src/vcu118.svh
View file

@ -12,4 +12,3 @@
// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
`define VCU118
`define FPGA_TARGET_XILINX

146
fpga/xilinx/ariane_axi_clock_converter.xci
View file

@ -1,146 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>ariane_axi_clock_converter</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_clock_converter" spirit:version="2.1"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MI_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MI_CLK.FREQ_HZ">10000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MI_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MI_RST.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SI_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ">10000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SI_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SI_RST.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_IS_ACLK_ASYNC">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_PROTOCOL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SUPPORTS_READ">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SUPPORTS_USER_SIGNALS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SUPPORTS_WRITE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_ACLK_RATIO">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ACLK_RATIO">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLK_ASYNC">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLK_RATIO">1:2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDR_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ariane_axi_clock_converter</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD">digilentinc.com:genesys2:part0:1.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2018.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ID_WIDTH" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>

0
fpga/ariane.srcs/sources_1/ip/mig_7series_0/mig_7series_0.xci → fpga/xilinx/mig_7series_0.xci
View file

0
fpga/ariane.srcs/sources_1/ip/mig_7series_0/mig_a.prj → fpga/xilinx/mig_a.prj
View file

12
fpga/ariane.srcs/sources_1/ip/axi_clock_converter_0/axi_clock_converter_0.xci → fpga/xilinx/xlnx_axi_clock_converter.xci
View file

@ -6,7 +6,7 @@
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>axi_clock_converter_0</spirit:instanceName>
<spirit:instanceName>xlnx_axi_clock_converter</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_clock_converter" spirit:version="2.1"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_BUSIF"/>
@ -31,7 +31,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
@ -67,7 +67,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
@ -86,7 +86,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_IS_ACLK_ASYNC">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_PROTOCOL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
@ -104,9 +104,9 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axi_clock_converter_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xlnx_axi_clock_converter</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">0</spirit:configurableElementValue>

10
fpga/ariane.srcs/sources_1/ip/axi_dwidth_converter_0/axi_dwidth_converter_0.xci → fpga/xilinx/xlnx_axi_dwidth_converter.xci
View file

@ -6,7 +6,7 @@
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>axi_dwidth_converter_0</spirit:instanceName>
<spirit:instanceName>xlnx_axi_clock_converter</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_dwidth_converter" spirit:version="2.1"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MI_CLK.ASSOCIATED_BUSIF"/>
@ -67,7 +67,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
@ -96,11 +96,11 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ACLK_RATIO">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ID_WIDTH">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLK_ASYNC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLK_RATIO">1:2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axi_dwidth_converter_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xlnx_axi_clock_converter</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_MODE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MAX_SPLIT_BEATS">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MI_DATA_WIDTH">32</spirit:configurableElementValue>
@ -108,7 +108,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SI_DATA_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SI_ID_WIDTH">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD">digilentinc.com:genesys2:part0:1.1</spirit:configurableElementValue>

76
fpga/ariane.srcs/sources_1/ip/axi_uartlite_1/axi_uartlite_1.xci → fpga/xilinx/xlnx_axi_ethernetlite.xci
View file

@ -6,14 +6,12 @@
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>axi_uartlite_1</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_uartlite" spirit:version="2.0"/>
<spirit:instanceName>xlnx_axi_ethernetlite</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_ethernetlite" spirit:version="3.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERRUPT.PortWidth">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MDIO.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">13</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
@ -21,43 +19,57 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BAUDRATE">115200</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_BITS">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DUPLEX">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ODD_PARITY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ACLK_FREQ_HZ">50000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PARITY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BAUDRATE">115200</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DATA_BITS">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ODD_PARITY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_ACLK_FREQ_HZ">50000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_ACLK_FREQ_HZ_d">50</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_PARITY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axi_uartlite_1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PARITY">No_Parity</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UARTLITE_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_GLOBAL_BUFFERS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_INTERNAL_LOOPBACK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_MDIO">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_PING_PONG">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ACLK_PERIOD_PS">20000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_PING_PONG">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ACLK_FREQ_MHZ">50</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DUPLEX">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INCLUDE_GLOBAL_BUFFERS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INCLUDE_INTERNAL_LOOPBACK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INCLUDE_MDIO">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_RX_PING_PONG">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TX_PING_PONG">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_INTERNAL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xlnx_axi_ethernetlite</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Constraints">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MDIO_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MII_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD">digilentinc.com:genesys2:part0:1.1</spirit:configurableElementValue>
@ -71,7 +83,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">21</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
@ -82,9 +94,9 @@
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BAUDRATE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_S_AXI_ACLK_FREQ_HZ" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_S_AXI_ACLK_FREQ_HZ_d" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AXI_ACLK_FREQ_MHZ" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_S_AXI_ID_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_S_AXI_PROTOCOL" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>

0
fpga/ariane.srcs/sources_1/ip/axi_quad_spi_0/axi_quad_spi_0.xci → fpga/xilinx/xlnx_axi_quad_spi.xci
View file

6
fpga/ariane.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci → fpga/xilinx/xlnx_clk_gen.xci
View file

@ -6,7 +6,7 @@
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>clk_wiz_0</spirit:instanceName>
<spirit:instanceName>xlnx_clk_gen</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="6.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_IN_D.CAN_DEBUG">false</spirit:configurableElementValue>
@ -373,7 +373,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clk_wiz_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">xlnx_clk_gen</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
@ -474,7 +474,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clk_wiz_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xlnx_clk_gen</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>

2
src/ariane.sv
View file

@ -21,7 +21,7 @@ import instruction_tracer_pkg::*;
module ariane #(
parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000 // address on which to decide whether the request is cache-able or not
)(
) (
input logic clk_i,
input logic rst_ni,
// Core ID, Cluster ID and boot address are considered more or less static

14
src/plic/plic.sv
View file

@ -28,19 +28,19 @@
//-------------------------------------------------------------------------------
module plic #(
parameter int ADDR_WIDTH = -1, //width of external address bus
parameter int DATA_WIDTH = -1, //width of external data bus
parameter int ID_BITWIDTH = -1, //width of the gateway identifiers
parameter int PARAMETER_BITWIDTH = -1, //width of the internal parameter e.g. priorities
parameter int NUM_TARGETS = -1, //number of target slices
parameter int NUM_SOURCES = -1 //number of sources = number of gateways
)(
parameter int ID_BITWIDTH = -1, // width of the gateway identifiers
parameter int PARAMETER_BITWIDTH = -1, // width of the internal parameter e.g. priorities
parameter int NUM_TARGETS = -1, // number of target slices
parameter int NUM_SOURCES = -1 // number of sources = number of gateways
) (
input logic clk_i,
input logic rst_ni,
input logic [NUM_SOURCES-1:0] irq_sources_i,
output logic [NUM_TARGETS-1:0] eip_targets_o,
REG_BUS.in external_bus_io
);
localparam int ADDR_WIDTH = 32;
localparam int DATA_WIDTH = 32;
// declare all local variables
// gateway arrays always go from NUM_SOURCES to 1 because gateway ids start at 1
logic gateway_irq_pendings [NUM_SOURCES]; //for pending irqs of the gateways

24
tb/ariane_soc_pkg.sv
View file

@ -15,28 +15,18 @@ package ariane_soc;
localparam NumTargets = 2;
// Uart, SPI, Ethernet
localparam NumSources = 3;
localparam PLICIdWidth = 3;
localparam ParameterBitwidth = PLICIdWidth;
typedef enum int unsigned {
`ifdef INCL_SRAM
DRAM = 0,
SRAM = 1,
ETHERNET = 2,
SPI = 3,
UART = 4,
PLIC = 5,
CLINT = 6,
ROM = 7,
Debug = 8
`else
DRAM = 0,
ETHERNET = 1
Ethernet = 1,
SPI = 2,
UART = 3,
PLIC = 4,
CLINT = 5,
ROM = 6,
Debug = 7
`endif
} axi_slaves_t;
localparam NB_PERIPHERALS = Debug + 1;
@ -46,7 +36,7 @@ package ariane_soc;
localparam logic[63:0] CLINTLength = 64'hC0000;
localparam logic[63:0] PLICLength = 64'h3FF_FFFF;
localparam logic[63:0] UARTLength = 64'h1000;
localparam logic[63:0] SPILength = 64'h1000;
localparam logic[63:0] SPILength = 64'h800000;
localparam logic[63:0] EthernetLength = 64'h10000;
localparam logic[63:0] SRAMLength = 64'h1800000; // 24 MByte of SRAM
localparam logic[63:0] DRAMLength = 64'h80000000; // 2 GByte of DDR
@ -61,13 +51,7 @@ package ariane_soc;
UARTBase = 64'h1000_0000,
SPIBase = 64'h2000_0000,
EthernetBase = 64'h3000_0000,
`ifdef INCL_SRAM
// let the memory appear contigouse
SRAMBase = 64'h8000_0000,
DRAMBase = 64'h8000_0000 + SRAMLength
`else
DRAMBase = 64'h8000_0000
`endif
} soc_bus_start_t;
endpackage

82
tb/ariane_testharness.sv
View file

@ -15,7 +15,7 @@
module ariane_testharness #(
parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000, // address on which to decide whether the request is cache-able or not
parameter int unsigned AXI_ID_WIDTH = 2,
parameter int unsigned AXI_ID_WIDTH = 4,
parameter int unsigned AXI_USER_WIDTH = 1,
parameter int unsigned AXI_ADDRESS_WIDTH = 64,
parameter int unsigned AXI_DATA_WIDTH = 64,
@ -413,16 +413,15 @@ module ariane_testharness #(
// ---------------
// AXI Xbar
// ---------------
axi_node_wrap_with_slices #(
// three ports from Ariane (instruction, data and bypass)
axi_node_intf_wrap #(
.NB_SLAVE ( NB_SLAVE ),
.NB_MASTER ( ariane_soc::NB_PERIPHERALS ),
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH ),
.AXI_ID_WIDTH ( AXI_ID_WIDTH ),
.MASTER_SLICE_DEPTH ( 2 ),
.SLAVE_SLICE_DEPTH ( 2 )
.AXI_ID_WIDTH ( AXI_ID_WIDTH )
// .MASTER_SLICE_DEPTH ( 0 ),
// .SLAVE_SLICE_DEPTH ( 0 )
) i_axi_xbar (
.clk ( clk_i ),
.rst_n ( ndmreset_n ),
@ -436,16 +435,18 @@ module ariane_testharness #(
ariane_soc::PLICBase,
ariane_soc::UARTBase,
ariane_soc::SPIBase,
ariane_soc::EthernetBase,
ariane_soc::DRAMBase
}),
.end_addr_i ({
ariane_soc::DebugBase + ariane_soc::DebugLength,
ariane_soc::ROMBase + ariane_soc::ROMLength,
ariane_soc::CLINTBase + ariane_soc::CLINTLength,
ariane_soc::PLICBase + ariane_soc::PLICLength,
ariane_soc::UARTBase + ariane_soc::UARTLength,
ariane_soc::SPIBase + ariane_soc::SPILength,
ariane_soc::DRAMBase + ariane_soc::DRAMLength
ariane_soc::DebugBase + ariane_soc::DebugLength - 1,
ariane_soc::ROMBase + ariane_soc::ROMLength - 1,
ariane_soc::CLINTBase + ariane_soc::CLINTLength - 1,
ariane_soc::PLICBase + ariane_soc::PLICLength - 1,
ariane_soc::UARTBase + ariane_soc::UARTLength - 1,
ariane_soc::SPIBase + ariane_soc::SPILength - 1,
ariane_soc::EthernetBase + ariane_soc::EthernetLength -1,
ariane_soc::DRAMBase + ariane_soc::DRAMLength - 1
})
);
@ -479,16 +480,31 @@ module ariane_testharness #(
ariane_peripherals #(
.AxiAddrWidth ( AXI_ADDRESS_WIDTH ),
.AxiDataWidth ( AXI_DATA_WIDTH ),
.AxiIdWidth ( AXI_ID_WIDTH_SLAVES )
.AxiIdWidth ( AXI_ID_WIDTH_SLAVES ),
.InclUART ( 1'b0 ),
.InclSPI ( 1'b0 ),
.InclEthernet ( 1'b0 )
) i_ariane_peripherals (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.plic ( master[ariane_soc::PLIC] ),
.uart ( master[ariane_soc::UART] ),
.spi ( master[ariane_soc::SPI] ),
.irq_o ( irqs ),
.rx_i ( rx ),
.tx_o ( tx ),
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.plic ( master[ariane_soc::PLIC] ),
.uart ( master[ariane_soc::UART] ),
.spi ( master[ariane_soc::SPI] ),
.ethernet ( master[ariane_soc::Ethernet] ),
.irq_o ( irqs ),
.rx_i ( rx ),
.tx_o ( tx ),
.eth_txck ( ),
.eth_rxck ( ),
.eth_rxctl ( ),
.eth_rxd ( ),
.eth_rst_n ( ),
.eth_tx_en ( ),
.eth_txd ( ),
.phy_mdio ( ),
.eth_mdc ( ),
.mdio ( ),
.mdc ( ),
.spi_clk_o ( ),
.spi_mosi ( ),
.spi_miso ( ),
@ -506,20 +522,18 @@ module ariane_testharness #(
ariane #(
.CACHE_START_ADDR ( CACHE_START_ADDR )
) i_ariane (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.boot_addr_i ( 64'h10000 ), // start fetching from ROM
.hart_id_i ( '0 ),
.irq_i ( irqs ), // we do not specify other interrupts in this TB
.ipi_i ( ipi ),
.time_irq_i ( timer_irq ),
.debug_req_i ( debug_req_core ),
.axi_req_o ( axi_ariane_req ),
.axi_resp_i ( axi_ariane_resp )
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
.boot_addr_i ( ariane_soc::ROMBase ), // start fetching from ROM
.hart_id_i ( '0 ),
.irq_i ( irqs ),
.ipi_i ( ipi ),
.time_irq_i ( timer_irq ),
.debug_req_i ( debug_req_core ),
.axi_req_o ( axi_ariane_req ),
.axi_resp_i ( axi_ariane_resp )
);
axi_connect i_axi_connect_ariane (.axi_req_i(axi_ariane_req), .axi_resp_o(axi_ariane_resp), .master(slave[0]));
endmodule