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Fix issue #24

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This commit is contained in:
Florian Zaruba 2017-06-12 13:53:16 +02:00
parent 8e5f93c6d8
commit 97a305561b
5 changed files with 17 additions and 17 deletions
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12
src/ariane.sv
View file

@ -193,8 +193,8 @@ module ariane
// CSR <-> *
// --------------
logic enable_translation_csr_ex;
logic flag_pum_csr_ex;
logic flag_mxr_csr_ex;
logic sum_csr_ex;
logic mxr_csr_ex;
logic [37:0] pd_ppn_csr_ex;
logic [0:0] asid_csr_ex;
logic [11:0] csr_addr_ex_csr;
@ -381,8 +381,8 @@ module ariane
.fetch_rdata_o ( fetch_rdata_ex_if ),
.fetch_ex_o ( fetch_ex_ex_if ), // fetch exception to IF
.priv_lvl_i ( priv_lvl ), // from CSR
.flag_pum_i ( flag_pum_csr_ex ), // from CSR
.flag_mxr_i ( flag_mxr_csr_ex ), // from CSR
.sum_i ( sum_csr_ex ), // from CSR
.mxr_i ( mxr_csr_ex ), // from CSR
.pd_ppn_i ( pd_ppn_csr_ex ), // from CSR
.asid_i ( asid_csr_ex ), // from CSR
.flush_tlb_i ( flush_tlb ),
@ -434,8 +434,8 @@ module ariane
.priv_lvl_o ( priv_lvl ),
.enable_translation_o ( enable_translation_csr_ex ),
.flag_pum_o ( flag_pum_csr_ex ),
.flag_mxr_o ( flag_mxr_csr_ex ),
.sum_o ( sum_csr_ex ),
.mxr_o ( mxr_csr_ex ),
.pd_ppn_o ( pd_ppn_csr_ex ),
.asid_o ( asid_csr_ex ),
.tvm_o ( tvm_csr_id ),

8
src/csr_regfile.sv
View file

@ -51,8 +51,8 @@ module csr_regfile #(
output priv_lvl_t priv_lvl_o, // Current privilege level the CPU is in
// MMU
output logic enable_translation_o, // Enable VA translation
output logic flag_pum_o, // TODO: this is called SUM now
output logic flag_mxr_o,
output logic sum_o,
output logic mxr_o,
// input logic flag_mprv_i,
output logic [37:0] pd_ppn_o,
output logic [ASID_WIDTH-1:0] asid_o,
@ -504,9 +504,9 @@ module csr_regfile #(
// MMU outputs
assign pd_ppn_o = satp_q.ppn;
assign asid_o = satp_q.asid[ASID_WIDTH-1:0];
assign flag_pum_o = mstatus_q.sum;
assign sum_o = mstatus_q.sum;
assign enable_translation_o = (satp_q.mode == 4'h8) ? 1'b1 : 1'b0;
assign flag_mxr_o = mstatus_q.mxr;
assign mxr_o = mstatus_q.mxr;
assign tvm_o = mstatus_q.tvm;
assign tw_o = mstatus_q.tw;
assign tsr_o = mstatus_q.tsr;

4
src/ex_stage.sv
View file

@ -79,8 +79,8 @@ module ex_stage #(
output logic [31:0] fetch_rdata_o,
output exception fetch_ex_o,
input priv_lvl_t priv_lvl_i,
input logic flag_pum_i,
input logic flag_mxr_i,
input logic sum_i,
input logic mxr_i,
input logic [37:0] pd_ppn_i,
input logic [ASID_WIDTH-1:0] asid_i,
input logic flush_tlb_i,

4
src/lsu.sv
View file

@ -49,8 +49,8 @@ module lsu #(
output exception fetch_ex_o, // Instruction fetch interface
input priv_lvl_t priv_lvl_i, // From CSR register file
input logic flag_pum_i, // From CSR register file
input logic flag_mxr_i, // From CSR register file
input logic sum_i, // From CSR register file
input logic mxr_i, // From CSR register file
input logic [37:0] pd_ppn_i, // From CSR register file
input logic [ASID_WIDTH-1:0] asid_i, // From CSR register file
input logic flush_tlb_i,

6
src/mmu.sv
View file

@ -50,8 +50,8 @@ module mmu #(
output exception lsu_exception_o,
// General control signals
input priv_lvl_t priv_lvl_i,
input logic flag_pum_i,
input logic flag_mxr_i,
input logic sum_i,
input logic mxr_i,
// input logic flag_mprv_i,
input logic [37:0] pd_ppn_i,
input logic [ASID_WIDTH-1:0] asid_i,
@ -196,7 +196,7 @@ module mmu #(
assign dtlb_lu_access = lsu_req_i;
assign iaccess_err = fetch_req_i & (
((priv_lvl_i == PRIV_LVL_U) & ~itlb_content.u)
| (flag_pum_i & (priv_lvl_i == PRIV_LVL_S) & itlb_content.u)
| (sum_i & (priv_lvl_i == PRIV_LVL_S) & itlb_content.u)
);
//-----------------------