mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-22 21:27:10 -04:00
Merge 52c2749a25 into 733743da0f
This commit is contained in:
Riccardo Tedeschi
GitHub
commit
983e670bc8
4 changed files with 76 additions and 140 deletions
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@ -23,8 +23,8 @@ valid_cycles = {
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"dhrystone_single": 24127,
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"coremark_dual": 1001191,
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"coremark_single": 1300030,
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"dhrystone_cv32a65x": 31976,
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"dhrystone_cv32a60x": 39449,
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"dhrystone_cv32a65x": 30056,
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"dhrystone_cv32a60x": 37474,
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}
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for arg in sys.argv[1:]:
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@ -136,7 +136,9 @@ module issue_read_operands
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logic none, load, store, alu, alu2, ctrl_flow, mult, csr, fpu, fpu_vec, cvxif, accel;
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} fus_busy_t;
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logic [CVA6Cfg.NrIssuePorts-1:0] stall_raw, stall_waw, stall_rs1, stall_rs2, stall_rs3;
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typedef logic [CVA6Cfg.TRANS_ID_BITS:0] clobber_t;
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logic [CVA6Cfg.NrIssuePorts-1:0] stall_raw, stall_rs1, stall_rs2, stall_rs3;
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logic [CVA6Cfg.NrIssuePorts-1:0] fu_busy; // functional unit is busy
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fus_busy_t [CVA6Cfg.NrIssuePorts-1:0] fus_busy; // which functional units are considered busy
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logic [CVA6Cfg.NrIssuePorts-1:0] issue_ack;
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@ -182,10 +184,17 @@ module issue_read_operands
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logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs3_res;
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// clobber
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fu_t [2**ariane_pkg::REG_ADDR_SIZE-1:0] rd_clobber_gpr, rd_clobber_fpr;
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logic [2**ariane_pkg::REG_ADDR_SIZE-1:0][CVA6Cfg.NR_SB_ENTRIES:0] gpr_clobber_vld;
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logic [2**ariane_pkg::REG_ADDR_SIZE-1:0][CVA6Cfg.NR_SB_ENTRIES:0] fpr_clobber_vld;
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ariane_pkg::fu_t [ CVA6Cfg.NR_SB_ENTRIES:0] clobber_fu;
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clobber_t [2**ariane_pkg::REG_ADDR_SIZE-1:0] rd_clobber_gpr, rd_clobber_fpr;
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// Csr issued check
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logic [CVA6Cfg.NR_SB_ENTRIES-1:0] csr_issued_raw;
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logic [ CVA6Cfg.NR_SB_ENTRIES:0] csr_issued;
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for (genvar i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin
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assign csr_issued_raw[i] = fwd_i.still_issued[i] && fwd_i.sbe[i].fu == ariane_pkg::CSR;
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end
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assign csr_issued = {1'b0, csr_issued_raw};
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//forward logic
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logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.NR_SB_ENTRIES+CVA6Cfg.NrWbPorts-1:0]
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@ -246,7 +255,7 @@ module issue_read_operands
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// TODO check only for 1st instruction ??
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// Allow a cvxif transaction if we WaW condition are ok.
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assign cvxif_req_allowed = (issue_instr_i[0].fu == CVXIF) && !stall_waw[0];
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assign cvxif_req_allowed = (issue_instr_i[0].fu == CVXIF);
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assign cvxif_instruction_valid = !issue_instr_i[0].ex.valid && issue_instr_valid_i[0] && cvxif_req_allowed;
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assign x_transaction_accepted_o = x_issue_valid_o && x_issue_ready_i && x_issue_resp_i.accept;
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assign x_transaction_rejected = x_issue_valid_o && x_issue_ready_i && ~x_issue_resp_i.accept;
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@ -412,74 +421,32 @@ module issue_read_operands
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// RD clobber process
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// -------------------
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// rd_clobber output: output currently clobbered destination registers
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logic [2*CVA6Cfg.NR_SB_ENTRIES-1:0] still_issued_rotated_raw;
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logic [ CVA6Cfg.NR_SB_ENTRIES-1:0] still_issued_rotated;
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logic [ CVA6Cfg.TRANS_ID_BITS-1:0] unrotated_index;
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assign still_issued_rotated_raw = {fwd_i.still_issued, fwd_i.still_issued} >> fwd_i.commit_pointer;
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assign still_issued_rotated = still_issued_rotated_raw[CVA6Cfg.NR_SB_ENTRIES-1:0];
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always_comb begin : clobber_assign
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gpr_clobber_vld = '0;
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fpr_clobber_vld = '0;
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rd_clobber_gpr = '{default: clobber_t'(CVA6Cfg.NR_SB_ENTRIES)};
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rd_clobber_fpr = '{default: clobber_t'(CVA6Cfg.NR_SB_ENTRIES)};
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// default (highest entry hast lowest prio in arbiter tree below)
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clobber_fu[CVA6Cfg.NR_SB_ENTRIES] = ariane_pkg::NONE;
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for (int unsigned i = 0; i < 2 ** ariane_pkg::REG_ADDR_SIZE; i++) begin
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gpr_clobber_vld[i][CVA6Cfg.NR_SB_ENTRIES] = 1'b1;
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fpr_clobber_vld[i][CVA6Cfg.NR_SB_ENTRIES] = 1'b1;
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end
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// check for all valid entries and set the clobber accordingly
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unrotated_index = '0;
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for (int unsigned i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin
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gpr_clobber_vld[fwd_i.sbe[i].rd][i] = fwd_i.still_issued[i] & ~(CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
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fwd_i.sbe[i].op));
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fpr_clobber_vld[fwd_i.sbe[i].rd][i] = fwd_i.still_issued[i] & (CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
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fwd_i.sbe[i].op));
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clobber_fu[i] = fwd_i.sbe[i].fu;
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unrotated_index = i + fwd_i.commit_pointer;
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if (still_issued_rotated[i]) begin
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if (~(CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(fwd_i.sbe[unrotated_index].op))) begin
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rd_clobber_gpr[fwd_i.sbe[unrotated_index].rd] = clobber_t'(unrotated_index[CVA6Cfg.TRANS_ID_BITS-1:0]);
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end else begin
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rd_clobber_fpr[fwd_i.sbe[unrotated_index].rd] = clobber_t'(unrotated_index[CVA6Cfg.TRANS_ID_BITS-1:0]);
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end
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end
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end
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// GPR[0] is always free
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gpr_clobber_vld[0] = '0;
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end
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for (genvar k = 0; k < 2 ** ariane_pkg::REG_ADDR_SIZE; k++) begin : gen_sel_clobbers
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// get fu that is going to clobber this register (there should be only one)
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rr_arb_tree #(
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.NumIn(CVA6Cfg.NR_SB_ENTRIES + 1),
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.DataType(ariane_pkg::fu_t),
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.ExtPrio(1'b1),
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.AxiVldRdy(1'b1)
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) i_sel_gpr_clobbers (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.flush_i(1'b0),
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.rr_i ('0),
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.req_i (gpr_clobber_vld[k]),
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.gnt_o (),
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.data_i (clobber_fu),
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.gnt_i (1'b1),
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.req_o (),
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.data_o (rd_clobber_gpr[k]),
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.idx_o ()
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);
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if (CVA6Cfg.FpPresent) begin
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rr_arb_tree #(
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.NumIn(CVA6Cfg.NR_SB_ENTRIES + 1),
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.DataType(ariane_pkg::fu_t),
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.ExtPrio(1'b1),
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.AxiVldRdy(1'b1)
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) i_sel_fpr_clobbers (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.flush_i(1'b0),
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.rr_i ('0),
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.req_i (fpr_clobber_vld[k]),
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.gnt_o (),
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.data_i (clobber_fu),
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.gnt_i (1'b1),
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.req_o (),
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.data_o (rd_clobber_fpr[k]),
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.idx_o ()
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);
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end else begin
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assign rd_clobber_fpr[k] = NONE;
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end
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rd_clobber_gpr[0] = clobber_t'(CVA6Cfg.NR_SB_ENTRIES);
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end
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// ----------------------------------
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@ -491,47 +458,48 @@ module issue_read_operands
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for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
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for (genvar k = 0; unsigned'(k) < CVA6Cfg.NrWbPorts; k++) begin : gen_rs_wb
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assign rs1_fwd_req[i][k] = (fwd_i.sbe[fwd_i.wb[k].trans_id].rd == issue_instr_i[i].rs1) & (fwd_i.still_issued[fwd_i.wb[k].trans_id]) & fwd_i.wb[k].valid & (~fwd_i.wb[k].ex_valid) & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
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fwd_i.sbe[fwd_i.wb[k].trans_id].op
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)) == (CVA6Cfg.FpPresent && ariane_pkg::is_rs1_fpr(
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assign rs1_fwd_req[i][k] = ((clobber_t'(fwd_i.wb[k].trans_id) == rd_clobber_gpr[issue_instr_i[i].rs1] && (!ariane_pkg::is_rs1_fpr(
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issue_instr_i[i].op
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)));
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assign rs2_fwd_req[i][k] = (fwd_i.sbe[fwd_i.wb[k].trans_id].rd == issue_instr_i[i].rs2) & (fwd_i.still_issued[fwd_i.wb[k].trans_id]) & fwd_i.wb[k].valid & (~fwd_i.wb[k].ex_valid) & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
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fwd_i.sbe[fwd_i.wb[k].trans_id].op
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)) == (CVA6Cfg.FpPresent && ariane_pkg::is_rs2_fpr(
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))) || (clobber_t'(fwd_i.wb[k].trans_id) == rd_clobber_fpr[issue_instr_i[i].rs1] &&
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(CVA6Cfg.FpPresent && ariane_pkg::is_rs1_fpr(
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issue_instr_i[i].op
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)));
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assign rs3_fwd_req[i][k] = (fwd_i.sbe[fwd_i.wb[k].trans_id].rd == issue_instr_i[i].result[ariane_pkg::REG_ADDR_SIZE-1:0]) & (fwd_i.still_issued[fwd_i.wb[k].trans_id]) & fwd_i.wb[k].valid & (~fwd_i.wb[k].ex_valid) & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
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fwd_i.sbe[fwd_i.wb[k].trans_id].op
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)) == (CVA6Cfg.FpPresent && ariane_pkg::is_imm_fpr(
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)))) & fwd_i.wb[k].valid & (~fwd_i.wb[k].ex_valid);
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assign rs2_fwd_req[i][k] = ((clobber_t'(fwd_i.wb[k].trans_id) == rd_clobber_gpr[issue_instr_i[i].rs2] && (!ariane_pkg::is_rs2_fpr(
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issue_instr_i[i].op
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)));
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))) || (clobber_t'(fwd_i.wb[k].trans_id) == rd_clobber_fpr[issue_instr_i[i].rs2] &&
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(CVA6Cfg.FpPresent && ariane_pkg::is_rs2_fpr(
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issue_instr_i[i].op
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)))) & fwd_i.wb[k].valid & (~fwd_i.wb[k].ex_valid);
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assign rs3_fwd_req[i][k] = ((clobber_t'(fwd_i.wb[k].trans_id) == rd_clobber_gpr[issue_instr_i[i].result[ariane_pkg::REG_ADDR_SIZE-1:0]] && (!ariane_pkg::is_imm_fpr(
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issue_instr_i[i].op
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))) || (clobber_t'(fwd_i.wb[k].trans_id) ==
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rd_clobber_fpr[issue_instr_i[i].result[ariane_pkg::REG_ADDR_SIZE-1:0]] &&
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(CVA6Cfg.FpPresent && ariane_pkg::is_imm_fpr(
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issue_instr_i[i].op
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)))) & fwd_i.wb[k].valid & (~fwd_i.wb[k].ex_valid);
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assign rs_data[i][k] = fwd_i.wb[k].data;
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end
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for (genvar k = 0; unsigned'(k) < CVA6Cfg.NR_SB_ENTRIES; k++) begin : gen_rs_entries
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assign rs1_fwd_req[i][k+CVA6Cfg.NrWbPorts] = (fwd_i.sbe[k].rd == issue_instr_i[i].rs1) & fwd_i.still_issued[k] & fwd_i.sbe[k].valid & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
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fwd_i.sbe[k].op
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)) == (CVA6Cfg.FpPresent && ariane_pkg::is_rs1_fpr(
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assign rs1_fwd_req[i][k+CVA6Cfg.NrWbPorts] = ((rd_clobber_gpr[issue_instr_i[i].rs1] == clobber_t'(k) &&(!ariane_pkg::is_rs1_fpr(
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issue_instr_i[i].op
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)));
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assign rs2_fwd_req[i][k+CVA6Cfg.NrWbPorts] = (fwd_i.sbe[k].rd == issue_instr_i[i].rs2) & fwd_i.still_issued[k] & fwd_i.sbe[k].valid & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
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fwd_i.sbe[k].op
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)) == (CVA6Cfg.FpPresent && ariane_pkg::is_rs2_fpr(
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))) || (rd_clobber_fpr[issue_instr_i[i].rs1] == clobber_t'(k) &&
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(CVA6Cfg.FpPresent && ariane_pkg::is_rs1_fpr(
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issue_instr_i[i].op
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)));
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assign rs3_fwd_req[i][k+CVA6Cfg.NrWbPorts] = (fwd_i.sbe[k].rd == issue_instr_i[i].result[ariane_pkg::REG_ADDR_SIZE-1:0]) & fwd_i.still_issued[k] & fwd_i.sbe[k].valid & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
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fwd_i.sbe[k].op
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)) == (CVA6Cfg.FpPresent && ariane_pkg::is_imm_fpr(
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)))) & fwd_i.still_issued[k] & fwd_i.sbe[k].valid;
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assign rs2_fwd_req[i][k+CVA6Cfg.NrWbPorts] = ((rd_clobber_gpr[issue_instr_i[i].rs2] == clobber_t'(k) && (!ariane_pkg::is_rs2_fpr(
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issue_instr_i[i].op
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)));
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))) || (rd_clobber_fpr[issue_instr_i[i].rs2] == clobber_t'(k) &&
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(CVA6Cfg.FpPresent && ariane_pkg::is_rs2_fpr(
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issue_instr_i[i].op
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)))) & fwd_i.still_issued[k] & fwd_i.sbe[k].valid;
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assign rs3_fwd_req[i][k+CVA6Cfg.NrWbPorts] = ((rd_clobber_gpr[issue_instr_i[i].result[ariane_pkg::REG_ADDR_SIZE-1:0]] == clobber_t'(k) && (!ariane_pkg::is_imm_fpr(
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issue_instr_i[i].op
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))) || (rd_clobber_fpr[issue_instr_i[i].result[ariane_pkg::REG_ADDR_SIZE-1:0]] ==
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clobber_t'(k) && (CVA6Cfg.FpPresent && ariane_pkg::is_imm_fpr(
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issue_instr_i[i].op
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)))) & fwd_i.still_issued[k] & fwd_i.sbe[k].valid;
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assign rs_data[i][k+CVA6Cfg.NrWbPorts] = fwd_i.sbe[k].result;
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end
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@ -603,27 +571,27 @@ module issue_read_operands
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assign rs1_has_raw[i] = !issue_instr_i[i].use_zimm && ((CVA6Cfg.FpPresent && is_rs1_fpr(
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issue_instr_i[i].op
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)) ? rd_clobber_fpr[issue_instr_i[i].rs1] != NONE :
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rd_clobber_gpr[issue_instr_i[i].rs1] != NONE);
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)) ? rd_clobber_fpr[issue_instr_i[i].rs1] != clobber_t'(CVA6Cfg.NR_SB_ENTRIES) :
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rd_clobber_gpr[issue_instr_i[i].rs1] != clobber_t'(CVA6Cfg.NR_SB_ENTRIES));
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assign rs1_valid[i] = rs1_available[i] && (CVA6Cfg.FpPresent && is_rs1_fpr(
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issue_instr_i[i].op
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) ? 1'b1 : ((rd_clobber_gpr[issue_instr_i[i].rs1] != CSR) ||
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) ? 1'b1 : (!(csr_issued[rd_clobber_gpr[issue_instr_i[i].rs1]]) ||
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(CVA6Cfg.RVS && issue_instr_i[i].op == SFENCE_VMA)));
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assign rs2_has_raw[i] = ((CVA6Cfg.FpPresent && is_rs2_fpr(
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issue_instr_i[i].op
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)) ? rd_clobber_fpr[issue_instr_i[i].rs2] != NONE :
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rd_clobber_gpr[issue_instr_i[i].rs2] != NONE);
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)) ? rd_clobber_fpr[issue_instr_i[i].rs2] != clobber_t'(CVA6Cfg.NR_SB_ENTRIES) :
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rd_clobber_gpr[issue_instr_i[i].rs2] != clobber_t'(CVA6Cfg.NR_SB_ENTRIES));
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assign rs2_valid[i] = rs2_available[i] && (CVA6Cfg.FpPresent && is_rs2_fpr(
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issue_instr_i[i].op
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) ? 1'b1 : ((rd_clobber_gpr[issue_instr_i[i].rs2] != CSR) ||
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) ? 1'b1 : (!(csr_issued[rd_clobber_gpr[issue_instr_i[i].rs2]]) ||
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(CVA6Cfg.RVS && issue_instr_i[i].op == SFENCE_VMA)));
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assign rs3_has_raw[i] = ((CVA6Cfg.FpPresent && is_imm_fpr(
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issue_instr_i[i].op
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)) ? rd_clobber_fpr[issue_instr_i[i].result[REG_ADDR_SIZE-1:0]] != NONE : 0);
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)) ? rd_clobber_fpr[issue_instr_i[i].result[REG_ADDR_SIZE-1:0]] != CVA6Cfg.NR_SB_ENTRIES : 0);
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assign rs3_valid[i] = rs3_available[i];
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assign rs3_fpr[i] = (CVA6Cfg.FpPresent && ariane_pkg::is_imm_fpr(issue_instr_i[i].op));
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@ -902,40 +870,6 @@ module issue_read_operands
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end
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end
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always_comb begin : gen_check_waw_dependencies
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stall_waw = '1;
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for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
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if (issue_instr_valid_i[i] && !fu_busy[i]) begin
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// -----------------------------------------
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// WAW - Write After Write Dependency Check
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// -----------------------------------------
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// no other instruction has the same destination register -> issue the instruction
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if ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
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issue_instr_i[i].op
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)) ? (rd_clobber_fpr[issue_instr_i[i].rd] == NONE) :
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(rd_clobber_gpr[issue_instr_i[i].rd] == NONE)) begin
|
||||
stall_waw[i] = 1'b0;
|
||||
end
|
||||
// or check that the target destination register will be written in this cycle by the
|
||||
// commit stage
|
||||
for (int unsigned c = 0; c < CVA6Cfg.NrCommitPorts; c++) begin
|
||||
if ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
|
||||
issue_instr_i[i].op
|
||||
)) ? (we_fpr_i[c] && waddr_i[c] == issue_instr_i[i].rd) :
|
||||
(we_gpr_i[c] && waddr_i[c] == issue_instr_i[i].rd)) begin
|
||||
stall_waw[i] = 1'b0;
|
||||
end
|
||||
end
|
||||
if (i > 0) begin
|
||||
if ((issue_instr_i[i].rd == issue_instr_i[i-1].rd) && (issue_instr_i[i].rd != '0)) begin
|
||||
stall_waw[i] = 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// We can issue an instruction if we do not detect that any other instruction is writing the same
|
||||
// destination register.
|
||||
// We also need to check if there is an unresolved branch in the scoreboard.
|
||||
|
|
@ -946,7 +880,7 @@ module issue_read_operands
|
|||
// check that the instruction we got is valid
|
||||
// and that the functional unit we need is not busy
|
||||
if (issue_instr_valid_i[i] && !fu_busy[i]) begin
|
||||
if (!stall_raw[i] && !stall_waw[i]) begin
|
||||
if (!stall_raw[i]) begin
|
||||
issue_ack[i] = 1'b1;
|
||||
end
|
||||
if (issue_instr_i[i].ex.valid) begin
|
||||
|
|
|
|||
|
|
@ -172,6 +172,7 @@ module issue_stage
|
|||
typedef struct packed {
|
||||
logic [CVA6Cfg.NR_SB_ENTRIES-1:0] still_issued;
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer;
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] commit_pointer;
|
||||
writeback_t [CVA6Cfg.NrWbPorts-1:0] wb;
|
||||
scoreboard_entry_t [CVA6Cfg.NR_SB_ENTRIES-1:0] sbe;
|
||||
} forwarding_t;
|
||||
|
|
|
|||
|
|
@ -295,6 +295,7 @@ module scoreboard #(
|
|||
|
||||
assign fwd_o.still_issued = still_issued;
|
||||
assign fwd_o.issue_pointer = issue_pointer;
|
||||
assign fwd_o.commit_pointer = commit_pointer_q[0];
|
||||
assign fwd_o.wb = wb;
|
||||
for (genvar i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin
|
||||
assign fwd_o.sbe[i] = mem_q[i].sbe;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue