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csr_regfile: SEIP is read only 0 (fix #2056) (#2716)

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Fix #2056

---------

Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
This commit is contained in:
Guillaume Chauvon 2025-01-21 14:53:37 +01:00 • committed by GitHub
parent 7bdfa5f63e
commit 98604b5920
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GPG key ID: B5690EEEBB952194
4 changed files with 5 additions and 2 deletions
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2
.gitlab-ci/expected_synth.yml
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@ -1,2 +1,2 @@
cv32a65x:
gates: 184679
gates: 185674

2
core/csr_regfile.sv
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@ -2424,7 +2424,7 @@ module csr_regfile
unique case (conv_csr_addr.address)
riscv::CSR_MIP:
csr_rdata_o = csr_rdata | ({{CVA6Cfg.XLEN - 1{1'b0}}, irq_i[1]} << riscv::IRQ_S_EXT);
csr_rdata_o = csr_rdata | ({{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.RVS && irq_i[1]} << riscv::IRQ_S_EXT);
// in supervisor mode we also need to check whether we delegated this bit
riscv::CSR_SIP: begin
if (CVA6Cfg.RVS) begin

1
core/cva6.sv
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@ -1731,6 +1731,7 @@ module cva6
.wdata_i (wdata_commit_id),
.csr_i(rvfi_csr),
.irq_i(irq_i),
.rvfi_probes_o(rvfi_probes_o)

2
core/cva6_rvfi_probes.sv
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@ -51,6 +51,7 @@ module cva6_rvfi_probes
input logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_i,
input rvfi_probes_csr_t csr_i,
input logic [1:0] irq_i,
output rvfi_probes_t rvfi_probes_o
);
@ -109,6 +110,7 @@ module cva6_rvfi_probes
instr.wdata = wdata_i;
csr = csr_i;
csr.mip_q = csr_i.mip_q | ({{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.RVS && irq_i[1]} << riscv::IRQ_S_EXT);
end