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Enable D$ by default and extend README
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Florian Zaruba
parent
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commit
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5 changed files with 54 additions and 35 deletions
51
README.md
51
README.md
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@ -83,25 +83,65 @@ $ make sim riscv-test-dir=$RISCV/riscv64-unknown-elf/bin riscv-test=pk target-op
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## FPGA Emulation
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We provide support for the [Genesys 2 board](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual).
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We currently provide support for the [Genesys 2 board](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual).
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During Synthesis set the following tick defines need to be set:
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```
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FPGA_TARGET_XILINX
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GENESYSII
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```
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TBD: FPGA flow
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Default baudrate is `9600`:
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Default baudrate is `115200`:
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```
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$ screen /dev/ttyUSB0 9600
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$ screen /dev/ttyUSB0 115200
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```
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### Debugging
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[OpenOCD](http://openocd.org/doc/html/Architecture-and-Core-Commands.html)
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You can debug (and program) the FPGA using [OpenOCD](http://openocd.org/doc/html/Architecture-and-Core-Commands.html). We provide two example scripts for OpenOCD, both to be used with Olimex Debug adapter. The JTAG port ist mapped to PMOD `JC` on the Gensys 2 board. You will need to connect the following wires to your debug adapter:
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| Pin | Nr. |
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|----------|-----|
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| `tck` | JC1 |
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| `tdi` | JC2 |
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| `tdo` | JC3 |
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| `tms` | JC4 |
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| `trst_n` | JC7 |
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```
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$ openocd -f fpga/ariane_tiny.cfg
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Open On-Chip Debugger 0.10.0+dev-00195-g933cb87 (2018-09-14-19:32)
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Licensed under GNU GPL v2
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For bug reports, read
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http://openocd.org/doc/doxygen/bugs.html
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adapter speed: 1000 kHz
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Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
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Info : clock speed 1000 kHz
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Info : TAP riscv.cpu does not have IDCODE
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Info : datacount=2 progbufsize=12
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Info : Examined RISC-V core; found 1 harts
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Info : hart 0: XLEN=64, misa=0x8000000000141105
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Info : Listening on port 3333 for gdb connections
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Ready for Remote Connections
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Info : Listening on port 6666 for tcl connections
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Info : Listening on port 4444 for telnet connections
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Info : accepting 'gdb' connection on tcp/3333
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```
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Then you will be able to either connect through `telnet` or with `gdb`:
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```
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$ riscv64-unknown-elf-gdb /path/to/elf
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(gdb) target remote localhost:3333
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(gdb) load
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Loading section .text, size 0x6508 lma 0x80000000
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Loading section .rodata, size 0x900 lma 0x80006508
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(gdb) b putchar
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(gdb) c
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Continuing.
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@ -186,7 +226,7 @@ $ make
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$ [sudo] make install
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```
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### Tandem Verification with Spike
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<!-- ### Tandem Verification with Spike
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```
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$ make sim preload=/home/zarubaf/Downloads/riscv-tests/build/benchmarks/dhrystone.riscv tandem=1
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@ -200,6 +240,7 @@ There are a couple of caveats:
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- The RTC clock needs to be sufficiently slow (e.g.: 32 kHz seems to work). This is needed as otherwise there will be a difference when reading the `mtime` register as the RTL simulation takes more time to propagate the information through the system.
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- All traps except memory traps need to zero the `tval` register. There is a switch you can set in `ariane_pkg`.
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- `mcycle` needs to be incremented with `instret` to be similar to the performance counters found in Spike (IPC = 1)
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-->
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### Re-generating the Bootcode (ZSBL)
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@ -8,7 +8,7 @@
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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// Top-level for Genesys 2
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// Xilinx FPGA top-level
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module ariane_xilinx (
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`ifdef VCU118
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input wire c0_sys_clk_p , // 250 MHz Clock for DDR
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@ -170,29 +170,6 @@ assign ndmreset_n = ~ndmreset ;
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logic [NBSlave-1:0] pc_asserted;
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// ila_0 i_ila_0 (
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// .clk(clk), // input wire clk
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// .probe0(tck), // input wire [63:0] probe0
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// .probe1(tdo), // input wire [63:0] probe1
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// .probe2(tdi), // input wire [0:0] probe2
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// .probe3(tms), // input wire [0:0] probe3
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// .probe4(trst_n), // input wire [0:0] probe4
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// .probe5(ndmreset), // input wire [1:0] probe5
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// .probe6(rst_n), // input wire [0:0] probe6
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// .probe7(cpu_reset), // input wire [0:0] probe7
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// .probe8(1'b0), // input wire [0:0] probe8
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// .probe9(slave_slice[3].aw_addr), // input wire [0:0] probe10
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// .probe10(slave_slice[3].aw_valid), // input wire [0:0] probe11
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// .probe11(slave_slice[3].aw_ready), // input wire [0:0] probe12
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// .probe12(pcie_axi_araddr), // input wire [0:0] probe13
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// .probe13(pcie_axi_arvalid), // input wire [0:0] probe14
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// .probe14(pcie_axi_arready),
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// .probe15(rtc),
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// .probe16(debug_req_valid),
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// .probe17(debug_req_ready),
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// .probe18(debug_req)
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// );
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// Slice the AXI Masters (slave ports on the XBar)
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for (genvar i = 0; i < NBSlave; i++) begin : slave_cut_gen
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axi_cut #(
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@ -67,7 +67,7 @@
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current-speed = <115200>;
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interrupt-parent = <&PLIC0>;
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interrupts = <1>;
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reg-shift = <2>; //regs are spaced on 32 bit boundary
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reg-shift = <2>; // regs are spaced on 32 bit boundary
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reg-io-width = <4>; // only 32-bit access are supported
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};
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// xlnx_axi_ethernetlite: ethernet@12000000 {
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@ -60,6 +60,7 @@ package ariane_pkg;
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// enables a commit log which matches spikes commit log format for easier trace comparison
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localparam bit ENABLE_SPIKE_COMMIT_LOG = 1'b0;
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// ------------- Dangerouse -------------
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// if set to zero a flush will not invalidate the cache-lines, in a single core environment
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// where coherence is not necessary this can improve performance. This needs to be switched on
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@ -67,11 +68,11 @@ package ariane_pkg;
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localparam logic INVALIDATE_ON_FLUSH = 1'b1;
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// enable performance cycle counter, if set to zero mcycle will be incremented
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// with instret (non RISC-V conformal)
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localparam bit ENABLE_CYCLE_COUNT = 1'b0;
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localparam bit ENABLE_CYCLE_COUNT = 1'b1;
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// mark WIF as nop
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localparam bit ENABLE_WFI = 1'b0;
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// this is Spike behaviour
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localparam bit ZERO_TVAL = 1'b1;
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localparam bit ENABLE_WFI = 1'b1;
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// Spike zeros tval on all exception except memory faults
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localparam bit ZERO_TVAL = 1'b0;
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// read mask for SSTATUS over MMSTATUS
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localparam logic [63:0] SMODE_STATUS_READ_MASK = riscv::SSTATUS_UIE
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@ -924,7 +924,7 @@ module csr_regfile #(
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mcause_q <= 64'b0;
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mscratch_q <= 64'b0;
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mtval_q <= 64'b0;
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dcache_q <= 64'b0;
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dcache_q <= 64'b1;
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icache_q <= 64'b1;
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// supervisor mode registers
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sepc_q <= 64'b0;
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