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define riscv-isa-manual as submodule (#2052)

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* remove riscv-isa-manual vendor

* Define riscv-isa-manual as submodule
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.gitmodules vendored
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[submodule "verif/sim/dv"]
path = verif/sim/dv
url = https://github.com/google/riscv-dv.git
[submodule "docs/06_cv32a65x_riscv/riscv-isa-manual"]
path = docs/06_cv32a65x_riscv/riscv-isa-manual
url = https://github.com/riscv/riscv-isa-manual.git

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docs/06_cv32a65x_riscv/riscv-isa-manual Submodule

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Subproject commit 217b3f8cdbd94583f4933bb7c7b35bae3e70f74d

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.DS_Store
.*.swp

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vendor/riscv/riscv-isa-manual/LICENSE vendored
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# RISC-V Instruction Set Manual
[![RISC-V ISA Build](https://github.com/riscv/riscv-isa-manual/actions/workflows/isa-build.yml/badge.svg)](https://github.com/riscv/riscv-isa-manual/actions/workflows/isa-build.yml)
This repository contains the source files for the RISC-V Instruction Set Manual, which is comprised of the Privileged RISC-V Instruction Set Manual (LaTeX) and the Unprivileged RISC-V Instruction Set Manual (AsciiDoc). The preface of each document indicates the version of each standard that has been formally ratified by RISC-V International.
This work is licensed under a [Creative Commons Attribution 4.0 International License](https://creativecommons.org/licenses/by/4.0/). See the [LICENSE](LICENSE) file for details.
The RISC-V Instruction Set Manual is organized into the following volumes:
- Volume I: User-Level ISA
- Volume II: Privileged Architecture
## Official and Draft Versions
- **Official versions** of the specifications are available at the [RISC-V International website](https://riscv.org/specifications/).
- **Compiled versions of the most recent drafts** of the specifications can be found on the [GitHub releases page](https://github.com/riscv/riscv-isa-manual/releases/latest).
- **Older official versions** of the specifications are archived at the [GitHub releases archive](https://github.com/riscv/riscv-isa-manual/releases/tag/archive).
The canonical list of **open-source RISC-V implementations' marchid CSR values** is available in the [marchid.md file](https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md).
## Contributing
If you would like to contribute to this documentation, please refer to the [Documentation Developer's Guide](https://github.com/riscv/docs-dev-guide).
The recommended method for building the PDF files is to use the Docker Image, as described in the [RISC-V Docs Base Container Image repository](https://github.com/riscv/riscv-docs-base-container-image).
Alternative build methods, such as local builds and GitHub Action builds, are also available and described in the Documentation Developer's Guide.

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*.aux
*.bbl
*.blg
*.html
*.log
*.out
*.pdf
*.pdf.tmp
*.toc
images
.asciidoctor

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# Makefile for RISC-V ISA Manuals
#
# This work is licensed under the Creative Commons Attribution-ShareAlike 4.0
# International License. To view a copy of this license, visit
# http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to
# Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.
#
# SPDX-License-Identifier: CC-BY-SA-4.0
#
# Description:
#
# This Makefile is designed to automate the process of building and packaging
# the documentation for RISC-V ISA Manuals. It supports multiple build targets
# for generating documentation in various formats (PDF, HTML).
# Build Targets
TARGETS := priv unpriv priv-html unpriv-html priv-latex
# Declare phony targets
.PHONY: all $(TARGETS) clean
# Default target builds all
all: $(TARGETS)
# Build with preinstalled docker container; first install it with:
# docker pull riscvintl/riscv-docs-base-container-image:latest
docker:
cd .. && docker run -it -v .:/build riscvintl/riscv-docs-base-container-image:latest /bin/sh -c 'cd ./build; make'
# Asciidoctor options
ASCIIDOCTOR_OPTS := -a compress \
--attribute=mathematical-format=svg \
--failure-level=ERROR \
--require=asciidoctor-bibtex \
--require=asciidoctor-diagram \
--require=asciidoctor-mathematical \
--trace
# Source directory
SRCDIR := ../src
# LaTeX source and related files
SRCS := $(wildcard $(SRCDIR)/latex/*.tex)
FIGS := $(wildcard $(SRCDIR)/latex/figs/*)
BIBS := $(SRCDIR)/latex/riscv-spec.bib
# LaTeX build tools
PDFLATEX := TEXINPUTS=$(SRCDIR)/latex: pdflatex -interaction=nonstopmode -halt-on-error
BIBTEX := BIBINPUTS=$(SRCDIR)/latex: bibtex
# Temporary files to clean up for LaTeX build
JUNK := *.pdf *.aux *.log *.bbl *.blg *.toc *.out *.fdb_latexmk *.fls *.synctex.gz
# Privileged ISA build
priv: priv-isa-asciidoc.pdf
priv-isa-asciidoc.pdf: $(SRCDIR)/riscv-privileged.adoc $(SRCDIR)/*.adoc
@echo "Building Privileged ISA"
rm -f $@.tmp
asciidoctor-pdf $(ASCIIDOCTOR_OPTS) --out-file=$@.tmp $<
mv $@.tmp $@
# Unprivileged ISA build
unpriv: unpriv-isa-asciidoc.pdf
unpriv-isa-asciidoc.pdf: $(SRCDIR)/riscv-unprivileged.adoc $(SRCDIR)/*.adoc
@echo "Building Unprivileged ISA"
rm -f $@.tmp
asciidoctor-pdf $(ASCIIDOCTOR_OPTS) --out-file=$@.tmp $<
mv $@.tmp $@
# Privileged ISA HTML build
priv-html: priv-isa-asciidoc.html
priv-isa-asciidoc.html: $(SRCDIR)/riscv-privileged.adoc
@echo "Building Privileged ISA HTML"
asciidoctor $(ASCIIDOCTOR_OPTS) --out-file=$@ $<
# Unprivileged ISA HTML build
unpriv-html: unpriv-isa-asciidoc.html
unpriv-isa-asciidoc.html: $(SRCDIR)/riscv-unprivileged.adoc
@echo "Building Unprivileged ISA HTML"
asciidoctor $(ASCIIDOCTOR_OPTS) --out-file=$@ $<
# LaTeX build for Privileged ISA
priv-latex: riscv-privileged.pdf
riscv-privileged.pdf: $(SRCDIR)/latex/riscv-privileged.tex $(SRCS) $(FIGS) $(BIBS)
$(PDFLATEX) riscv-privileged
$(BIBTEX) riscv-privileged
$(PDFLATEX) riscv-privileged
$(PDFLATEX) riscv-privileged
clean:
@if [ -f priv-isa-asciidoc.pdf ]; then \
echo "Removing priv-isa-asciidoc.pdf"; \
rm -f priv-isa-asciidoc.pdf; \
fi
@if [ -f unpriv-isa-asciidoc.pdf ]; then \
echo "Removing unpriv-isa-asciidoc.pdf"; \
rm -f unpriv-isa-asciidoc.pdf; \
fi
@if [ -f priv-isa-asciidoc.html ]; then \
echo "Removing priv-isa-asciidoc.html"; \
rm -f priv-isa-asciidoc.html; \
fi
@if [ -f unpriv-isa-asciidoc.html ]; then \
echo "Removing unpriv-isa-asciidoc.html"; \
rm -f unpriv-isa-asciidoc.html; \
fi
@echo "Cleaning up files from LaTeX build"
@cd $(SRCDIR)/latex; \
for file in $(JUNK); do \
if [ -f "$$file" ]; then \
echo "Removing $$file"; \
rm -f "$$file"; \
fi; \
done

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source 'https://rubygems.org'
gem 'asciidoctor'
gem 'asciidoctor-bibtex'
gem 'asciidoctor-diagram'
gem 'asciidoctor-mathematical'
gem 'asciidoctor-pdf'
gem 'citeproc-ruby'
gem 'coderay'
gem 'csl-styles'
gem 'json'
gem 'pygments.rb'
gem 'rghost'
gem 'rouge'
gem 'ruby_dev'

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Dependencies for the build environment for various package managers. Used in
`.github/workflows/`.

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bison
build-essential
cmake
curl
flex
fonts-lyx
git
graphviz
# For wavedrom
default-jre
libcairo2-dev
libffi-dev
libgdk-pixbuf2.0-dev
libglib2.0-dev
libpango1.0-dev
libxml2-dev
make
pkg-config
ruby
ruby-dev
libwebp-dev
libzstd-dev

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vendor/riscv/riscv-isa-manual/dependencies/package.json vendored
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{
"name": "local",
"version": "0.0.1",
"dependencies": {
"wavedrom-cli": "^2.6.8",
"bytefield-svg": "^1.8.0"
}
}

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Open-Source RISC-V Architecture IDs
========================================
Every RISC-V hart provides an marchid CSR that encodes its base
microarchitecture. Any hart may report an architecture ID of 0, indicating
unspecified origin. Commercial implementations (those with nonzero mvendorid)
may encode any value in marchid with the most-significant bit set, with the
low-order bits formatted in a vendor-specific manner. Open-source
implementations (which may or may not have a nonzero mvendorid) have the
most-significant bit clear, with a globally unique pattern in the low-order
bits.
This document contains the canonical list of open-source RISC-V implementations
and their architecture IDs. Open-source project maintainers may make pull
requests against this repository to request the allocation of an architecture
ID.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Project Name | Maintainers | Point of Contact | Architecture ID | Project URL
------------- | ------------------------------- | ----------------------------------------------------------- | ----------------- | ---------------------------------------------------
Rocket | SiFive, UC Berkeley | [Andrew Waterman](mailto:andrew@sifive.com), SiFive | 1 | https://github.com/chipsalliance/rocket-chip
BOOM | UC Berkeley | [Christopher Celio](mailto:celio@berkeley.edu) | 2 | https://github.com/riscv-boom/riscv-boom
CVA6 | OpenHW Group | [Florian Zaruba](mailto:florian@openhwgroup.org), OpenHW Group | 3 | https://github.com/openhwgroup/cva6
CV32E40P | OpenHW Group | [Davide Schiavone](mailto:davide@openhwgroup.org), OpenHW Group | 4 | https://github.com/openhwgroup/cv32e40p
Spike | SiFive, UC Berkeley | [Andrew Waterman](mailto:andrew@sifive.com), SiFive | 5 | https://github.com/riscv/riscv-isa-sim
E-Class | IIT Madras | [Neel Gala](mailto:neelgala@gmail.com) | 6 | https://gitlab.com/shaktiproject/cores/e-class
ORCA | VectorBlox | [Joel Vandergriendt](mailto:joel@vectorblox.com) | 7 | https://github.com/vectorblox/orca
SCR1 | Syntacore | [Dmitri Pavlov](mailto:dmitri.pavlov@syntacore.com), Syntacore| 8 | https://github.com/syntacore/scr1
YARVI | Tommy Thorn's Priceless Services| [Tommy Thorn](mailto:tommy-github2@thorn.ws) | 9 | https://github.com/tommythorn/yarvi
RVBS | Alexandre Joannou, University of Cambridge| [Alexandre Joannou](mailto:aj443@cl.cam.ac.uk) | 10 | https://github.com/CTSRD-CHERI/RVBS
SweRV EH1 | Western Digital Corporation | [Thomas Wicki](mailto:Thomas.Wicki@wdc.com) | 11 | https://github.com/chipsalliance/Cores-SweRV
MSCC | Rongcui Dong | [Rongcui Dong](mailto:rongcuid@outlook.com) | 12 | https://github.com/rongcuid/MSCC
BlackParrot | The World | [Michael B. Taylor](mailto:prof.taylor@gmail.com), U. Washington | 13 | https://github.com/black-parrot
BaseJump Manycore | U. Washington | [Michael B. Taylor](mailto:prof.taylor@gmail.com), U. Washington | 14 | https://github.com/bespoke-silicon-group/bsg_manycore
C-Class | IIT Madras | [Neel Gala](mailto:neelgala@gmail.com) | 15 | https://gitlab.com/shaktiproject/cores/c-class
SweRV EL2 | Western Digital Corporation | [Thomas Wicki](mailto:Thomas.Wicki@wdc.com) | 16 | https://github.com/chipsalliance/Cores-SweRV-EL2
SweRV EH2 | Western Digital Corporation | [Thomas Wicki](mailto:Thomas.Wicki@wdc.com) | 17 | https://github.com/chipsalliance/Cores-SweRV-EH2
SERV | Olof Kindgren Enterprises | [Olof Kindgren](mailto:olof.kindgren@gmail.com) | 18 | https://github.com/olofk/serv
NEORV32 | Stephan Nolting | [Stephan Nolting](mailto:stnolting@gmail.com) | 19 | https://github.com/stnolting/neorv32
CV32E40X | OpenHW Group | [Arjan Bink](mailto:arjan.bink@silabs.com), Silicon Laboratories | 20 | https://github.com/openhwgroup/cv32e40x
CV32E40S | OpenHW Group | [Arjan Bink](mailto:arjan.bink@silabs.com), Silicon Laboratories | 21 | https://github.com/openhwgroup/cv32e40s
Ibex | lowRISC | [lowRISC Hardware Team](mailto:hardware@lowrisc.org) | 22 | https://github.com/lowRISC/ibex
RudolV | Jörg Mische | [Jörg Mische](mailto:bobbl@gmx.de) | 23 | https://github.com/bobbl/rudolv
Steel Core | Rafael Calcada | [Rafael Calcada](mailto:rafaelcalcada@gmail.com) | 24 | https://github.com/rafaelcalcada/steel-core
XiangShan | ICT, CAS | [XiangShan Team](mailto:xiangshan-all@ict.ac.cn) | 25 | https://github.com/OpenXiangShan/XiangShan
Hummingbirdv2 E203 | Nuclei System Technology | [Can Hu](mailto:canhu@nucleisys.com), Nuclei System Technology | 26 | https://github.com/riscv-mcu/e203_hbirdv2
Hazard3 | Luke Wren | [Luke Wren](mailto:wren6991@gmail.com) | 27 | https://github.com/wren6991/hazard3
CV32E41P | OpenHW Group | [Mark Hill](mailto:mark.hill@huawei.com), OpenHW Group | 28 | https://github.com/openhwgroup/cv32e41p
Rift | Jianhu Lab, WUT | [Ruige Lee](mailto:295054118@whut.edu.cn) | 29 | [RiftCore](https://github.com/whutddk/RiftCore), [Rift2Core](https://github.com/whutddk/Rift2Core)
RISu064 | Wenting Zhang | [Wenting Zhang](mailto:zephray@outlook.com) | 30 | https://github.com/zephray/RISu064
AIRISC | Fraunhofer IMS | [AIRISC Support](mailto:airisc@ims.fraunhofer.de) | 31 | https://github.com/Fraunhofer-IMS/airisc_core_complex
Proteus | imec-DistriNet, KU Leuven | [Marton Bognar](mailto:marton.bognar@kuleuven.be) | 32 | https://github.com/proteus-core/proteus
VexRiscv | SpinalHDL | [Charles Papon](mailto:charles.papon.90@gmail.com) | 33 | https://github.com/SpinalHDL/VexRiscv
Shuttle | UC Berkeley | [Jerry Zhao](mailto:jerryz123@berkeley.edu) | 34 | https://github.com/ucb-bar/shuttle
CV32E2 | OpenHW Group | [Davide Schiavone](mailto:davide@openhwgroup.org), OpenHW Group | 35 | https://github.com/openhwgroup/cve2

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[[atomics]]
== "A" Standard Extension for Atomic Instructions, Version 2.1
The standard atomic-instruction extension, named "A", contains
instructions that atomically read-modify-write memory to support
synchronization between multiple RISC-V harts running in the same memory
space. The two forms of atomic instruction provided are
load-reserved/store-conditional instructions and atomic fetch-and-op
memory instructions. Both types of atomic instruction support various
memory consistency orderings including unordered, acquire, release, and
sequentially consistent semantics. These instructions allow RISC-V to
support the RCsc memory consistency model. cite:[Gharachorloo90memoryconsistency]
[NOTE]
====
After much debate, the language community and architecture community
appear to have finally settled on release consistency as the standard
memory consistency model and so the RISC-V atomic support is built
around this model.
====
=== Specifying Ordering of Atomic Instructions
The base RISC-V ISA has a relaxed memory model, with the FENCE
instruction used to impose additional ordering constraints. The address
space is divided by the execution environment into memory and I/O
domains, and the FENCE instruction provides options to order accesses to
one or both of these two address domains.
To provide more efficient support for release consistency cite:[Gharachorloo90memoryconsistency], each atomic
instruction has two bits, _aq_ and _rl_, used to specify additional
memory ordering constraints as viewed by other RISC-V harts. The bits
order accesses to one of the two address domains, memory or I/O,
depending on which address domain the atomic instruction is accessing.
No ordering constraint is implied to accesses to the other domain, and a
FENCE instruction should be used to order across both domains.
If both bits are clear, no additional ordering constraints are imposed
on the atomic memory operation. If only the _aq_ bit is set, the atomic
memory operation is treated as an _acquire_ access, i.e., no following
memory operations on this RISC-V hart can be observed to take place
before the acquire memory operation. If only the _rl_ bit is set, the
atomic memory operation is treated as a _release_ access, i.e., the
release memory operation cannot be observed to take place before any
earlier memory operations on this RISC-V hart. If both the _aq_ and _rl_
bits are set, the atomic memory operation is _sequentially consistent_
and cannot be observed to happen before any earlier memory operations or
after any later memory operations in the same RISC-V hart and to the
same address domain.
[[sec:lrsc]]
=== Load-Reserved/Store-Conditional Instructions
include::images/wavedrom/load-reserve-st-conditional.adoc[]
Complex atomic memory operations on a single memory word or doubleword
are performed with the load-reserved (LR) and store-conditional (SC)
instructions. LR.W loads a word from the address in _rs1_, places the
sign-extended value in _rd_, and registers a _reservation set_—a set of
bytes that subsumes the bytes in the addressed word. SC.W conditionally
writes a word in _rs2_ to the address in _rs1_: the SC.W succeeds only
if the reservation is still valid and the reservation set contains the
bytes being written. If the SC.W succeeds, the instruction writes the
word in _rs2_ to memory, and it writes zero to _rd_. If the SC.W fails,
the instruction does not write to memory, and it writes a nonzero value
to _rd_. Regardless of success or failure, executing an SC.W instruction
invalidates any reservation held by this hart. LR.D and SC.D act
analogously on doublewords and are only available on RV64. For RV64,
LR.W and SC.W sign-extend the value placed in _rd_.
[NOTE]
====
Both compare-and-swap (CAS) and LR/SC can be used to build lock-free
data structures. After extensive discussion, we opted for LR/SC for
several reasons: 1) CAS suffers from the ABA problem, which LR/SC avoids
because it monitors all writes to the address rather than only checking
for changes in the data value; 2) CAS would also require a new integer
instruction format to support three source operands (address, compare
value, swap value) as well as a different memory system message format,
which would complicate microarchitectures; 3) Furthermore, to avoid the
ABA problem, other systems provide a double-wide CAS (DW-CAS) to allow a
counter to be tested and incremented along with a data word. This
requires reading five registers and writing two in one instruction, and
also a new larger memory system message type, further complicating
implementations; 4) LR/SC provides a more efficient implementation of
many primitives as it only requires one load as opposed to two with CAS
(one load before the CAS instruction to obtain a value for speculative
computation, then a second load as part of the CAS instruction to check
if value is unchanged before updating).
The main disadvantage of LR/SC over CAS is livelock, which we avoid,
under certain circumstances, with an architected guarantee of eventual
forward progress as described below. Another concern is whether the
influence of the current x86 architecture, with its DW-CAS, will
complicate porting of synchronization libraries and other software that
assumes DW-CAS is the basic machine primitive. A possible mitigating
factor is the recent addition of transactional memory instructions to
x86, which might cause a move away from DW-CAS.
More generally, a multi-word atomic primitive is desirable, but there is
still considerable debate about what form this should take, and
guaranteeing forward progress adds complexity to a system.
====
The failure code with value 1 encodes an unspecified failure. Other
failure codes are reserved at this time. Portable software should only
assume the failure code will be non-zero.
[NOTE]
====
We reserve a failure code of 1 to mean ''unspecified'' so that simple
implementations may return this value using the existing mux required
for the SLT/SLTU instructions. More specific failure codes might be
defined in future versions or extensions to the ISA.
====
For LR and SC, the A extension requires that the address held in _rs1_
be naturally aligned to the size of the operand (i.e., eight-byte
aligned for _doublewords_ and four-byte aligned for _words_). If the
address is not naturally aligned, an address-misaligned exception or an
access-fault exception will be generated. The access-fault exception can
be generated for a memory access that would otherwise be able to
complete except for the misalignment, if the misaligned access should
not be emulated.
[NOTE]
====
Emulating misaligned LR/SC sequences is impractical in most systems.
Misaligned LR/SC sequences also raise the possibility of accessing
multiple reservation sets at once, which present definitions do not
provide for.
====
An implementation can register an arbitrarily large reservation set on
each LR, provided the reservation set includes all bytes of the
addressed data word or doubleword. An SC can only pair with the most
recent LR in program order. An SC may succeed only if no store from
another hart to the reservation set can be observed to have occurred
between the LR and the SC, and if there is no other SC between the LR
and itself in program order. An SC may succeed only if no write from a
device other than a hart to the bytes accessed by the LR instruction can
be observed to have occurred between the LR and SC. Note this LR might
have had a different effective address and data size, but reserved the
SC's address as part of the reservation set.
[NOTE]
====
Following this model, in systems with memory translation, an SC is
allowed to succeed if the earlier LR reserved the same location using an
alias with a different virtual address, but is also allowed to fail if
the virtual address is different.
To accommodate legacy devices and buses, writes from devices other than
RISC-V harts are only required to invalidate reservations when they
overlap the bytes accessed by the LR. These writes are not required to
invalidate the reservation when they access other bytes in the
reservation set.
====
The SC must fail if the address is not within the reservation set of the
most recent LR in program order. The SC must fail if a store to the
reservation set from another hart can be observed to occur between the
LR and SC. The SC must fail if a write from some other device to the
bytes accessed by the LR can be observed to occur between the LR and SC.
(If such a device writes the reservation set but does not write the
bytes accessed by the LR, the SC may or may not fail.) An SC must fail
if there is another SC (to any address) between the LR and the SC in
program order. The precise statement of the atomicity requirements for
successful LR/SC sequences is defined by the Atomicity Axiom in
<<rvwmo>>.
[NOTE]
====
The platform should provide a means to determine the size and shape of
the reservation set.
A platform specification may constrain the size and shape of the
reservation set.
A store-conditional instruction to a scratch word of memory should be
used to forcibly invalidate any existing load reservation:
* during a preemptive context switch, and
* if necessary when changing virtual to physical address mappings, such
as when migrating pages that might contain an active reservation.
The invalidation of a hart's reservation when it executes an LR or SC
imply that a hart can only hold one reservation at a time, and that an
SC can only pair with the most recent LR, and LR with the next following
SC, in program order. This is a restriction to the Atomicity Axiom in
<<rvwmo>> that ensures software runs correctly on
expected common implementations that operate in this manner.
====
An SC instruction can never be observed by another RISC-V hart before
the LR instruction that established the reservation.
[NOTE]
====
The LR/SC sequence
can be given acquire semantics by setting the _aq_ bit on the LR
instruction. The LR/SC sequence can be given release semantics by
by setting the _rl_ bit on the SC instruction. Assuming
suitable mappings for other atomic operations, setting the
_aq_ bit on the LR instruction, and setting the
_rl_ bit on the SC instruction makes the LR/SC
sequence sequentially consistent in the C\++ `memory_order_seq_cst`
sense. Such a sequence does not act as a fence for ordering ordinary
load and store instructions before and after the sequence. Specific
instruction mappings for other C++ atomic operations,
or stronger notions of "sequential consistency", may require both
bits to be set on either or both of the LR or SC instruction.
If neither bit is set on either LR or SC, the LR/SC sequence can be
observed to occur before or after surrounding memory operations from the
same RISC-V hart. This can be appropriate when the LR/SC sequence is
used to implement a parallel reduction operation.
====
Software should not set the _rl_ bit on an LR instruction unless the
_aq_ bit is also set, nor should software set the _aq_ bit on an SC
instruction unless the _rl_ bit is also set. LR._rl_ and SC._aq_
instructions are not guaranteed to provide any stronger ordering than
those with both bits clear, but may result in lower performance.
<<<
[[cas]]
[source,asm]
.Sample code for compare-and-swap function using LR/SC.
# a0 holds address of memory location
# a1 holds expected value
# a2 holds desired value
# a0 holds return value, 0 if successful, !0 otherwise
cas:
lr.w t0, (a0) # Load original value.
bne t0, a1, fail # Doesn't match, so fail.
sc.w t0, a2, (a0) # Try to update.
bnez t0, cas # Retry if store-conditional failed.
li a0, 0 # Set return to success.
jr ra # Return.
fail:
li a0, 1 # Set return to failure.
jr ra # Return.
LR/SC can be used to construct lock-free data structures. An example
using LR/SC to implement a compare-and-swap function is shown in
<<cas>>. If inlined, compare-and-swap functionality need only take four instructions.
[[sec:lrscseq]]
=== Eventual Success of Store-Conditional Instructions
The standard A extension defines _constrained LR/SC loops_, which have
the following properties:
* The loop comprises only an LR/SC sequence and code to retry the
sequence in the case of failure, and must comprise at most 16
instructions placed sequentially in memory.
* An LR/SC sequence begins with an LR instruction and ends with an SC
instruction. The dynamic code executed between the LR and SC
instructions can only contain instructions from the base ''I''
instruction set, excluding loads, stores, backward jumps, taken backward
branches, JALR, FENCE, and SYSTEM instructions. If the ''C'' extension
is supported, then compressed forms of the aforementioned ''I''
instructions are also permitted.
* The code to retry a failing LR/SC sequence can contain backwards jumps
and/or branches to repeat the LR/SC sequence, but otherwise has the same
constraint as the code between the LR and SC.
* The LR and SC addresses must lie within a memory region with the
_LR/SC eventuality_ property. The execution environment is responsible
for communicating which regions have this property.
* The SC must be to the same effective address and of the same data size
as the latest LR executed by the same hart.
LR/SC sequences that do not lie within constrained LR/SC loops are
_unconstrained_. Unconstrained LR/SC sequences might succeed on some
attempts on some implementations, but might never succeed on other
implementations.
[NOTE]
====
We restricted the length of LR/SC loops to fit within 64 contiguous
instruction bytes in the base ISA to avoid undue restrictions on
instruction cache and TLB size and associativity. Similarly, we
disallowed other loads and stores within the loops to avoid restrictions
on data-cache associativity in simple implementations that track the
reservation within a private cache. The restrictions on branches and
jumps limit the time that can be spent in the sequence. Floating-point
operations and integer multiply/divide were disallowed to simplify the
operating system's emulation of these instructions on implementations
lacking appropriate hardware support.
Software is not forbidden from using unconstrained LR/SC sequences, but
portable software must detect the case that the sequence repeatedly
fails, then fall back to an alternate code sequence that does not rely
on an unconstrained LR/SC sequence. Implementations are permitted to
unconditionally fail any unconstrained LR/SC sequence.
====
If a hart _H_ enters a constrained LR/SC loop, the execution environment
must guarantee that one of the following events eventually occurs:
* _H_ or some other hart executes a successful SC to the reservation set
of the LR instruction in _H_'s constrained LR/SC loops.
* Some other hart executes an unconditional store or AMO instruction to
the reservation set of the LR instruction in _H_'s constrained LR/SC
loop, or some other device in the system writes to that reservation set.
* _H_ executes a branch or jump that exits the constrained LR/SC loop.
* _H_ traps.
[NOTE]
====
Note that these definitions permit an implementation to fail an SC
instruction occasionally for any reason, provided the aforementioned
guarantee is not violated.
As a consequence of the eventuality guarantee, if some harts in an
execution environment are executing constrained LR/SC loops, and no
other harts or devices in the execution environment execute an
unconditional store or AMO to that reservation set, then at least one
hart will eventually exit its constrained LR/SC loop. By contrast, if
other harts or devices continue to write to that reservation set, it is
not guaranteed that any hart will exit its LR/SC loop.
Loads and load-reserved instructions do not by themselves impede the
progress of other harts' LR/SC sequences. We note this constraint
implies, among other things, that loads and load-reserved instructions
executed by other harts (possibly within the same core) cannot impede
LR/SC progress indefinitely. For example, cache evictions caused by
another hart sharing the cache cannot impede LR/SC progress
indefinitely. Typically, this implies reservations are tracked
independently of evictions from any shared cache. Similarly, cache
misses caused by speculative execution within a hart cannot impede LR/SC
progress indefinitely.
These definitions admit the possibility that SC instructions may
spuriously fail for implementation reasons, provided progress is
eventually made.
One advantage of CAS is that it guarantees that some hart eventually
makes progress, whereas an LR/SC atomic sequence could livelock
indefinitely on some systems. To avoid this concern, we added an
architectural guarantee of livelock freedom for certain LR/SC sequences.
Earlier versions of this specification imposed a stronger
starvation-freedom guarantee. However, the weaker livelock-freedom
guarantee is sufficient to implement the C11 and C++11 languages, and is
substantially easier to provide in some microarchitectural styles.
====
[[sec:amo]]
=== Atomic Memory Operations
include::images/wavedrom/atomic-mem.adoc[]
The atomic memory operation (AMO) instructions perform read-modify-write
operations for multiprocessor synchronization and are encoded with an
R-type instruction format. These AMO instructions atomically load a data
value from the address in _rs1_, place the value into register _rd_,
apply a binary operator to the loaded value and the original value in
_rs2_, then store the result back to the original address in _rs1_. AMOs
can either operate on _doublewords_ (RV64 only) or _words_ in memory. For
RV64, 32-bit AMOs always sign-extend the value placed in _rd_, and
ignore the upper 32 bits of the original value of _rs2_.
For AMOs, the A extension requires that the address held in _rs1_ be
naturally aligned to the size of the operand (i.e., eight-byte aligned
for _doublewords_ and four-byte aligned for _words_). If the address
is not naturally aligned, an address-misaligned exception or an
access-fault exception will be generated. The access-fault exception can
be generated for a memory access that would otherwise be able to
complete except for the misalignment, if the misaligned access should
not be emulated. The "Zam" extension, described in <<zam>>, relaxes this requirement and specifies the semantics of misaligned AMOs.
The operations supported are swap, integer add, bitwise AND, bitwise OR,
bitwise XOR, and signed and unsigned integer maximum and minimum.
Without ordering constraints, these AMOs can be used to implement
parallel reduction operations, where typically the return value would be
discarded by writing to `x0`.
[NOTE]
====
We provided fetch-and-op style atomic primitives as they scale to highly
parallel systems better than LR/SC or CAS. A simple microarchitecture
can implement AMOs using the LR/SC primitives, provided the
implementation can guarantee the AMO eventually completes. More complex
implementations might also implement AMOs at memory controllers, and can
optimize away fetching the original value when the destination is `x0`.
The set of AMOs was chosen to support the C11/C++11 atomic memory
operations efficiently, and also to support parallel reductions in
memory. Another use of AMOs is to provide atomic updates to
memory-mapped device registers (e.g., setting, clearing, or toggling
bits) in the I/O space.
====
To help implement multiprocessor synchronization, the AMOs optionally
provide release consistency semantics. If the _aq_ bit is set, then no
later memory operations in this RISC-V hart can be observed to take
place before the AMO. Conversely, if the _rl_ bit is set, then other
RISC-V harts will not observe the AMO before memory accesses preceding
the AMO in this RISC-V hart. Setting both the _aq_ and the _rl_ bit on
an AMO makes the sequence sequentially consistent, meaning that it
cannot be reordered with earlier or later memory operations from the
same hart.
[NOTE]
====
The AMOs were designed to implement the C11 and C++11 memory models
efficiently. Although the FENCE R, RW instruction suffices to implement
the _acquire_ operation and FENCE RW, W suffices to implement _release_,
both imply additional unnecessary ordering as compared to AMOs with the
corresponding _aq_ or _rl_ bit set.
====
An example code sequence for a critical section guarded by a
test-and-test-and-set spinlock is shown in
Example <<critical>>. Note the first AMO is marked _aq_ to
order the lock acquisition before the critical section, and the second
AMO is marked _rl_ to order the critical section before the lock
relinquishment.
<<<
[[critical]]
[source,asm]
.Sample code for mutual exclusion. `a0` contains the address of the lock.
li t0, 1 # Initialize swap value.
again:
lw t1, (a0) # Check if lock is held.
bnez t1, again # Retry if held.
amoswap.w.aq t1, t0, (a0) # Attempt to acquire lock.
bnez t1, again # Retry if held.
# ...
# Critical section.
# ...
amoswap.w.rl x0, x0, (a0) # Release lock by storing 0.
[NOTE]
====
We recommend the use of the AMO Swap idiom shown above for both lock
acquire and release to simplify the implementation of speculative lock
elision. cite:[Rajwar:2001:SLE]
====
[NOTE]
====
The instructions in the "A" extension can be used to provide sequentially
consistent loads and stores, but this constrains hardware
reordering of memory accesses more than necessary.
A C++ sequentially consistent load can be implemented as
an LR with _aq_ set. However, the LR/SC eventual
success guarantee may slow down concurrent loads from the same effective
address. A sequentially consistent store can be implemented as an AMOSWAP
that writes the old value to `x0` and has _rl_ set. However the superfluous
load may impose ordering constraints that are unnecessary for this use case.
Specific compilation conventions may require both the _aq_ and _rl_
bits to be set in either or both the LR and AMOSWAP instructions.
====

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[[bits]]
== "B" Standard Extension for Bit Manipulation, Version 0.0
This chapter is a placeholder for a future standard extension to provide
bit manipulation instructions, including instructions to insert,
extract, and test bit fields, and for rotations, funnel shifts, and bit
and byte permutations.
[NOTE]
====
Although bit manipulation instructions are very effective in some
application domains, particularly when dealing with externally packed
data structures, we excluded them from the base ISAs as they are not
useful in all domains and can add additional complexity or instruction
formats to supply all needed operands.
We anticipate the B extension will be a brownfield encoding within the
base 30-bit instruction space.
====

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[bibliography]
== Bibliography
bibliography::[]

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[[compressed]]
== "C" Standard Extension for Compressed Instructions, Version 2.0
This chapter describes the RISC-V standard compressed instruction-set
extension, named "C", which reduces static and dynamic code size by
adding short 16-bit instruction encodings for common operations. The C
extension can be added to any of the base ISAs (RV32, RV64, RV128), and
we use the generic term "RVC" to cover any of these. Typically,
50%-60% of the RISC-V instructions in a program can be replaced with RVC
instructions, resulting in a 25%-30% code-size reduction.
=== Overview
RVC uses a simple compression scheme that offers shorter 16-bit versions
of common 32-bit RISC-V instructions when:
* the immediate or address offset is small, or
* one of the registers is the zero register (`x0`), the ABI link register
(`x1`), or the ABI stack pointer (`x2`), or
* the destination register and the first source register are identical, or
* the registers used are the 8 most popular ones.
The C extension is compatible with all other standard instruction
extensions. The C extension allows 16-bit instructions to be freely
intermixed with 32-bit instructions, with the latter now able to start
on any 16-bit boundary, i.e., IALIGN=16. With the addition of the C
extension, no instructions can raise instruction-address-misaligned
exceptions.
[NOTE]
====
Removing the 32-bit alignment constraint on the original 32-bit
instructions allows significantly greater code density.
====
The compressed instruction encodings are mostly common across RV32C,
RV64C, and RV128C, but as shown in <<rvc-instr-table0, Table 34>>, a few opcodes are used for
different purposes depending on base ISA. For example, the wider
address-space RV64C and RV128C variants require additional opcodes to
compress loads and stores of 64-bit integer values, while RV32C uses the
same opcodes to compress loads and stores of single-precision
floating-point values. Similarly, RV128C requires additional opcodes to
capture loads and stores of 128-bit integer values, while these same
opcodes are used for loads and stores of double-precision floating-point
values in RV32C and RV64C. If the C extension is implemented, the
appropriate compressed floating-point load and store instructions must
be provided whenever the relevant standard floating-point extension (F
and/or D) is also implemented. In addition, RV32C includes a compressed
jump and link instruction to compress short-range subroutine calls,
where the same opcode is used to compress ADDIW for RV64C and RV128C.
[TIP]
====
Double-precision loads and stores are a significant fraction of static
and dynamic instructions, hence the motivation to include them in the
RV32C and RV64C encoding.
Although single-precision loads and stores are not a significant source
of static or dynamic compression for benchmarks compiled for the
currently supported ABIs, for microcontrollers that only provide
hardware single-precision floating-point units and have an ABI that only
supports single-precision floating-point numbers, the single-precision
loads and stores will be used at least as frequently as double-precision
loads and stores in the measured benchmarks. Hence, the motivation to
provide compressed support for these in RV32C.
Short-range subroutine calls are more likely in small binaries for
microcontrollers, hence the motivation to include these in RV32C.
Although reusing opcodes for different purposes for different base ISAs
adds some complexity to documentation, the impact on implementation
complexity is small even for designs that support multiple base ISAs.
The compressed floating-point load and store variants use the same
instruction format with the same register specifiers as the wider
integer loads and stores.
====
RVC was designed under the constraint that each RVC instruction expands
into a single 32-bit instruction in either the base ISA (RV32I/E, RV64I/E,
or RV128I) or the F and D standard extensions where present. Adopting
this constraint has two main benefits:
* Hardware designs can simply expand RVC instructions during decode,
simplifying verification and minimizing modifications to existing
microarchitectures.
* Compilers can be unaware of the RVC extension and leave code compression
to the assembler and linker, although a compression-aware compiler will
generally be able to produce better results.
[NOTE]
====
We felt the multiple complexity reductions of a simple one-one mapping
between C and base IFD instructions far outweighed the potential gains
of a slightly denser encoding that added additional instructions only
supported in the C extension, or that allowed encoding of multiple IFD
instructions in one C instruction.
====
It is important to note that the C extension is not designed to be a
stand-alone ISA, and is meant to be used alongside a base ISA.
[TIP]
====
Variable-length instruction sets have long been used to improve code
density. For example, the IBM Stretch cite:[stretch], developed in the late 1950s, had
an ISA with 32-bit and 64-bit instructions, where some of the 32-bit
instructions were compressed versions of the full 64-bit instructions.
Stretch also employed the concept of limiting the set of registers that
were addressable in some of the shorter instruction formats, with short
branch instructions that could only refer to one of the index registers.
The later IBM 360 architecture cite:[ibm360] supported a simple variable-length
instruction encoding with 16-bit, 32-bit, or 48-bit instruction formats.
In 1963, CDC introduced the Cray-designed CDC 6600 cite:[cdc6600], a precursor to RISC
architectures, that introduced a register-rich load-store architecture
with instructions of two lengths, 15-bits and 30-bits. The later Cray-1
design used a very similar instruction format, with 16-bit and 32-bit
instruction lengths.
The initial RISC ISAs from the 1980s all picked performance over code
size, which was reasonable for a workstation environment, but not for
embedded systems. Hence, both ARM and MIPS subsequently made versions of
the ISAs that offered smaller code size by offering an alternative
16-bit wide instruction set instead of the standard 32-bit wide
instructions. The compressed RISC ISAs reduced code size relative to
their starting points by about 25-30%, yielding code that was
significantly smaller than 80x86. This result surprised some, as their
intuition was that the variable-length CISC ISA should be smaller than
RISC ISAs that offered only 16-bit and 32-bit formats.
Since the original RISC ISAs did not leave sufficient opcode space free
to include these unplanned compressed instructions, they were instead
developed as complete new ISAs. This meant compilers needed different
code generators for the separate compressed ISAs. The first compressed
RISC ISA extensions (e.g., ARM Thumb and MIPS16) used only a fixed
16-bit instruction size, which gave good reductions in static code size
but caused an increase in dynamic instruction count, which led to lower
performance compared to the original fixed-width 32-bit instruction
size. This led to the development of a second generation of compressed
RISC ISA designs with mixed 16-bit and 32-bit instruction lengths (e.g.,
ARM Thumb2, microMIPS, PowerPC VLE), so that performance was similar to
pure 32-bit instructions but with significant code size savings.
Unfortunately, these different generations of compressed ISAs are
incompatible with each other and with the original uncompressed ISA,
leading to significant complexity in documentation, implementations, and
software tools support.
Of the commonly used 64-bit ISAs, only PowerPC and microMIPS currently
supports a compressed instruction format. It is surprising that the most
popular 64-bit ISA for mobile platforms (ARM v8) does not include a
compressed instruction format given that static code size and dynamic
instruction fetch bandwidth are important metrics. Although static code
size is not a major concern in larger systems, instruction fetch
bandwidth can be a major bottleneck in servers running commercial
workloads, which often have a large instruction working set.
Benefiting from 25 years of hindsight, RISC-V was designed to support
compressed instructions from the outset, leaving enough opcode space for
RVC to be added as a simple extension on top of the base ISA (along with
many other extensions). The philosophy of RVC is to reduce code size for
embedded applications _and_ to improve performance and energy-efficiency
for all applications due to fewer misses in the instruction cache.
Waterman shows that RVC fetches 25%-30% fewer instruction bits, which
reduces instruction cache misses by 20%-25%, or roughly the same
performance impact as doubling the instruction cache size. cite:[waterman-ms]
====
=== Compressed Instruction Formats
((((compressed, formats))))
<<rvc-form>> shows the nine compressed instruction
formats. CR, CI, and CSS can use any of the 32 RVI registers, but CIW,
CL, CS, CA, and CB are limited to just 8 of them.
<<registers>> lists these popular registers, which
correspond to registers `x8` to `x15`. Note that there is a separate
version of load and store instructions that use the stack pointer as the
base address register, since saving to and restoring from the stack are
so prevalent, and that they use the CI and CSS formats to allow access
to all 32 data registers. CIW supplies an 8-bit immediate for the
ADDI4SPN instruction.
[NOTE]
====
The RISC-V ABI was changed to make the frequently used registers map to
registers 'x8-x15'. This simplifies the decompression decoder by
having a contiguous naturally aligned set of register numbers, and is
also compatible with the RV32E and RV64E base ISAs, which only have 16 integer
registers.
====
Compressed register-based floating-point loads and stores also use the
CL and CS formats respectively, with the eight registers mapping to `f8` to `f15`.
((((calling convention, standard))))
[NOTE]
====
_The standard RISC-V calling convention maps the most frequently used
floating-point registers to registers `f8` to `f15`, which allows the
same register decompression decoding as for integer register numbers._
====
((((register source spcifiers, c-ext))))
The formats were designed to keep bits for the two register source
specifiers in the same place in all instructions, while the destination
register field can move. When the full 5-bit destination register
specifier is present, it is in the same place as in the 32-bit RISC-V
encoding. Where immediates are sign-extended, the sign-extension is
always from bit 12. Immediate fields have been scrambled, as in the base
specification, to reduce the number of immediate muxes required.
[NOTE]
====
The immediate fields are scrambled in the instruction formats instead of
in sequential order so that as many bits as possible are in the same
position in every instruction, thereby simplifying implementations.
====
For many RVC instructions, zero-valued immediates are disallowed and
`x0` is not a valid 5-bit register specifier. These restrictions free up
encoding space for other instructions requiring fewer operand bits.
//[[cr-register]]
//include::images/wavedrom/cr-register.adoc[]
//.Compressed 16-bit RVC instructions
//(((compressed, 16-bit)))
[[rvc-form]]
.Compressed 16-bit RVC instruction formats
//[%header]
[float="center",align="center",cols="1a, 2a",frame="none",grid="none"]
|===
|
[%autowidth,float="right",align="right",cols="^,^",frame="none",grid="none",options="noheader"]
!===
!Format ! Meaning
!CR ! Register
!CI ! Immediate
!CSS ! Stack-relative Store
!CIW ! Wide Immediate
!CL ! Load
!CS ! Store
!CA ! Arithmetic
!CB ! Branch/Arithmetic
!CJ ! Jump
!===
|
[float="left",align="left",cols="1,1,1,1,1,1,1",options="noheader"]
!===
2+^!15 14 13 12 2+^!11 10 9 8 7 2+^!6 5 4 3 2 ^!1 0
2+^!funct4 2+^!rd/rs1 2+^!rs2 ^! op
^!funct3 ^!imm 2+^!rd/rs1 2+^!imm ^! op
^!funct3 3+^!imm 2+^!rs2 ^! op
^!funct3 4+^!imm ^!rd&#x2032; ^! op
^!funct3 2+^!imm ^!rs1&#x2032; ^!imm ^!rd&#x2032; ^! op
^!funct3 2+^!imm ^!rs1&#x2032; ^! imm ^!rs2&#x2032; ^! op
3+^!funct6 ^!rd&#x2032;/rs1&#x2032; ^!funct2 ^!rs2&#x2032; ^! op
^!funct3 2+^!offset ^!rd&#x2032;/rs1&#x2032; 2+^!offset ^! op
^!funct3 5+^!jump target ^! op
!===
|===
[[registers]]
.Registers specified by the three-bit _rs1_&#x2032;, _rs2_&#x2032;, and _rd_&#x2032; fields of the CIW, CL, CS, CA, and CB formats.
//[cols="20%,10%,10%,10%,10%,10%,10%,10%,10%"]
[float="center",align="center",cols="1a, 1a",frame="none",grid="none"]
|===
|
[%autowidth,cols="<",frame="none",grid="none",options="noheader"]
!===
!RVC Register Number
!Integer Register Number
!Integer Register ABI Name
!Floating-Point Register Number
!Floating-Point Register ABI Name
!===
|
[%autowidth,cols="^,^,^,^,^,^,^,^",options="noheader"]
!===
!`000` !`001` !`010` !`011` !`100` !`101` !`110` !`111`
!`x8` !`x9` !`x10` !`x11` !`x12` !`x13` !`x14`!`x15`
!`s0` !`s1` !`a0` !`a1` !`a2` !`a3` !`a4`!`a5`
!`f8` !`f9` !`f10` !`f11` !`f12` !`f13`!`f14` !`f15`
!`fs0` !`fs1` !`fa0` !`fa1` !`fa2`!`fa3` !`fa4` !`fa5`
!===
|===
=== Load and Store Instructions
To increase the reach of 16-bit instructions, data-transfer instructions
use zero-extended immediates that are scaled by the size of the data in
bytes: ×4 for words, ×8 for double
words, and ×16 for quad words.
RVC provides two variants of loads and stores. One uses the ABI stack
pointer, `x2`, as the base address and can target any data register. The
other can reference one of 8 base address registers and one of 8 data
registers.
==== Stack-Pointer-Based Loads and Stores
include::images/wavedrom/c-sp-load-store.adoc[]
[c-sp-load-store]
//.Stack-Pointer-Based Loads and Stores--these instructions use the CI format.
These instructions use the CI format.
C.LWSP loads a 32-bit value from memory into register _rd_. It computes
an effective address by adding the _zero_-extended offset, scaled by 4,
to the stack pointer, `x2`. It expands to `lw rd, offset(x2)`. C.LWSP is
only valid when _rd_&#x2260;x0 the code
points with _rd_=x0 are reserved.
C.LDSP is an RV64C/RV128C-only instruction that loads a 64-bit value
from memory into register _rd_. It computes its effective address by
adding the zero-extended offset, scaled by 8, to the stack pointer,
`x2`. It expands to `ld rd, offset(x2)`. C.LDSP is only valid when
_rd_&#x2260;x0 the code points with
_rd_=x0 are reserved.
C.LQSP is an RV128C-only instruction that loads a 128-bit value from
memory into register _rd_. It computes its effective address by adding
the zero-extended offset, scaled by 16, to the stack pointer, `x2`. It
expands to `lq rd, offset(x2)`. C.LQSP is only valid when
_rd_&#x2260;x0 the code points with
_rd_=x0 are reserved.
C.FLWSP is an RV32FC-only instruction that loads a single-precision
floating-point value from memory into floating-point register _rd_. It
computes its effective address by adding the _zero_-extended offset,
scaled by 4, to the stack pointer, `x2`. It expands to
`flw rd, offset(x2)`.
C.FLDSP is an RV32DC/RV64DC-only instruction that loads a
double-precision floating-point value from memory into floating-point
register _rd_. It computes its effective address by adding the
_zero_-extended offset, scaled by 8, to the stack pointer, `x2`. It
expands to `fld rd, offset(x2)`.
include::images/wavedrom/c-sp-load-store-css.adoc[]
[c-sp-load-store-css]
//.Stack-Pointer-Based Loads and Stores--these instructions use the CSS format.
These instructions use the CSS format.
C.SWSP stores a 32-bit value in register _rs2_ to memory. It computes an
effective address by adding the _zero_-extended offset, scaled by 4, to
the stack pointer, `x2`. It expands to `sw rs2, offset(x2)`.
C.SDSP is an RV64C/RV128C-only instruction that stores a 64-bit value in
register _rs2_ to memory. It computes an effective address by adding the
_zero_-extended offset, scaled by 8, to the stack pointer, `x2`. It
expands to `sd rs2, offset(x2)`.
C.SQSP is an RV128C-only instruction that stores a 128-bit value in
register _rs2_ to memory. It computes an effective address by adding the
_zero_-extended offset, scaled by 16, to the stack pointer, `x2`. It
expands to `sq rs2, offset(x2)`.
C.FSWSP is an RV32FC-only instruction that stores a single-precision
floating-point value in floating-point register _rs2_ to memory. It
computes an effective address by adding the _zero_-extended offset,
scaled by 4, to the stack pointer, `x2`. It expands to
`fsw rs2, offset(x2)`.
C.FSDSP is an RV32DC/RV64DC-only instruction that stores a
double-precision floating-point value in floating-point register _rs2_
to memory. It computes an effective address by adding the
_zero_-extended offset, scaled by 8, to the stack pointer, `x2`. It
expands to `fsd rs2, offset(x2)`.
[NOTE]
====
Register save/restore code at function entry/exit represents a
significant portion of static code size. The stack-pointer-based
compressed loads and stores in RVC are effective at reducing the
save/restore static code size by a factor of 2 while improving
performance by reducing dynamic instruction bandwidth.
A common mechanism used in other ISAs to further reduce save/restore
code size is load-multiple and store-multiple instructions. We
considered adopting these for RISC-V but noted the following drawbacks
to these instructions:
* These instructions complicate processor implementations.
* For virtual memory systems, some data accesses could be resident in
physical memory and some could not, which requires a new restart
mechanism for partially executed instructions.
* Unlike the rest of the RVC instructions, there is no IFD equivalent to
Load Multiple and Store Multiple.
* Unlike the rest of the RVC instructions, the compiler would have to be
aware of these instructions to both generate the instructions and to
allocate registers in an order to maximize the chances of the them being
saved and stored, since they would be saved and restored in sequential
order.
* Simple microarchitectural implementations will constrain how other
instructions can be scheduled around the load and store multiple
instructions, leading to a potential performance loss.
* The desire for sequential register allocation might conflict with the
featured registers selected for the CIW, CL, CS, CA, and CB formats.
Furthermore, much of the gains can be realized in software by replacing
prologue and epilogue code with subroutine calls to common prologue and
epilogue code, a technique described in Section 5.6 of cite:[waterman-phd].
While reasonable architects might come to different conclusions, we
decided to omit load and store multiple and instead use the
software-only approach of calling save/restore millicode routines to
attain the greatest code size reduction.
====
==== Register-Based Loads and Stores
[[reg-based-ldnstr]]
include::images/wavedrom/reg-based-ldnstr.adoc[]
//.Compressed, register-based load and stores--these instructions use the CL format.
(((compressed, register-based load and store)))
These instructions use the CL format.
C.LW loads a 32-bit value from memory into register
`_rd′_`. It computes an effective address by adding the
_zero_-extended offset, scaled by 4, to the base address in register
`_rs1′_`. It expands to `lw rd′, offset(rs1′)`.
C.LD is an RV64C/RV128C-only instruction that loads a 64-bit value from
memory into register `_rd′_`. It computes an effective
address by adding the _zero_-extended offset, scaled by 8, to the base
address in register `_rs1′_`. It expands to
`ld rd′, offset(rs1′)`.
C.LQ is an RV128C-only instruction that loads a 128-bit value from
memory into register `_rd′_`. It computes an effective
address by adding the _zero_-extended offset, scaled by 16, to the base
address in register `_rs1′_`. It expands to
`lq rd′, offset(rs1′)`.
C.FLW is an RV32FC-only instruction that loads a single-precision
floating-point value from memory into floating-point register
`_rd′_`. It computes an effective address by adding the
_zero_-extended offset, scaled by 4, to the base address in register
`_rs1′_`. It expands to
`flw rd′, offset(rs1′)`.
C.FLD is an RV32DC/RV64DC-only instruction that loads a double-precision
floating-point value from memory into floating-point register
`_rd′_`. It computes an effective address by adding the
_zero_-extended offset, scaled by 8, to the base address in register
`_rs1′_`. It expands to
`fld rd′, offset(rs1′)`.
[[c-cs-format-ls]]
include::images/wavedrom/c-cs-format-ls.adoc[]
//.Compressed, CS format load and store--these instructions use the CS format.
(((compressed, cs-format load and store)))
These instructions use the CS format.
C.SW stores a 32-bit value in register `_rs2′_` to memory.
It computes an effective address by adding the _zero_-extended offset,
scaled by 4, to the base address in register `_rs1′_`. It
expands to `sw rs2′, offset(rs1′)`.
C.SD is an RV64C/RV128C-only instruction that stores a 64-bit value in
register `_rs2′_` to memory. It computes an effective
address by adding the _zero_-extended offset, scaled by 8, to the base
address in register `_rs1′_`. It expands to
`sd rs2′, offset(rs1′)`.
C.SQ is an RV128C-only instruction that stores a 128-bit value in
register `_rs2′_` to memory. It computes an effective
address by adding the _zero_-extended offset, scaled by 16, to the base
address in register `_rs1′_`. It expands to
`sq rs2′, offset(rs1′)`.
C.FSW is an RV32FC-only instruction that stores a single-precision
floating-point value in floating-point register `_rs2′_` to
memory. It computes an effective address by adding the _zero_-extended
offset, scaled by 4, to the base address in register
`_rs1′_`. It expands to
`fsw rs2′, offset(rs1′)`.
C.FSD is an RV32DC/RV64DC-only instruction that stores a
double-precision floating-point value in floating-point register
`_rs2′_` to memory. It computes an effective address by
adding the _zero_-extended offset, scaled by 8, to the base address in
register `_rs1′_`. It expands to
`fsd rs2′, offset(rs1′)`.
=== Control Transfer Instructions
RVC provides unconditional jump instructions and conditional branch
instructions. As with base RVI instructions, the offsets of all RVC
control transfer instructions are in multiples of 2 bytes.
[[c-cj-format-ls]]
include::images/wavedrom/c-cj-format-ls.adoc[]
//.Compressed, CJ format load and store--these instructions use the CJ format.
(((compressed, cj-format load and store)))
These instructions use the CJ format.
C.J performs an unconditional control transfer. The offset is
sign-extended and added to the `pc` to form the jump target address. C.J
can therefore target a &#177;2 KiB range. C.J expands to
`jal x0, offset`.
C.JAL is an RV32C-only instruction that performs the same operation as
C.J, but additionally writes the address of the instruction following
the jump (`pc+2`) to the link register, `x1`. C.JAL expands to
`jal x1, offset`.
[[c-cr-format-ls]]
include::images/wavedrom/c-cr-format-ls.adoc[]
//.Compressed, CR format load and store--these instructions use the CR format.
(((compressed, cr-format load and store)))
These instructions use the CR format.
C.JR (jump register) performs an unconditional control transfer to the
address in register _rs1_. C.JR expands to `jalr x0, 0(rs1)`. C.JR is
only valid when latexmath:[$\textit{rs1}{\neq}\texttt{x0}$]; the code
point with latexmath:[$\textit{rs1}{=}\texttt{x0}$] is reserved.
C.JALR (jump and link register) performs the same operation as C.JR, but
additionally writes the address of the instruction following the jump
(`pc`+2) to the link register, `x1`. C.JALR expands to
`jalr x1, 0(rs1)`. C.JALR is only valid when
latexmath:[$\textit{rs1}{\neq}\texttt{x0}$]; the code point with
latexmath:[$\textit{rs1}{=}\texttt{x0}$] corresponds to the C.EBREAK
instruction.
[TIP]
====
Strictly speaking, C.JALR does not expand exactly to a base RVI
instruction as the value added to the PC to form the link address is 2
rather than 4 as in the base ISA, but supporting both offsets of 2 and 4
bytes is only a very minor change to the base microarchitecture.
====
[[c-cb-format-ls]]
include::images/wavedrom/c-cb-format-ls.adoc[]
//.Compressed, CB format load and store--these instructions use the CB format.
(((compressed, cb-format load and store)))
These instructions use the CB format.
C.BEQZ performs conditional control transfers. The offset is
sign-extended and added to the `pc` to form the branch target address.
It can therefore target a &#177;256 B range. C.BEQZ takes the
branch if the value in register _rs1′_ is zero. It
expands to `beq rs1′, x0, offset`.
C.BNEZ is defined analogously, but it takes the branch if
_rs1′_ contains a nonzero value. It expands to
`bne rs1′, x0, offset`.
=== Integer Computational Instructions
RVC provides several instructions for integer arithmetic and constant
generation.
==== Integer Constant-Generation Instructions
The two constant-generation instructions both use the CI instruction
format and can target any integer register.
[[c-integer-const-gen]]
include::images/wavedrom/c-integer-const-gen.adoc[]
//.Integer constant generation format.
(((compressed, integer constant generation)))
C.LI loads the sign-extended 6-bit immediate, _imm_, into register _rd_.
C.LI expands into `addi rd, x0, imm`. C.LI is only valid when
`_rd_≠x0`; the code points with `_rd_=x0` encode HINTs.
C.LUI loads the non-zero 6-bit immediate field into bits 17–12 of the
destination register, clears the bottom 12 bits, and sign-extends bit 17
into all higher bits of the destination. C.LUI expands into
`lui rd, imm`. C.LUI is only valid when
latexmath:[$\textit{rd}{\neq}{\left\{\texttt{x0},\texttt{x2}\right\}}$],
and when the immediate is not equal to zero. The code points with
_imm_=0 are reserved; the remaining code points with _rd_=`x0` are
HINTs; and the remaining code points with _rd_=`x2` correspond to the
C.ADDI16SP instruction.
==== Integer Register-Immediate Operations
These integer register-immediate operations are encoded in the CI format
and perform operations on an integer register and a 6-bit immediate.
[[c-integer-register-immediate]]
include::images/wavedrom/c-int-reg-immed.adoc[]
//.Integer register-immediate format.
(((compressed, integer register-immediate)))
C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in
register _rd_ then writes the result to _rd_. C.ADDI expands into
`addi rd, rd, imm`. C.ADDI is only valid when
`_rd_≠x0` and `_imm_≠0`. The code
points with `_rd_=x0` encode the C.NOP instruction; the remaining code
points with _imm_=0 encode HINTs.
C.ADDIW is an RV64C/RV128C-only instruction that performs the same
computation but produces a 32-bit result, then sign-extends result to 64
bits. C.ADDIW expands into `addiw rd, rd, imm`. The immediate can be
zero for C.ADDIW, where this corresponds to `sext.w rd`. C.ADDIW is
only valid when `_rd_≠x0`; the code points with
`_rd_=x0` are reserved.
C.ADDI16SP shares the opcode with C.LUI, but has a destination field of
`x2`. C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the
value in the stack pointer (`sp=x2`), where the immediate is scaled to
represent multiples of 16 in the range (-512,496). C.ADDI16SP is used to
adjust the stack pointer in procedure prologues and epilogues. It
expands into `addi x2, x2, nzimm[9:4]`. C.ADDI16SP is only valid when
_nzimm_≠0; the code point with _nzimm_=0 is reserved.
[NOTE]
====
In the standard RISC-V calling convention, the stack pointer `sp` is
always 16-byte aligned.
====
[[c-ciw]]
include::images/wavedrom/c-ciw.adoc[]
//.CIW format.
(((compressed, CIW)))
C.ADDI4SPN is a CIW-format instruction that adds a _zero_-extended
non-zero immediate, scaled by 4, to the stack pointer, `x2`, and writes
the result to `rd′`. This instruction is used to generate
pointers to stack-allocated variables, and expands to
`addi rd′, x2, nzuimm[9:2]`. C.ADDI4SPN is only valid when
_nzuimm_≠0; the code points with _nzuimm_=0 are
reserved.
[[c-ci]]
include::images/wavedrom/c-ci.adoc[]
//.CI format.
(((compressed, CI)))
C.SLLI is a CI-format instruction that performs a logical left shift of
the value in register _rd_ then writes the result to _rd_. The shift
amount is encoded in the _shamt_ field. For RV128C, a shift amount of
zero is used to encode a shift of 64. C.SLLI expands into
`slli rd, rd, shamt[5:0]`, except for RV128C with `shamt=0`, which expands to
`slli rd, rd, 64`.
For RV32C, _shamt[5]_ must be zero; the code points with _shamt[5]_=1
are designated for custom extensions. For RV32C and RV64C, the shift
amount must be non-zero; the code points with _shamt_=0 are HINTs. For
all base ISAs, the code points with `_rd_=x0` are HINTs, except those
with _shamt[5]_=1 in RV32C.
[[c-srli-srai]]
include::images/wavedrom/c-srli-srai.adoc[]
//.C-SRLI-SRAI format.
(((compressed, C.SRLI, C.SRAI)))
C.SRLI is a CB-format instruction that performs a logical right shift of
the value in register _rd′_ then writes the result to
_rd′_. The shift amount is encoded in the _shamt_ field.
For RV128C, a shift amount of zero is used to encode a shift of 64.
Furthermore, the shift amount is sign-extended for RV128C, and so the
legal shift amounts are 1-31, 64, and 96-127. C.SRLI expands into
`srli rd′, rd′, shamt`, except for
RV128C with `shamt=0`, which expands to
`srli rd′, rd′, 64`.
For RV32C, _shamt[5]_ must be zero; the code points with _shamt[5]_=1
are designated for custom extensions. For RV32C and RV64C, the shift
amount must be non-zero; the code points with _shamt_=0 are HINTs.
C.SRAI is defined analogously to C.SRLI, but instead performs an
arithmetic right shift. C.SRAI expands to
`srai rd′, rd′, shamt`.
[NOTE]
====
Left shifts are usually more frequent than right shifts, as left shifts
are frequently used to scale address values. Right shifts have therefore
been granted less encoding space and are placed in an encoding quadrant
where all other immediates are sign-extended. For RV128, the decision
was made to have the 6-bit shift-amount immediate also be sign-extended.
Apart from reducing the decode complexity, we believe right-shift
amounts of 96-127 will be more useful than 64-95, to allow extraction of
tags located in the high portions of 128-bit address pointers. We note
that RV128C will not be frozen at the same point as RV32C and RV64C, to
allow evaluation of typical usage of 128-bit address-space codes.
====
[[c-andi]]
include::images/wavedrom/c-andi.adoc[]
//.C.ANDI format
(((compressed, C.ANDI)))
C.ANDI is a CB-format instruction that computes the bitwise AND of the
value in register _rd′_ and the sign-extended 6-bit
immediate, then writes the result to _rd′_. C.ANDI
expands to `andi rd′, rd′, imm`.
==== Integer Register-Register Operations
[[c-cr]]
include::images/wavedrom/c-int-reg-to-reg-cr-format.adoc[]
//C.CR format
((((compressed. C.CR))))
These instructions use the CR format.
C.MV copies the value in register _rs2_ into register _rd_. C.MV expands
into `add rd, x0, rs2`. C.MV is only valid when
`rs2≠x0` the code points with `rs2=x0` correspond to the C.JR instruction. The code points with `rs2≠x0` and `rd=x0` are HINTs.
[TIP]
====
_C.MV expands to a different instruction than the canonical MV
pseudoinstruction, which instead uses ADDI. Implementations that handle
MV specially, e.g. using register-renaming hardware, may find it more
convenient to expand C.MV to MV instead of ADD, at slight additional
hardware cost._
====
C.ADD adds the values in registers _rd_ and _rs2_ and writes the result
to register _rd_. C.ADD expands into `add rd, rd, rs2`. C.ADD is only
valid when `rs2≠x0` the code points with `rs2=x0` correspond to the C.JALR
and C.EBREAK instructions. The code points with `rs2≠x0` and rd=x0 are HINTs.
[[c-ca]]
include::images/wavedrom/c-int-reg-to-reg-ca-format.adoc[]
//C.CA format
((((compressed. C.CA))))
These instructions use the CA format.
`C.AND` computes the bitwise `AND` of the values in registers
_rd′_ and _rs2′_, then writes the result
to register _rd′_. `C.AND` expands into
*`_and rd′, rd′, rs2′_`*.
`C.OR` computes the bitwise `OR` of the values in registers
_rd′_ and _rs2′_, then writes the result
to register _rd′_. `C.OR` expands into
*`_or rd&#8242;, rd&#8242;, rs2&#8242;_`*.
`C.XOR` computes the bitwise `XOR` of the values in registers
_rd′_ and _rs2′_, then writes the result
to register _rd′_. `C.XOR` expands into
*`_xor rd′, rd′, rs2′_`*.
`C.SUB` subtracts the value in register _rs2′_ from the
value in register _rd′_, then writes the result to
register _rd′_. `C.SUB` expands into
*`_sub rd′, rd′, rs2′_`*.
`C.ADDW` is an RV64C/RV128C-only instruction that adds the values in
registers _rd′_ and _rs2′_, then
sign-extends the lower 32 bits of the sum before writing the result to
register _rd′_. `C.ADDW` expands into
*`_addw rd′, rd′, rs2′_`*.
`C.SUBW` is an RV64C/RV128C-only instruction that subtracts the value in
register _rs2′_ from the value in register
_rd′_, then sign-extends the lower 32 bits of the
difference before writing the result to register _rd′_.
`C.SUBW` expands into *`_subw rd′, rd′, rs2′_`*.
[NOTE]
====
This group of six instructions do not provide large savings
individually, but do not occupy much encoding space and are
straightforward to implement, and as a group provide a worthwhile
improvement in static and dynamic compression.
====
==== Defined Illegal Instruction
[[c-def-illegal-inst]]
include::images/wavedrom/c-def-illegal-inst.adoc[]
((((compressed. C.DIINST))))
A 16-bit instruction with all bits zero is permanently reserved as an
illegal instruction.
[NOTE]
====
We reserve all-zero instructions to be illegal instructions to help trap
attempts to execute zero-ed or non-existent portions of the memory
space. The all-zero value should not be redefined in any non-standard
extension. Similarly, we reserve instructions with all bits set to 1
(corresponding to very long instructions in the RISC-V variable-length
encoding scheme) as illegal to capture another common value seen in
non-existent memory regions.
====
==== NOP Instruction
[[c-nop-instr]]
include::images/wavedrom/c-nop-instr.adoc[]
((((compressed. C.NOPINSTR))))
`C.NOP` is a CI-format instruction that does not change any user-visible
state, except for advancing the `pc` and incrementing any applicable
performance counters. `C.NOP` expands to `nop`. `C.NOP` is only valid when
_imm_=0; the code points with _imm_≠0 encode HINTs.
==== Breakpoint Instruction
[[c-breakpoint-instr]]
include::images/wavedrom/c-breakpoint-instr.adoc[]
((((compressed. C.BREAKPOINTINSTR))))
Debuggers can use the `C.EBREAK` instruction, which expands to `ebreak`,
to cause control to be transferred back to the debugging environment.
`C.EBREAK` shares the opcode with the `C.ADD` instruction, but with _rd_ and
_rs2_ both zero, thus can also use the `CR` format.
=== Usage of C Instructions in LR/SC Sequences
On implementations that support the C extension, compressed forms of the
I instructions permitted inside constrained LR/SC sequences, as
described in <<sec:lrscseq>>, are also permitted
inside constrained LR/SC sequences.
[NOTE]
====
The implication is that any implementation that claims to support both
the A and C extensions must ensure that LR/SC sequences containing valid
C instructions will eventually complete.
====
[[rvc-hints]]
=== HINT Instructions
A portion of the RVC encoding space is reserved for microarchitectural
HINTs. Like the HINTs in the RV32I base ISA (see
<<rv32i-hints>>), these instructions do not
modify any architectural state, except for advancing the `pc` and any
applicable performance counters. HINTs are executed as no-ops on
implementations that ignore them.
RVC HINTs are encoded as computational instructions that do not modify
the architectural state, either because _rd_=`x0` (e.g.
`C.ADD _x0_, _t0_`), or because _rd_ is overwritten with a copy of itself
(e.g. `C.ADDI _t0_, 0`).
[NOTE]
====
This HINT encoding has been chosen so that simple implementations can
ignore HINTs altogether, and instead execute a HINT as a regular
computational instruction that happens not to mutate the architectural
state.
====
RVC HINTs do not necessarily expand to their RVI HINT counterparts. For
example, `C.ADD` _x0_, _a0_ might not encode the same HINT as
`ADD` _x0_, _x0_, _a0_.
[NOTE]
====
The primary reason to not require an RVC HINT to expand to an RVI HINT
is that HINTs are unlikely to be compressible in the same manner as the
underlying computational instruction. Also, decoupling the RVC and RVI
HINT mappings allows the scarce RVC HINT space to be allocated to the
most popular HINTs, and in particular, to HINTs that are amenable to
macro-op fusion.
====
<<rvc-t-hints, Table 32>> lists all RVC HINT code points. For RV32C, 78%
of the HINT space is reserved for standard HINTs. The remainder of the HINT space is designated for custom HINTs;
no standard HINTs will ever be defined in this subspace.
[[rvc-t-hints]]
.RVC HINT instructions.
[cols="<,<,>,<",options="header",]
|===
|Instruction |Constraints |Code Points |Purpose
|C.NOP |_imm_≠0 |63 .6+.^|_Designated for future standard use_
|C.ADDI | _rd_≠`x0`, _imm_=0 |31
|C.LI | _rd_=`x0` |64
|C.LUI | _rd_=`x0`, _imm_≠0 |63
|C.MV | _rd_=`x0`, _rs2_≠`x0` |31
|C.ADD | _rd_=`x0`, _rs2_≠`x0`, _rs2_≠`x2-x5` | 27
|C.ADD | _rd_=`x0`, _rs2_≠`x2-x5` |4|(rs2=x2) C.NTL.P1 (rs2=x3) C.NTL.PALL (rs2=x4) C.NTL.S1 (rs2=x5) C.NTL.ALL
|C.SLLI |_rd_=`x0`, _imm_≠0 |31 (RV32), 63 (RV64/128) .5+.^|_Designated for custom use_
|C.SLLI64 | _rd_=_x0_ |1
|C.SLLI64 | _rd_≠`x0`, RV32 and RV64 only |31
|C.SRLI64 | RV32 and RV64 only |8
|C.SRAI64 | RV32 and RV64 only |8
|===
=== RVC Instruction Set Listings
<<rvcopcodemap>> shows a map of the major
opcodes for RVC. Each row of the table corresponds to one quadrant of
the encoding space. The last quadrant, which has the two
least-significant bits set, corresponds to instructions wider than 16
bits, including those in the base ISAs. Several instructions are only
valid for certain operands; when invalid, they are marked either _RES_
to indicate that the opcode is reserved for future standard extensions;
_Custom_ to indicate that the opcode is designated for custom
extensions; or _HINT_ to indicate that the opcode is reserved for
microarchitectural hints (see <<rvc-hints, Section 18.7>>).
<<<
[[rvcopcodemap]]
.RVC opcode map instructions.
[%autowidth,float="center",align="center",cols=">,^,^,^,^,^,^,^,^,^,<]
|===
2+>|inst[15:13] +
inst[1:0] ^.^s|000 ^.^s|001 ^.^s|010 ^.^s|011 ^.^s|100 ^.^s|101 ^.^s|110 ^.^s|111 |
2+>.^|00 .^|ADDI4SPN ^.^|FLD +
FLD +
LQ ^.^| LW ^.^| FLW +
LD +
LD ^.^| _Reserved_ ^.^| FSD +
FSD +
SQSW ^.^| SW ^.^| FSW +
SD +
SD
^.^| RV32 +
RV64 +
RV128
2+>.^|01 ^.^|ADDI ^.^|JAL +
ADDIW +
ADDIW ^.^|LI ^.^|LUI/ADDI16SP ^.^|MISC-ALU ^.^|J ^.^|BEQZ ^.^|BNEZ ^.^|RV32 +
RV64 +
RV128
2+>.^|10 ^.^|SLLI ^.^|FLDSP +
FLDSP +
LDSP ^.^|LWSP ^.^|FLWSP +
LDSP +
LDSP ^.^|J[AL]R/MV/ADD ^.^|FSDSP +
FSDSP +
SQSP ^.^|SWSP ^.^|FSWSP +
SDSP +
SDSP ^.^|RV32 +
RV6 +
RV128
2+>.^|11 9+^|>16b
|===
<<rvc-instr-table0>>, <<rvc-instr-table1>>, and <<rvc-instr-table2>> list the RVC instructions.
[[rvc-instr-table0]]
.Instruction listing for RVC, Quadrant 0
include::images/bytefield/rvc-instr-quad0.adoc[]
//include::images/bytefield/rvc-instr-quad0.png[]
[[rvc-instr-table1]]
.Instruction listing for RVC, Quadrant 1
include::images/bytefield/rvc-instr-quad1.adoc[]
//include::images/bytefield/rvc-instr-quad1.png[]
[[rvc-instr-table2]]
.Instruction listing for RVC, Quadrant 2
include::images/bytefield/rvc-instr-quad2.adoc[]
//include::images/bytefield/rvc-instr-quad2.png[]

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[colophon]
= Preface
This document describes the RISC-V unprivileged architecture.
The ISA modules marked *Ratified* have been ratified at this time. The
modules marked _Frozen_ are not expected to change significantly before
being put up for ratification. The modules marked _Draft_ are expected
to change before ratification.
The document contains the following versions of the RISC-V ISA modules:
[%autowidth,float="center",align="center",cols="^,<,^",options="header"]
|===
|Base |Version |Status
|*RVWMO* |*2.0* |*Ratified*
|*RV32I* |*2.1* |*Ratified*
|*RV64I* |*2.1* |*Ratified*
|*RV32E* |*2.0* |*Ratified*
|*RV64E* |*2.0* |*Ratified*
|_RV128I_ |_1.7_ |_Draft_
h|Extension h|Version h|Status
|*M* |*2.0* |*Ratified*
|*A* |*2.1* |*Ratified*
|*F* |*2.2* |*Ratified*
|*D* |*2.2* |*Ratified*
|*Q* |*2.2* |*Ratified*
|*C* |*2.0* |*Ratified*
|_Counters_ |*2.0* |*Ratified*
|_P_ |_0.2_ |_Draft_
|*V* |*1.0* |*Ratified*
|*Zicsr* |*2.0* |*Ratified*
|*Zifencei* |*2.0* |*Ratified*
|*Zihintpause* |*2.0* |*Ratified*
|*Zihintntl* |*1.0* |*Ratified*
|_Zam_ |_0.1_ |_Draft_
|*Zfa* |*1.0* |*Ratified*
|*Zfh* |*1.0* |*Ratified*
|*Zfhmin* |*1.0* |*Ratified*
|*Zfinx* |*1.0* |*Ratified*
|*Zdinx* |*1.0* |*Ratified*
|*Zhinx* |*1.0* |*Ratified*
|*Zhinxmin* |*1.0* |*Ratified*
|*Zmmul* |*1.0* |*Ratified*
|*Ztso* |*1.0* |*Ratified*
|===
[.big]*_Preface to Document Version 20191213-Base-Ratified_*
This document describes the RISC-V unprivileged architecture.
The ISA modules marked *Ratified* have been ratified at this time. The
modules marked _Frozen_ are not expected to change significantly before
being put up for ratification. The modules marked _Draft_ are expected
to change before ratification.
The document contains the following versions of the RISC-V ISA modules:
[%autowidth,float="center",align="center",cols="^,<,^",options="header",]
|===
|Base |Version |Status
|RVWMO |2.0 |*Ratified*
|*RV32I* |*2.1* |*Ratified*
|*RV64I* |*2.1* |*Ratified*
|_RV32E_ |_1.9_ |_Draft_
|_RV128I_ |_1.7_ |_Draft_
h|Extension h|Version h|Status
|*M* |*2.0* |*Ratified*
|*A* |*2.1* |*Ratified*
|*F* |*2.2* |*Ratified*
|*D* |*2.2* |*Ratified*
|*Q* |*2.2* |*Ratified*
|*C* |*2.0* |*Ratified*
|_Counters_ |_2.0_ |_Draft_
|_L_ |_0.0_ |_Draft_
|_B_ |_0.0_ |_Draft_
|_J_ |_0.0_ |_Draft_
|_T_ |_0.0_ |_Draft_
|_P_ |_0.2_ |_Draft_
|_V_ |_0.7_ |_Draft_
|*Zicsr* |*2.0* |*Ratified*
|*Zifencei* |*2.0* |*Ratified*
|_Zam_ |_0.1_ |_Draft_
|_Ztso_ |_0.1_ |_Frozen_
|===
The changes in this version of the document include:
* The A extension, now version 2.1, was ratified by the board in
December 2019.
* Defined big-endian ISA variant.
* Moved N extension for user-mode interrupts into Volume II.
* Defined PAUSE hint instruction.
[.big]*_Preface to Document Version 20190608-Base-Ratified_*
This document describes the RISC-V unprivileged architecture.
The RVWMO memory model has been ratified at this time. The ISA modules
marked *Ratified*, have been ratified at this time. The modules marked
_Frozen_ are not expected to change significantly before being put up
for ratification. The modules marked _Draft_ are expected to change
before ratification.
The document contains the following versions of the RISC-V ISA modules:
[%autowidth,float="center",align="center",cols="^,<,^",options="header",]
|===
|Base |Version |Status
|RVWMO |2.0 |*Ratified*
|*RV32I* |*2.1* |*Ratified*
|*RV64I* |*2.1* |*Ratified*
|_RV32E_ |_1.9_ |_Draft_
|_RV128I_ |_1.7_ |_Draft_
h|Extension h|Version h|Status
|*Zifencei* |*2.0* |*Ratified*
|*Zicsr* |*2.0* |*Ratified*
|*M* |*2.0* |*Ratified*
|_A_ |_2.0_ |Frozen
|*F* |*2.2* |*Ratified*
|*D* |*2.2* |*Ratified*
|*Q* |*2.2* |*Ratified*
|*C* |*2.0* |*Ratified*
|_Ztso_ |_0.1_ |_Frozen_
|_Counters_ |_2.0_ |_Draft_
|_L_ |_0.0_ |_Draft_
|_B_ |_0.0_ |_Draft_
|_J_ |_0.0_ |_Draft_
|_T_ |_0.0_ |_Draft_
|_P_ |_0.2_ |_Draft_
|_V_ |_0.7_ |_Draft_
|_N_ |_1.1_ |_Draft_
|_Zam_ |_0.1_ |_Draft_
|===
The changes in this version of the document include:
* Moved description to *Ratified* for the ISA modules ratified by the
board in early 2019.
* Removed the A extension from ratification.
* Changed document version scheme to avoid confusion with versions of
the ISA modules.
* Incremented the version numbers of the base integer ISA to 2.1,
reflecting the presence of the ratified RVWMO memory model and exclusion
of FENCE.I, counters, and CSR instructions that were in previous base
ISA.
* Incremented the version numbers of the F and D extensions to 2.2,
reflecting that version 2.1 changed the canonical NaN, and version 2.2
defined the NaN-boxing scheme and changed the definition of the FMIN and
FMAX instructions.
* Changed name of document to refer to "unprivileged" instructions as
part of move to separate ISA specifications from platform profile
mandates.
* Added clearer and more precise definitions of execution environments,
harts, traps, and memory accesses.
* Defined instruction-set categories: _standard_, _reserved_, _custom_,
_non-standard_, and _non-conforming_.
* Removed text implying operation under alternate endianness, as
alternate-endianness operation has not yet been defined for RISC-V.
* Changed description of misaligned load and store behavior. The
specification now allows visible misaligned address traps in execution
environment interfaces, rather than just mandating invisible handling of
misaligned loads and stores in user mode. Also, now allows access-fault
exceptions to be reported for misaligned accesses (including atomics)
that should not be emulated.
* Moved FENCE.I out of the mandatory base and into a separate extension,
with Zifencei ISA name. FENCE.I was removed from the Linux user ABI and
is problematic in implementations with large incoherent instruction and
data caches. However, it remains the only standard instruction-fetch
coherence mechanism.
* Removed prohibitions on using RV32E with other extensions.
* Removed platform-specific mandates that certain encodings produce
illegal-instruction exceptions in RV32E and RV64I chapters.
* Counter/timer instructions are now not considered part of the
mandatory base ISA, and so CSR instructions were moved into separate
chapter and marked as version 2.0, with the unprivileged counters moved
into another separate chapter. The counters are not ready for
ratification as there are outstanding issues, including counter
inaccuracies.
* A CSR-access ordering model has been added.
* Explicitly defined the 16-bit half-precision floating-point format for
floating-point instructions in the 2-bit _fmt field._
* Defined the signed-zero behavior of FMIN._fmt_ and FMAX._fmt_, and
changed their behavior on signaling-NaN inputs to conform to the
minimumNumber and maximumNumber operations in the proposed IEEE 754-201x
specification.
* The memory consistency model, RVWMO, has been defined.
* The "Zam" extension, which permits misaligne%autowidth,float="center",align="center",d AMOs and specifies
their semantics, has been defined.
* The "Ztso" extension, which enforces a stricter memory consistency
model than RVWMO, has been defined.
* Improvements to the description and commentary.
* Defined the term `IALIGN` as shorthand to describe the
instruction-address alignment constraint.
* Removed text of `P` extension chapter as now superseded by active task
group documents.
* Removed text of `V` extension chapter as now superseded by separate
vector extension draft document.
[.big]*_Preface to Document Version 2.2_*
This is version 2.2 of the document describing the RISC-V user-level
architecture. The document contains the following versions of the RISC-V
ISA modules:
[%autowidth,float="center",align="center",cols="^,<,^",options="header",]
|===
h|Base h|_Version_ h|_Draft Frozen?_
|RV32I |2.0 |Y
|RV32E |1.9 |N
|RV64I |2.0 |Y
|RV128I |1.7 |N
h|Extension h|Version h|Frozen?
|M |2.0 |Y
|A |2.0 |Y
|F |2.0 |Y
|D |2.0 |Y
|Q |2.0 |Y
|L |0.0 |N
|C |2.0 |Y
|B |0.0 |N
|J |0.0 |N
|T |0.0 |N
|P |0.1 |N
|V |0.7 |N
|N |1.1 |N
|===
To date, no parts of the standard have been officially ratified by the
RISC-V Foundation, but the components labeled "frozen" above are not
expected to change during the ratification process beyond resolving
ambiguities and holes in the specification.
The major changes in this version of the document include:
* The previous version of this document was released under a Creative
Commons Attribution 4.0 International License by the original authors,
and this and future versions of this document will be released under the
same license.
* Rearranged chapters to put all extensions first in canonical order.
* Improvements to the description and commentary.
* Modified implicit hinting suggestion on `JALR` to support more efficient
macro-op fusion of `LUI/JALR` and `AUIPC/JALR` pairs.
* Clarification of constraints on load-reserved/store-conditional
sequences.
* A new table of control and status register (CSR) mappings.
* Clarified purpose and behavior of high-order bits of `fcsr`.
* Corrected the description of the `FNMADD`._fmt_ and `FNMSUB`._fmt_
instructions, which had suggested the incorrect sign of a zero result.
* Instructions `FMV.S.X` and `FMV.X.S` were renamed to `FMV.W.X` and `FMV.X.W`
respectively to be more consistent with their semantics, which did not
change. The old names will continue to be supported in the tools.
* Specified behavior of narrower (latexmath:[$<$]FLEN) floating-point
values held in wider `f` registers using NaN-boxing model.
* Defined the exception behavior of FMA(latexmath:[$\infty$], 0, qNaN).
* Added note indicating that the `P` extension might be reworked into an
integer packed-SIMD proposal for fixed-point operations using the
integer registers.
* A draft proposal of the V vector instruction-set extension.
* An early draft proposal of the N user-level traps extension.
* An expanded pseudoinstruction listing.
* Removal of the calling convention chapter, which has been superseded
by the RISC-V ELF psABI Specification cite:[riscv-elf-psabi].
* The C extension has been frozen and renumbered version 2.0.
[.big]*_Preface to Document Version 2.1_*
This is version 2.1 of the document describing the RISC-V user-level
architecture. Note the frozen user-level ISA base and extensions `IMAFDQ`
version 2.0 have not changed from the previous version of this
document cite:[riscvtr2], but some specification holes have been fixed and the
documentation has been improved. Some changes have been made to the
software conventions.
* Numerous additions and improvements to the commentary sections.
* Separate version numbers for each chapter.
* Modification to long instruction encodings latexmath:[$>$]64 bits to
avoid moving the _rd_ specifier in very long instruction formats.
* CSR instructions are now described in the base integer format where
the counter registers are introduced, as opposed to only being
introduced later in the floating-point section (and the companion
privileged architecture manual).
* The SCALL and SBREAK instructions have been renamed to `ECALL` and
`EBREAK`, respectively. Their encoding and functionality are unchanged.
* Clarification of floating-point NaN handling, and a new canonical NaN
value.
* Clarification of values returned by floating-point to integer
conversions that overflow.
* Clarification of `LR/SC` allowed successes and required failures,
including use of compressed instructions in the sequence.
* A new `RV32E` base ISA proposal for reduced integer register counts,
supports `MAC` extensions.
* A revised calling convention.
* Relaxed stack alignment for soft-float calling convention, and
description of the RV32E calling convention.
* A revised proposal for the `C` compressed extension, version 1.9 .
[.big]*_Preface to Version 2.0_*
This is the second release of the user ISA specification, and we intend
the specification of the base user ISA plus general extensions (i.e.,
IMAFD) to remain fixed for future development. The following changes
have been made since Version 1.0 cite:[riscvtr] of this ISA specification.
* The ISA has been divided into an integer base with several standard
extensions.
* The instruction formats have been rearranged to make immediate
encoding more efficient.
* The base ISA has been defined to have a little-endian memory system,
with big-endian or bi-endian as non-standard variants.
* Load-Reserved/Store-Conditional (`LR/SC`) instructions have been added
in the atomic instruction extension.
* `AMOs` and `LR/SC` can support the release consistency model.
* The `FENCE` instruction provides finer-grain memory and I/O orderings.
* An `AMO` for fetch-and-`XOR` (`AMOXOR`) has been added, and the encoding for
`AMOSWAP` has been changed to make room.
* The `AUIPC` instruction, which adds a 20-bit upper immediate to the `PC`,
replaces the `RDNPC` instruction, which only read the current `PC` value.
This results in significant savings for position-independent code.
* The `JAL` instruction has now moved to the `U-Type` format with an
explicit destination register, and the `J` instruction has been dropped
being replaced by `JAL` with _rd_=`x0`. This removes the only instruction
with an implicit destination register and removes the `J-Type` instruction
format from the base ISA. There is an accompanying reduction in `JAL`
reach, but a significant reduction in base ISA complexity.
* The static hints on the `JALR` instruction have been dropped. The hints
are redundant with the _rd_ and _rs1_ register specifiers for code
compliant with the standard calling convention.
* The `JALR` instruction now clears the lowest bit of the calculated
target address, to simplify hardware and to allow auxiliary information
to be stored in function pointers.
* The `MFTX.S` and `MFTX.D` instructions have been renamed to `FMV.X.S` and
`FMV.X.D`, respectively. Similarly, `MXTF.S` and `MXTF.D` instructions have
been renamed to `FMV.S.X` and `FMV.D.X`, respectively.
* The `MFFSR` and `MTFSR` instructions have been renamed to `FRCSR` and `FSCSR`,
respectively. `FRRM`, `FSRM`, `FRFLAGS`, and `FSFLAGS` instructions have been
added to individually access the rounding mode and exception flags
subfields of the `fcsr`.
* The `FMV.X.S` and `FMV.X.D` instructions now source their operands from
_rs1_, instead of _rs2_. This change simplifies datapath design.
* `FCLASS.S` and `FCLASS.D` floating-point classify instructions have been
added.
* A simpler NaN generation and propagation scheme has been adopted.
* For `RV32I`, the system performance counters have been extended to
64-bits wide, with separate read access to the upper and lower 32 bits.
* Canonical `NOP` and `MV` encodings have been defined.
* Standard instruction-length encodings have been defined for 48-bit,
64-bit, and latexmath:[$>$]64-bit instructions.
* Description of a 128-bit address space variant, `RV128`, has been added.
* Major opcodes in the 32-bit base instruction format have been
allocated for user-defined custom extensions.
* A typographical error that suggested that stores source their data
from _rd_ has been corrected to refer to _rs2_.

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== Counters
RISC-V ISAs provide a set of up to 32latexmath:[$\times$]64-bit
performance counters and timers that are accessible via unprivileged
XLEN read-only CSR registers `0xC00`–`0xC1F` (with the upper 32 bits
accessed via CSR registers `0xC80`–`0xC9F` on RV32). The first three of
these (CYCLE, TIME, and INSTRET) have dedicated functions (cycle count,
real-time clock, and instructions-retired respectively), while the
remaining counters, if implemented, provide programmable event counting.
=== Base Counters and Timers
M@R@F@R@S +
& & & & +
& & & & +
& 5 & 3 & 5 & 7 +
RDCYCLE[H] & 0 & CSRRS & dest & SYSTEM +
RDTIME[H] & 0 & CSRRS & dest & SYSTEM +
RDINSTRET[H] & 0 & CSRRS & dest & SYSTEM +
RV32I provides a number of 64-bit read-only user-level counters, which
are mapped into the 12-bit CSR address space and accessed in 32-bit
pieces using CSRRS instructions. In RV64I, the CSR instructions can
manipulate 64-bit CSRs. In particular, the RDCYCLE, RDTIME, and
RDINSTRET pseudoinstructions read the full 64 bits of the `cycle`,
`time`, and `instret` counters. Hence, the RDCYCLEH, RDTIMEH, and
RDINSTRETH instructions are RV32I-only.
Some execution environments might prohibit access to counters to impede
timing side-channel attacks.
The RDCYCLE pseudoinstruction reads the low XLEN bits of the ` cycle`
CSR which holds a count of the number of clock cycles executed by the
processor core on which the hart is running from an arbitrary start time
in the past. RDCYCLEH is an RV32I-only instruction that reads bits 63–32
of the same cycle counter. The underlying 64-bit counter should never
overflow in practice. The rate at which the cycle counter advances will
depend on the implementation and operating environment. The execution
environment should provide a means to determine the current rate
(cycles/second) at which the cycle counter is incrementing.
RDCYCLE is intended to return the number of cycles executed by the
processor core, not the hart. Precisely defining what is a ``core'' is
difficult given some implementation choices (e.g., AMD Bulldozer).
Precisely defining what is a ``clock cycle'' is also difficult given the
range of implementations (including software emulations), but the intent
is that RDCYCLE is used for performance monitoring along with the other
performance counters. In particular, where there is one hart/core, one
would expect cycle-count/instructions-retired to measure CPI for a hart.
Cores don’t have to be exposed to software at all, and an implementor
might choose to pretend multiple harts on one physical core are running
on separate cores with one hart/core, and provide separate cycle
counters for each hart. This might make sense in a simple barrel
processor (e.g., CDC 6600 peripheral processors) where inter-hart timing
interactions are non-existent or minimal.
Where there is more than one hart/core and dynamic multithreading, it is
not generally possible to separate out cycles per hart (especially with
SMT). It might be possible to define a separate performance counter that
tried to capture the number of cycles a particular hart was running, but
this definition would have to be very fuzzy to cover all the possible
threading implementations. For example, should we only count cycles for
which any instruction was issued to execution for this hart, and/or
cycles any instruction retired, or include cycles this hart was
occupying machine resources but couldn’t execute due to stalls while
other harts went into execution? Likely, ``all of the above'' would be
needed to have understandable performance stats. This complexity of
defining a per-hart cycle count, and also the need in any case for a
total per-core cycle count when tuning multithreaded code led to just
standardizing the per-core cycle counter, which also happens to work
well for the common single hart/core case.
Standardizing what happens during ``sleep'' is not practical given that
what ``sleep'' means is not standardized across execution environments,
but if the entire core is paused (entirely clock-gated or powered-down
in deep sleep), then it is not executing clock cycles, and the cycle
count shouldn’t be increasing per the spec. There are many details,
e.g., whether clock cycles required to reset a processor after waking up
from a power-down event should be counted, and these are considered
execution-environment-specific details.
Even though there is no precise definition that works for all platforms,
this is still a useful facility for most platforms, and an imprecise,
common, ``usually correct'' standard here is better than no standard.
The intent of RDCYCLE was primarily performance monitoring/tuning, and
the specification was written with that goal in mind.
The RDTIME pseudoinstruction reads the low XLEN bits of the ` time` CSR,
which counts wall-clock real time that has passed from an arbitrary
start time in the past. RDTIMEH is an RV32I-only instruction that reads
bits 63–32 of the same real-time counter. The underlying 64-bit counter
should never overflow in practice. The execution environment should
provide a means of determining the period of the real-time counter
(seconds/tick). The period must be constant. The real-time clocks of all
harts in a single user application should be synchronized to within one
tick of the real-time clock. The environment should provide a means to
determine the accuracy of the clock.
On some simple platforms, cycle count might represent a valid
implementation of RDTIME, but in this case, platforms should implement
the RDTIME instruction as an alias for RDCYCLE to make code more
portable, rather than using RDCYCLE to measure wall-clock time.
The RDINSTRET pseudoinstruction reads the low XLEN bits of the
` instret` CSR, which counts the number of instructions retired by this
hart from some arbitrary start point in the past. RDINSTRETH is an
RV32I-only instruction that reads bits 63–32 of the same instruction
counter. The underlying 64-bit counter should never overflow in
practice.
The following code sequence will read a valid 64-bit cycle counter value
into `x3`:`x2`, even if the counter overflows its lower half between
reading its upper and lower halves.
....
again:
rdcycleh x3
rdcycle x2
rdcycleh x4
bne x3, x4, again
....
We recommend provision of these basic counters in implementations as
they are essential for basic performance analysis, adaptive and dynamic
optimization, and to allow an application to work with real-time
streams. Additional counters should be provided to help diagnose
performance problems and these should be made accessible from user-level
application code with low overhead.
We required the counters be 64 bits wide, even on RV32, as otherwise it
is very difficult for software to determine if values have overflowed.
For a low-end implementation, the upper 32 bits of each counter can be
implemented using software counters incremented by a trap handler
triggered by overflow of the lower 32 bits. The sample code described
above shows how the full 64-bit width value can be safely read using the
individual 32-bit instructions.
In some applications, it is important to be able to read multiple
counters at the same instant in time. When run under a multitasking
environment, a user thread can suffer a context switch while attempting
to read the counters. One solution is for the user thread to read the
real-time counter before and after reading the other counters to
determine if a context switch occurred in the middle of the sequence, in
which case the reads can be retried. We considered adding output latches
to allow a user thread to snapshot the counter values atomically, but
this would increase the size of the user context, especially for
implementations with a richer set of counters.
=== Hardware Performance Counters
There is CSR space allocated for 29 additional unprivileged 64-bit
hardware performance counters, `hpmcounter3`–`hpmcounter31`. For RV32,
the upper 32 bits of these performance counters is accessible via
additional CSRs `hpmcounter3h`–` hpmcounter31h`. These counters count
platform-specific events and are configured via additional privileged
registers. The number and width of these additional counters, and the
set of events they count is platform-specific.
The privileged architecture manual describes the privileged CSRs
controlling access to these counters and to set the events to be
counted.
It would be useful to eventually standardize event settings to count
ISA-level metrics, such as the number of floating-point instructions
executed for example, and possibly a few common microarchitectural
metrics, such as ``L1 instruction cache misses''.

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[[counters]]
== "Zicntr" and "Zihpm" Counters, Version 2.0
RISC-V ISAs provide a set of up to thirty-two 64-bit performance
counters and timers that are accessible via unprivileged XLEN-bit
read-only CSR registers `0xC00`–`0xC1F` (when XLEN=32, the upper 32 bits
are accessed via CSR registers `0xC80`–`0xC9F`). These counters are
divided between the "Zicntr" and "Zihpm" extensions.
=== "Zicntr" Standard Extension for Base Counters and Timers
The Zicntr standard extension comprises the first three of these
counters (CYCLE, TIME, and INSTRET), which have dedicated functions
(cycle count, real-time clock, and instructions retired, respectively).
The Zicntr extension depends on the Zicsr extension.
[TIP]
====
We recommend provision of these basic counters in implementations as
they are essential for basic performance analysis, adaptive and dynamic
optimization, and to allow an application to work with real-time
streams. Additional counters in the separate Zihpm extension can help
diagnose performance problems and these should be made accessible from
user-level application code with low overhead.
Some execution environments might prohibit access to counters, for
example, to impede timing side-channel attacks.
====
include::images/wavedrom/counters-diag.adoc[]
For base ISAs with XLEN&#8805;64, CSR instructions can access
the full 64-bit CSRs directly. In particular, the RDCYCLE, RDTIME, and
RDINSTRET pseudoinstructions read the full 64 bits of the `cycle`,
`time`, and `instret` counters.
[TIP]
====
The counter pseudoinstructions are mapped to the read-only
`csrrs rd, counter, x0` canonical form, but the other read-only CSR
instruction forms (based on CSRRC/CSRRSI/CSRRCI) are also legal ways to
read these CSRs.
====
For base ISAs with XLEN=32, the Zicntr extension enables the three
64-bit read-only counters to be accessed in 32-bit pieces. The RDCYCLE,
RDTIME, and RDINSTRET pseudoinstructions provide the lower 32 bits, and
the RDCYCLEH, RDTIMEH, and RDINSTRETH pseudoinstructions provide the
upper 32 bits of the respective counters.
[TIP]
====
We required the counters be 64 bits wide, even when XLEN=32, as
otherwise it is very difficult for software to determine if values have
overflowed. For a low-end implementation, the upper 32 bits of each
counter can be implemented using software counters incremented by a trap
handler triggered by overflow of the lower 32 bits. The sample code
given below shows how the full 64-bit width value can be safely read
using the individual 32-bit width pseudoinstructions.
====
The RDCYCLE pseudoinstruction reads the low XLEN bits of the `cycle`
CSR which holds a count of the number of clock cycles executed by the
processor core on which the hart is running from an arbitrary start time
in the past. RDCYCLEH is only present when XLEN=32 and reads bits 63-32
of the same cycle counter. The underlying 64-bit counter should never
overflow in practice. The rate at which the cycle counter advances will
depend on the implementation and operating environment. The execution
environment should provide a means to determine the current rate
(cycles/second) at which the cycle counter is incrementing.
[TIP]
====
RDCYCLE is intended to return the number of cycles executed by the
processor core, not the hart. Precisely defining what is a "core" is
difficult given some implementation choices (e.g., AMD Bulldozer).
Precisely defining what is a "clock cycle" is also difficult given the
range of implementations (including software emulations), but the intent
is that RDCYCLE is used for performance monitoring along with the other
performance counters. In particular, where there is one hart/core, one
would expect cycle-count/instructions-retired to measure CPI for a hart.
Cores don't have to be exposed to software at all, and an implementor
might choose to pretend multiple harts on one physical core are running
on separate cores with one hart/core, and provide separate cycle
counters for each hart. This might make sense in a simple barrel
processor (e.g., CDC 6600 peripheral processors) where inter-hart timing
interactions are non-existent or minimal.
Where there is more than one hart/core and dynamic multithreading, it is
not generally possible to separate out cycles per hart (especially with
SMT). It might be possible to define a separate performance counter that
tried to capture the number of cycles a particular hart was running, but
this definition would have to be very fuzzy to cover all the possible
threading implementations. For example, should we only count cycles for
which any instruction was issued to execution for this hart, and/or
cycles any instruction retired, or include cycles this hart was
occupying machine resources but couldn't execute due to stalls while
other harts went into execution? Likely, "all of the above" would be
needed to have understandable performance stats. This complexity of
defining a per-hart cycle count, and also the need in any case for a
total per-core cycle count when tuning multithreaded code led to just
standardizing the per-core cycle counter, which also happens to work
well for the common single hart/core case.
Standardizing what happens during "sleep" is not practical given that
what "sleep" means is not standardized across execution environments,
but if the entire core is paused (entirely clock-gated or powered-down
in deep sleep), then it is not executing clock cycles, and the cycle
count shouldn't be increasing per the spec. There are many details,
e.g., whether clock cycles required to reset a processor after waking up
from a power-down event should be counted, and these are considered
execution-environment-specific details.
Even though there is no precise definition that works for all platforms,
this is still a useful facility for most platforms, and an imprecise,
common, "usually correct" standard here is better than no standard.
The intent of RDCYCLE was primarily performance monitoring/tuning, and
the specification was written with that goal in mind.
====
The RDTIME pseudoinstruction reads the low XLEN bits of the "time" CSR,
which counts wall-clock real time that has passed from an arbitrary
start time in the past. RDTIMEH is only present when XLEN=32 and reads
bits 63-32 of the same real-time counter. The underlying 64-bit counter
increments by one with each tick of the real-time clock, and, for
realistic real-time clock frequencies, should never overflow in
practice. The execution environment should provide a means of
determining the period of a counter tick (seconds/tick). The period
should be constant within a small error bound. The environment should
provide a means to determine the accuracy of the clock (i.e., the
maximum relative error between the nominal and actual real-time clock
periods).
[TIP]
====
On some simple platforms, cycle count might represent a valid
implementation of RDTIME, in which case RDTIME and RDCYCLE may return
the same result.
It is difficult to provide a strict mandate on clock period given the
wide variety of possible implementation platforms. The maximum error
bound should be set based on the requirements of the platform.
====
The real-time clocks of all harts must be synchronized to within one
tick of the real-time clock.
[TIP]
====
As with other architectural mandates, it suffices to appear "as if"
harts are synchronized to within one tick of the real-time clock, i.e.,
software is unable to observe that there is a greater delta between the
real-time clock values observed on two harts.
====
The RDINSTRET pseudoinstruction reads the low XLEN bits of the
`instret` CSR, which counts the number of instructions retired by this
hart from some arbitrary start point in the past. RDINSTRETH is only
present when XLEN=32 and reads bits 63-32 of the same instruction
counter. The underlying 64-bit counter should never overflow in
practice.
[TIP]
====
Instructions that cause synchronous exceptions, including ECALL and
EBREAK, are not considered to retire and hence do not increment the
`instret` CSR.
====
The following code sequence will read a valid 64-bit cycle counter value
into `x3:x2`, even if the counter overflows its lower half between
reading its upper and lower halves.
[source,asm.]
.Sample code for reading the 64-bit cycle counter when XLEN=32.
again:
rdcycleh x3
rdcycle x2
rdcycleh x4
bne x3, x4, again
=== "Zihpm" Standard Extension for Hardware Performance Counters
The Zihpm extension comprises up to 29 additional unprivileged 64-bit
hardware performance counters, `hpmcounter3-hpmcounter31`. When
XLEN=32, the upper 32 bits of these performance counters are accessible
via additional CSRs `hpmcounter3h- hpmcounter31h`. The Zihpm extension
depends on the Zicsr extension.
[TIP]
====
In some applications, it is important to be able to read multiple
counters at the same instant in time. When run under a multitasking
environment, a user thread can suffer a context switch while attempting
to read the counters. One solution is for the user thread to read the
real-time counter before and after reading the other counters to
determine if a context switch occurred in the middle of the sequence, in
which case the reads can be retried. We considered adding output latches
to allow a user thread to snapshot the counter values atomically, but
this would increase the size of the user context, especially for
implementations with a richer set of counters.
====
The implemented number and width of these additional counters, and the
set of events they count, is platform-specific. Accessing an
unimplemented or ill-configured counter may cause an illegal-instruction
exception or may return a constant value.
The execution environment should provide a means to determine the number
and width of the implemented counters, and an interface to configure the
events to be counted by each counter.
[TIP]
====
For execution environments implemented on RISC-V privileged platforms,
the privileged architecture manual describes privileged CSRs controlling
access by lower privileged modes to these counters, and to set the
events to be counted.
Alternative execution environments (e.g., user-level-only software
performance models) may provide alternative mechanisms to configure the
events counted by the performance counters.
It would be useful to eventually standardize event settings to count
ISA-level metrics, such as the number of floating-point instructions
executed for example, and possibly a few common microarchitectural
metrics, such as "L1 instruction cache misses".
====

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== "D" Standard Extension for Double-Precision Floating-Point, Version 2.2
This chapter describes the standard double-precision floating-point
instruction-set extension, which is named "D" and adds
double-precision floating-point computational instructions compliant
with the IEEE 754-2008 arithmetic standard. The D extension depends on
the base single-precision instruction subset F.
(((double-precision, floating point)))
(((floating point, double precision)))
=== D Register State
The D extension widens the 32 floating-point registers, `f0-f31`, to
64 bits (FLEN=64 in <<fprs>>. The `f` registers can
now hold either 32-bit or 64-bit floating-point values as described
below in <<nanboxing>>.
[NOTE]
====
FLEN can be 32, 64, or 128 depending on which of the F, D, and Q
extensions are supported. There can be up to four different
floating-point precisions supported, including H, F, D, and Q.
====
(((floating-point, supported precisions)))
[[nanboxing]]
=== NaN Boxing of Narrower Values
When multiple floating-point precisions are supported, then valid values
of narrower _n_-bit types, _n<_FLEN, are represented in the lower _n_ bits of an FLEN-bit NaN value, in a process termed NaN-boxing. The upper bits of a valid NaN-boxed value must be all 1s. Valid NaN-boxed _n_-bit values
therefore appear as negative quiet NaNs (qNaNs) when viewed as any wider
_m_-bit value, _n_ < _m_ &#8804; FLEN. Any operation that writes a narrower result to an 'f' register must write all 1s to the uppermost FLEN-_n_ bits to yield a legal NaN-boxedvalue.
(((floating-point, requirements)))
[NOTE]
====
Software might not know the current type of data stored in a
floating-point register but has to be able to save and restore the
register values, hence the result of using wider operations to transfer
narrower values has to be defined. A common case is for callee-saved
registers, but a standard convention is also desirable for features
including varargs, user-level threading libraries, virtual machine
migration, and debugging.
====
Floating-point _n_-bit transfer operations move external
values held in IEEE standard formats into and out of the `f` registers,
and comprise floating-point loads and stores (FL_n_/FS_n_) and floating-point move instructions (FMV._n_.X/FMV.X._n_). A narrower _n_-bit transfer, _n_<FLEN, into the `f` registers will create a valid NaN-boxed value. A narrower
_n_-bit transfer out of the floating-point registers will
transfer the lower _n_ bits of the register ignoring the
upper FLEN-_n_ bits.
Apart from transfer operations described in the previous paragraph, all
other floating-point operations on narrower latexmath:[$n$]-bit
operations, _n_<FLEN, check if the input operands are
correctly NaN-boxed, i.e., all upper FLEN-_n_ bits are 1. If
so, the _n_ least-significant bits of the input are used as
the input value, otherwise the input value is treated as an
_n_-bit canonical NaN.
[TIP]
====
Earlier versions of this document did not define the behavior of feeding
the results of narrower or wider operands into an operation, except to
require that wider saves and restores would preserve the value of a
narrower operand. The new definition removes this
implementation-specific behavior, while still accommodating both
non-recoded and recoded implementations of the floating-point unit. The
new definition also helps catch software errors by propagating NaNs if
values are used incorrectly.
Non-recoded implementations unpack and pack the operands to IEEE
standard format on the input and output of every floating-point
operation. The NaN-boxing cost to a non-recoded implementation is
primarily in checking if the upper bits of a narrower operation
represent a legal NaN-boxed value, and in writing all 1s to the upper
bits of a result.
Recoded implementations use a more convenient internal format to
represent floating-point values, with an added exponent bit to allow all
values to be held normalized. The cost to the recoded implementation is
primarily the extra tagging needed to track the internal types and sign
bits, but this can be done without adding new state bits by recoding
NaNs internally in the exponent field. Small modifications are needed to
the pipelines used to transfer values in and out of the recoded format,
but the datapath and latency costs are minimal. The recoding process has
to handle shifting of input subnormal values for wide operands in any
case, and extracting the NaN-boxed value is a similar process to
normalization except for skipping over leading-1 bits instead of
skipping over leading-0 bits, allowing the datapath muxing to be shared.
====
[[fld_fsd]]
=== Double-Precision Load and Store Instructions
The FLD instruction loads a double-precision floating-point value from
memory into floating-point register _rd_. FSD stores a double-precision
value from the floating-point registers to memory.
(((floating point, load and store)))
[NOTE]
====
The double-precision value may be a NaN-boxed single-precision value.
====
include::images/wavedrom/double-ls.adoc[]
[[double-ls]]
//.Double-precision load and store
FLD and FSD are only guaranteed to execute atomically if the effective
address is naturally aligned and XLEN&#8805;64.
FLD and FSD do not modify the bits being transferred; in particular, the
payloads of non-canonical NaNs are preserved.
=== Double-Precision Floating-Point Computational Instructions
The double-precision floating-point computational instructions are
defined analogously to their single-precision counterparts, but operate
on double-precision operands and produce double-precision results.
include::images/wavedrom/double-fl-compute.adoc[]
[[fl-compute]]
//.Double-precision float computational
=== Double-Precision Floating-Point Conversion and Move Instructions
Floating-point-to-integer and integer-to-floating-point conversion
instructions are encoded in the OP-FP major opcode space. FCVT.W.D or
FCVT.L.D converts a double-precision floating-point number in
floating-point register _rs1_ to a signed 32-bit or 64-bit integer,
respectively, in integer register _rd_. FCVT.D.W or FCVT.D.L converts a
32-bit or 64-bit signed integer, respectively, in integer register _rs1_
into a double-precision floating-point number in floating-point register
_rd_. FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to
or from unsigned integer values. For RV64, FCVT.W[U].D sign-extends the
32-bit result. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions.
The range of valid inputs for FCVT._int_.D and the behavior for invalid
inputs are the same as for FCVT._int_.S.
(((floating point, convert and move)))
All floating-point to integer and integer to floating-point conversion
instructions round according to the _rm_ field. Note FCVT.D.W[U] always
produces an exact result and is unaffected by rounding mode.
include::images/wavedrom/double-fl-convert-mv.adoc[]
[[fl-convert-mv]]
//.Double-precision float convert and move
The double-precision to single-precision and single-precision to
double-precision conversion instructions, FCVT.S.D and FCVT.D.S, are
encoded in the OP-FP major opcode space and both the source and
destination are floating-point registers. The _rs2_ field encodes the
datatype of the source, and the _fmt_ field encodes the datatype of the
destination. FCVT.S.D rounds according to the RM field; FCVT.D.S will
never round.
(((double-precision, to single-precision)))
(((single-precision, to double-precision )))
include::images/wavedrom/fcvt-sd-ds.adoc[]
[[fcvt-sd-ds]]
//.Double-precision FCVT.S.D and FCVT.D.S
Floating-point to floating-point sign-injection instructions, FSGNJ.D,
FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision
sign-injection instruction.
//FSGNJ.D, FSGNJN.D, and FSGNJX.D
include::images/wavedrom/fsjgnjnx-d.adoc[]
//.Double-precision sign-injection
For XLEN&#8805;64 only, instructions are provided to move bit
patterns between the floating-point and integer registers. FMV.X.D moves
the double-precision value in floating-point register _rs1_ to a
representation in IEEE 754-2008 standard encoding in integer register
_rd_. FMV.D.X moves the double-precision value encoded in IEEE 754-2008
standard encoding from the integer register _rs1_ to the floating-point
register _rd_.
FMV.X.D and FMV.D.X do not modify the bits being transferred; in
particular, the payloads of non-canonical NaNs are preserved.
include::images/wavedrom/d-xwwx.adoc[]
[[fmvxddx]]
//.Double-precision float move to _rd_
[TIP]
====
Early versions of the RISC-V ISA had additional instructions to allow
RV32 systems to transfer between the upper and lower portions of a
64-bit floating-point register and an integer register. However, these
would be the only instructions with partial register writes and would
add complexity in implementations with recoded floating-point or
register renaming, requiring a pipeline read-modify-write sequence.
Scaling up to handling quad-precision for RV32 and RV64 would also
require additional instructions if they were to follow this pattern. The
ISA was defined to reduce the number of explicit int-float register
moves, by having conversions and comparisons write results to the
appropriate register file, so we expect the benefit of these
instructions to be lower than for other ISAs.
We note that for systems that implement a 64-bit floating-point unit
including fused multiply-add support and 64-bit floating-point loads and
stores, the marginal hardware cost of moving from a 32-bit to a 64-bit
integer datapath is low, and a software ABI supporting 32-bit wide
address-space and pointers can be used to avoid growth of static data
and dynamic memory traffic.
====
=== Double-Precision Floating-Point Compare Instructions
The double-precision floating-point compare instructions are defined
analogously to their single-precision counterparts, but operate on
double-precision operands.
(((floating-point, compare)))
include::images/wavedrom/double-fl-compare.adoc[]
[[fl-compare]]
//.Double-precision float compare
=== Double-Precision Floating-Point Classify Instruction
The double-precision floating-point classify instruction, FCLASS.D, is
defined analogously to its single-precision counterpart, but operates on
double-precision operands.
(((floating-point, classify)))
include::images/wavedrom/double-fl-class.adoc[]
[[fl-class]]
//.Double-precision float classify

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[[extending]]
== Extending RISC-V
In addition to supporting standard general-purpose software development,
another goal of RISC-V is to provide a basis for more specialized
instruction-set extensions or more customized accelerators. The
instruction encoding spaces and optional variable-length instruction
encoding are designed to make it easier to leverage software development
effort for the standard ISA toolchain when building more customized
processors. For example, the intent is to continue to provide full
software support for implementations that only use the standard I base,
perhaps together with many non-standard instruction-set extensions.
This chapter describes various ways in which the base RISC-V ISA can be
extended, together with the scheme for managing instruction-set
extensions developed by independent groups. This volume only deals with
the unprivileged ISA, although the same approach and terminology is used
for supervisor-level extensions described in the second volume.
=== Extension Terminology
This section defines some standard terminology for describing RISC-V
extensions.
==== Standard versus Non-Standard Extension
Any RISC-V processor implementation must support a base integer ISA
(RV32I, RV32E, RV64I, RV64E, or RV128I). In addition, an implementation may
support one or more extensions. We divide extensions into two broad
categories: _standard_ versus _non-standard_.
* A standard extension is one that is generally useful and that is
designed to not conflict with any other standard extension. Currently,
"MAFDQLCBTPV", described in other chapters of this manual, are either
complete or planned standard extensions.
* A non-standard extension may be highly specialized and may conflict
with other standard or non-standard extensions. We anticipate a wide
variety of non-standard extensions will be developed over time, with
some eventually being promoted to standard extensions.
==== Instruction Encoding Spaces and Prefixes
An instruction encoding space is some number of instruction bits within
which a base ISA or ISA extension is encoded. RISC-V supports varying
instruction lengths, but even within a single instruction length, there
are various sizes of encoding space available. For example, the base
ISAs are defined within a 30-bit encoding space (bits 31-2 of the 32-bit
instruction), while the atomic extension "A" fits within a 25-bit
encoding space (bits 31-7).
We use the term _prefix_ to refer to the bits to the _right_ of an
instruction encoding space (since instruction fetch in RISC-V is
little-endian, the bits to the right are stored at earlier memory
addresses, hence form a prefix in instruction-fetch order). The prefix
for the standard base ISA encoding is the two-bit "11" field held in
bits 1-0 of the 32-bit word, while the prefix for the standard atomic
extension "A" is the seven-bit "0101111" field held in bits 6-0 of
the 32-bit word representing the AMO major opcode. A quirk of the
encoding format is that the 3-bit funct3 field used to encode a minor
opcode is not contiguous with the major opcode bits in the 32-bit
instruction format, but is considered part of the prefix for 22-bit
instruction spaces.
Although an instruction encoding space could be of any size, adopting a
smaller set of common sizes simplifies packing independently developed
extensions into a single global encoding.
<<encodingspaces>> gives the suggested sizes for RISC-V.
[[encodingspaces]]
.Suggested standard RISC-V instruction encoding space sizes.
[%autowidth,float="center",align="center",cols="^,<,>,>,>,>", options="header"]
|===
|Size |Usage
4+^| # Available in standard instruction length
| | |16-bit |32-bit |48-bit |64-bit
6+|
|14-bit |Quadrant of compressed 16-bit encoding |3 | | |
6+|
|22-bit |Minor opcode in base 32-bit encoding | |latexmath:[$2^{8}$]
|latexmath:[$2^{20}$] |latexmath:[$2^{35}$]
|25-bit |Major opcode in base 32-bit encoding | |32
|latexmath:[$2^{17}$] |latexmath:[$2^{32}$]
|30-bit |Quadrant of base 32-bit encoding | |1 |latexmath:[$2^{12}$]
|latexmath:[$2^{27}$]
6+|
|32-bit |Minor opcode in 48-bit encoding | | |latexmath:[$2^{10}$]
|latexmath:[$2^{25}$]
|37-bit |Major opcode in 48-bit encoding | | |32 |latexmath:[$2^{20}$]
|40-bit |Quadrant of 48-bit encoding | | |4 |latexmath:[$2^{17}$]
6+|
|45-bit |Sub-minor opcode in 64-bit encoding | | | |latexmath:[$2^{12}$]
|48-bit |Minor opcode in 64-bit encoding | | | |latexmath:[$2^{9}$]
|52-bit |Major opcode in 64-bit encoding | | | |32
|===
==== Greenfield versus Brownfield Extensions
We use the term _greenfield extension_ to describe an extension that
begins populating a new instruction encoding space, and hence can only
cause encoding conflicts at the prefix level. We use the term
_brownfield extension_ to describe an extension that fits around
existing encodings in a previously defined instruction space. A
brownfield extension is necessarily tied to a particular greenfield
parent encoding, and there may be multiple brownfield extensions to the
same greenfield parent encoding. For example, the base ISAs are
greenfield encodings of a 30-bit instruction space, while the FDQ
floating-point extensions are all brownfield extensions adding to the
parent base ISA 30-bit encoding space.
Note that we consider the standard A extension to have a greenfield
encoding as it defines a new previously empty 25-bit encoding space in
the leftmost bits of the full 32-bit base instruction encoding, even
though its standard prefix locates it within the 30-bit encoding space
of its parent base ISA. Changing only its single 7-bit prefix could move
the A extension to a different 30-bit encoding space while only worrying
about conflicts at the prefix level, not within the encoding space
itself.
[[exttax]]
.Two-dimensional characterization of standard instruction-set extensions.
[cols="^,^,^",options="header",]
[%autowidth, float="center", align="center"]
|===
| |Adds state |No new state
|Greenfield |RV32I(30), RV64I(30) |A(25)
|Brownfield |F(I), D(F), Q(D) |M(I)
|===
<<exttax>> shows the bases and standard extensions placed
in a simple two-dimensional taxonomy. One axis is whether the extension
is greenfield or brownfield, while the other axis is whether the
extension adds architectural state. For greenfield extensions, the size
of the instruction encoding space is given in parentheses. For
brownfield extensions, the name of the extension (greenfield or
brownfield) it builds upon is given in parentheses. Additional
user-level architectural state usually implies changes to the
supervisor-level system or possibly to the standard calling convention.
Note that RV64I is not considered an extension of RV32I, but a different
complete base encoding.
==== Standard-Compatible Global Encodings
A complete or _global_ encoding of an ISA for an actual RISC-V
implementation must allocate a unique non-conflicting prefix for every
included instruction encoding space. The bases and every standard
extension have each had a standard prefix allocated to ensure they can
all coexist in a global encoding.
A _standard-compatible_ global encoding is one where the base and every
included standard extension have their standard prefixes. A
standard-compatible global encoding can include non-standard extensions
that do not conflict with the included standard extensions. A
standard-compatible global encoding can also use standard prefixes for
non-standard extensions if the associated standard extensions are not
included in the global encoding. In other words, a standard extension
must use its standard prefix if included in a standard-compatible global
encoding, but otherwise its prefix is free to be reallocated. These
constraints allow a common toolchain to target the standard subset of
any RISC-V standard-compatible global encoding.
==== Guaranteed Non-Standard Encoding Space
To support development of proprietary custom extensions, portions of the
encoding space are guaranteed to never be used by standard extensions.
=== RISC-V Extension Design Philosophy
We intend to support a large number of independently developed
extensions by encouraging extension developers to operate within
instruction encoding spaces, and by providing tools to pack these into a
standard-compatible global encoding by allocating unique prefixes. Some
extensions are more naturally implemented as brownfield augmentations of
existing extensions, and will share whatever prefix is allocated to
their parent greenfield extension. The standard extension prefixes avoid
spurious incompatibilities in the encoding of core functionality, while
allowing custom packing of more esoteric extensions.
This capability of repacking RISC-V extensions into different
standard-compatible global encodings can be used in a number of ways.
One use-case is developing highly specialized custom accelerators,
designed to run kernels from important application domains. These might
want to drop all but the base integer ISA and add in only the extensions
that are required for the task in hand. The base ISAs have been designed
to place minimal requirements on a hardware implementation, and has been
encoded to use only a small fraction of a 32-bit instruction encoding
space.
Another use-case is to build a research prototype for a new type of
instruction-set extension. The researchers might not want to expend the
effort to implement a variable-length instruction-fetch unit, and so
would like to prototype their extension using a simple 32-bit
fixed-width instruction encoding. However, this new extension might be
too large to coexist with standard extensions in the 32-bit space. If
the research experiments do not need all of the standard extensions, a
standard-compatible global encoding might drop the unused standard
extensions and reuse their prefixes to place the proposed extension in a
non-standard location to simplify engineering of the research prototype.
Standard tools will still be able to target the base and any standard
extensions that are present to reduce development time. Once the
instruction-set extension has been evaluated and refined, it could then
be made available for packing into a larger variable-length encoding
space to avoid conflicts with all standard extensions.
The following sections describe increasingly sophisticated strategies
for developing implementations with new instruction-set extensions.
These are mostly intended for use in highly customized, educational, or
experimental architectures rather than for the main line of RISC-V ISA
development.
[[fix32b]]
=== Extensions within fixed-width 32-bit instruction format
In this section, we discuss adding extensions to implementations that
only support the base fixed-width 32-bit instruction format.
[NOTE]
====
We anticipate the simplest fixed-width 32-bit encoding will be popular
for many restricted accelerators and research prototypes.
====
==== Available 30-bit instruction encoding spaces
In the standard encoding, three of the available 30-bit instruction
encoding spaces (those with 2-bit prefixes `00`, `01`, and `10`) are used to
enable the optional compressed instruction extension. However, if the
compressed instruction-set extension is not required, then these three
further 30-bit encoding spaces become available. This quadruples the
available encoding space within the 32-bit format.
==== Available 25-bit instruction encoding spaces
A 25-bit instruction encoding space corresponds to a major opcode in the
base and standard extension encodings.
There are four major opcodes expressly designated for custom extensions
<<opcodemap>>, each of which represents a 25-bit
encoding space. Two of these are reserved for eventual use in the RV128
base encoding (will be OP-IMM-64 and OP-64), but can be used for
non-standard extensions for RV32 and RV64.
The two major opcodes reserved for RV64 (OP-IMM-32 and OP-32) can also
be used for non-standard extensions to RV32 only.
If an implementation does not require floating-point, then the seven
major opcodes reserved for standard floating-point extensions (LOAD-FP,
STORE-FP, MADD, MSUB, NMSUB, NMADD, OP-FP) can be reused for
non-standard extensions. Similarly, the AMO major opcode can be reused
if the standard atomic extensions are not required.
If an implementation does not require instructions longer than 32-bits,
then an additional four major opcodes are available (those marked in
gray in <<opcodemap>>).
The base RV32I encoding uses only 11 major opcodes plus 3 reserved
opcodes, leaving up to 18 available for extensions. The base RV64I
encoding uses only 13 major opcodes plus 3 reserved opcodes, leaving up
to 16 available for extensions.
==== Available 22-bit instruction encoding spaces
A 22-bit encoding space corresponds to a funct3 minor opcode space in
the base and standard extension encodings. Several major opcodes have a
funct3 field minor opcode that is not completely occupied, leaving
available several 22-bit encoding spaces.
Usually a major opcode selects the format used to encode operands in the
remaining bits of the instruction, and ideally, an extension should
follow the operand format of the major opcode to simplify hardware
decoding.
==== Other spaces
Smaller spaces are available under certain major opcodes, and not all
minor opcodes are entirely filled.
=== Adding aligned 64-bit instruction extensions
The simplest approach to provide space for extensions that are too large
for the base 32-bit fixed-width instruction format is to add naturally
aligned 64-bit instructions. The implementation must still support the
32-bit base instruction format, but can require that 64-bit instructions
are aligned on 64-bit boundaries to simplify instruction fetch, with a
32-bit NOP instruction used as alignment padding where necessary.
To simplify use of standard tools, the 64-bit instructions should be
encoded as described in <<instlengthcode, Table 1>>.
However, an implementation might choose a non-standard
instruction-length encoding for 64-bit instructions, while retaining the
standard encoding for 32-bit instructions. For example, if compressed
instructions are not required, then a 64-bit instruction could be
encoded using one or more zero bits in the first two bits of an
instruction.
[NOTE]
====
We anticipate processor generators that produce instruction-fetch units
capable of automatically handling any combination of supported
variable-length instruction encodings.
====
=== Supporting VLIW encodings
Although RISC-V was not designed as a base for a pure VLIW machine, VLIW
encodings can be added as extensions using several alternative
approaches. In all cases, the base 32-bit encoding has to be supported
to allow use of any standard software tools.
==== Fixed-size instruction group
The simplest approach is to define a single large naturally aligned
instruction format (e.g., 128 bits) within which VLIW operations are
encoded. In a conventional VLIW, this approach would tend to waste
instruction memory to hold NOPs, but a RISC-V-compatible implementation
would have to also support the base 32-bit instructions, confining the
VLIW code size expansion to VLIW-accelerated functions.
==== Encoded-Length Groups
Another approach is to use the standard length encoding from
<<instlengthcode>> to encode parallel
instruction groups, allowing NOPs to be compressed out of the VLIW
instruction. For example, a 64-bit instruction could hold two 28-bit
operations, while a 96-bit instruction could hold three 28-bit
operations, and so on. Alternatively, a 48-bit instruction could hold
one 42-bit operation, while a 96-bit instruction could hold two 42-bit
operations, and so on.
This approach has the advantage of retaining the base ISA encoding for
instructions holding a single operation, but has the disadvantage of
requiring a new 28-bit or 42-bit encoding for operations within the VLIW
instructions, and misaligned instruction fetch for larger groups. One
simplification is to not allow VLIW instructions to straddle certain
microarchitecturally significant boundaries (e.g., cache lines or
virtual memory pages).
==== Fixed-Size Instruction Bundles
Another approach, similar to Itanium, is to use a larger naturally
aligned fixed instruction bundle size (e.g., 128 bits) across which
parallel operation groups are encoded. This simplifies instruction
fetch, but shifts the complexity to the group execution engine. To
remain RISC-V compatible, the base 32-bit instruction would still have
to be supported.
==== End-of-Group bits in Prefix
None of the above approaches retains the RISC-V encoding for the
individual operations within a VLIW instruction. Yet another approach is
to repurpose the two prefix bits in the fixed-width 32-bit encoding. One
prefix bit can be used to signal "end-of-group" if set, while the
second bit could indicate execution under a predicate if clear. Standard
RISC-V 32-bit instructions generated by tools unaware of the VLIW
extension would have both prefix bits set (11) and thus have the correct
semantics, with each instruction at the end of a group and not
predicated.
The main disadvantage of this approach is that the base ISAs lack the
complex predication support usually required in an aggressive VLIW
system, and it is difficult to add space to specify more predicate
registers in the standard 30-bit encoding space.

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:stem: latexmath
[[single-float]]
== "F" Standard Extension for Single-Precision Floating-Point, Version 2.2
This chapter describes the standard instruction-set extension for
single-precision floating-point, which is named "F" and adds
single-precision floating-point computational instructions compliant
with the IEEE 754-2008 arithmetic standard cite:[ieee754-2008]. The F extension depends on the "Zicsr" extension for control and status register access.
=== F Register State
The F extension adds 32 floating-point registers, `f0-f31`, each 32
bits wide, and a floating-point control and status register `fcsr`,
which contains the operating mode and exception status of the
floating-point unit. This additional state is shown in
<<fprs>>. We use the term FLEN to describe the width of
the floating-point registers in the RISC-V ISA, and FLEN=32 for the F
single-precision floating-point extension. Most floating-point
instructions operate on values in the floating-point register file.
Floating-point load and store instructions transfer floating-point
values between registers and memory. Instructions to transfer values to and from the integer register file are also provided.
[TIP]
====
We considered a unified register file for both integer and
floating-point values as this simplifies software register allocation
and calling conventions, and reduces total user state. However, a split
organization increases the total number of registers accessible with a
given instruction width, simplifies provision of enough regfile ports
for wide superscalar issue, supports decoupled floating-point-unit
architectures, and simplifies use of internal floating-point encoding
techniques. Compiler support and calling conventions for split register
file architectures are well understood, and using dirty bits on
floating-point register file state can reduce context-switch overhead.
====
[[fprs]]
.RISC-V standard F extension single-precision floating-point state
[col[s="<|^|>"|option[s="header",width="50%",align="center"grid="rows"]
|===
| [.small]#FLEN-1#| >| [.small]#0#
3+^| [.small]#f0#
3+^| [.small]#f1#
3+^| [.small]#f2#
3+^| [.small]#f3#
3+^| [.small]#f4#
3+^| [.small]#f5#
3+^| [.small]#f6#
3+^| [.small]#f7#
3+^| [.small]#f8#
3+^| [.small]#f9#
3+^| [.small]#f10#
3+^| [.small]#f11#
3+^| [.small]#f12#
3+^| [.small]#f13#
3+^| [.small]#f14#
3+^| [.small]#f15#
3+^| [.small]#f16#
3+^| [.small]#f17#
3+^| [.small]#f18#
3+^| [.small]#f19#
3+^| [.small]#f20#
3+^| [.small]#f21#
3+^| [.small]#f22#
3+^| [.small]#f23#
3+^| [.small]#f24#
3+^| [.small]#f25#
3+^| [.small]#f26#
3+^| [.small]#f27#
3+^| [.small]#f28#
3+^| [.small]#f29#
3+^| [.small]#f30#
3+^| [.small]#f31#
3+^| [.small]#FLEN#
| [.small]#31#| >| [.small]#0#
3+^| [.small]#fcsr#
3+^| [.small]#32#
|===
=== Floating-Point Control and Status Register
The floating-point control and status register, `fcsr`, is a RISC-V
control and status register (CSR). It is a 32-bit read/write register
that selects the dynamic rounding mode for floating-point arithmetic
operations and holds the accrued exception flags, as shown in <<fcsr>>.
[[fcsr, Floating-Point Control and Status Register]]
.Floating-point control and status register
include::images/wavedrom/float-csr.adoc[]
The `fcsr` register can be read and written with the FRCSR and FSCSR
instructions, which are assembler pseudoinstructions built on the
underlying CSR access instructions. FRCSR reads `fcsr` by copying it
into integer register _rd_. FSCSR swaps the value in `fcsr` by copying
the original value into integer register _rd_, and then writing a new
value obtained from integer register _rs1_ into `fcsr`.
The fields within the `fcsr` can also be accessed individually through
different CSR addresses, and separate assembler pseudoinstructions are defined
for these accesses. The FRRM instruction reads the Rounding Mode field `frm`
(`fcsr` bits 7--5) and copies it into the least-significant three bits of
integer register _rd_, with zero in all other bits. FSRM swaps the value in
`frm` by copying the original value into integer register _rd_, and then
writing a new value obtained from the three least-significant bits of integer
register _rs1_ into `frm`. FRFLAGS and FSFLAGS are defined analogously for the
Accrued Exception Flags field `fflags` (`fcsr` bits 4--0).
Bits 31--8 of the `fcsr` are reserved for other standard extensions. If
these extensions are not present, implementations shall ignore writes to
these bits and supply a zero value when read. Standard software should
preserve the contents of these bits.
Floating-point operations use either a static rounding mode encoded in
the instruction, or a dynamic rounding mode held in `frm`. Rounding
modes are encoded as shown in <<rm>>. A value of 111 in the
instruction's _rm_ field selects the dynamic rounding mode held in
`frm`. The behavior of floating-point instructions that depend on
rounding mode when executed with a reserved rounding mode is _reserved_, including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111). Some instructions, including widening conversions, have the _rm_ field but are nevertheless mathematically unaffected by the rounding mode; software should set their _rm_ field to
RNE (000) but implementations must treat the _rm_ field as usual (in
particular, with regard to decoding legal vs. reserved encodings).
[[rm]]
.Rounding mode encoding.
[%autowidth,float="center",align="center",cols="^,^,<",options="header"]
|===
|Rounding Mode |Mnemonic |Meaning
|000 |RNE |Round to Nearest, ties to Even
|001 |RTZ |Round towards Zero
|010 |RDN |Round Down (towards latexmath:[$-\infty$])
|011 |RUP |Round Up (towards latexmath:[$+\infty$])
|100 |RMM |Round to Nearest, ties to Max Magnitude
|101 | |_Reserved for future use._
|110 | |_Reserved for future use._
|111 |DYN |In instruction's _rm_ field, selects dynamic rounding mode; In Rounding Mode register, _reserved_.
|===
[NOTE]
====
The C99 language standard effectively mandates the provision of a
dynamic rounding mode register. In typical implementations, writes to
the dynamic rounding mode CSR state will serialize the pipeline. Static
rounding modes are used to implement specialized arithmetic operations
that often have to switch frequently between different rounding modes.
The ratified version of the F spec mandated that an illegal-instruction
exception was raised when an instruction was executed with a reserved
dynamic rounding mode. This has been weakened to reserved, which matches
the behavior of static rounding-mode instructions. Raising an
illegal-instruction exception is still valid behavior when encountering a
reserved encoding, so implementations compatible with the ratified spec
are compatible with the weakened spec.
====
The accrued exception flags indicate the exception conditions that have
arisen on any floating-point arithmetic instruction since the field was
last reset by software, as shown in <<bitdef>>. The base
RISC-V ISA does not support generating a trap on the setting of a
floating-point exception flag.
(((floating-point, exception flag)))
[[bitdef]]
.Accrued exception flag encoding.
[%autowidth,float="center",align="center",cols="^,<",options="header",]
|===
|Flag Mnemonic |Flag Meaning
|NV |Invalid Operation
|DZ |Divide by Zero
|OF |Overflow
|UF |Underflow
|NX |Inexact
|===
[NOTE]
====
As allowed by the standard, we do not support traps on floating-point
exceptions in the F extension, but instead require explicit checks of
the flags in software. We considered adding branches controlled directly
by the contents of the floating-point accrued exception flags, but
ultimately chose to omit these instructions to keep the ISA simple.
====
=== NaN Generation and Propagation
Except when otherwise stated, if the result of a floating-point
operation is NaN, it is the canonical NaN. The canonical NaN has a
positive sign and all significand bits clear except the MSB, a.k.a. the
quiet bit. For single-precision floating-point, this corresponds to the pattern `0x7fc00000`.
(((NaN, generation)))
(((NaN, propagation)))
[TIP]
====
We considered propagating NaN payloads, as is recommended by the
standard, but this decision would have increased hardware cost.
Moreover, since this feature is optional in the standard, it cannot be
used in portable code.
Implementors are free to provide a NaN payload propagation scheme as a
nonstandard extension enabled by a nonstandard operating mode. However, the canonical NaN scheme described above must always be supported and should be the default mode.
====
'''
[NOTE]
====
We require implementations to return the standard-mandated default
values in the case of exceptional conditions, without any further
intervention on the part of user-level software (unlike the Alpha ISA
floating-point trap barriers). We believe full hardware handling of
exceptional cases will become more common, and so wish to avoid
complicating the user-level ISA to optimize other approaches.
Implementations can always trap to machine-mode software handlers to
provide exceptional default values.
====
=== Subnormal Arithmetic
Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard.
(((operations, subnormal)))
In the parlance of the IEEE standard, tininess is detected after
rounding.
(((tininess, handling)))
[NOTE]
====
Detecting tininess after rounding results in fewer spurious underflow
signals.
====
=== Single-Precision Load and Store Instructions
Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register _rs1_ and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register _rd_. FSW stores a single-precision value from floating-point register _rs2_ to memory.
include::images/wavedrom/sp-load-store-2.adoc[]
[[sp-ldst]]
//.SP load and store
FLW and FSW are only guaranteed to execute atomically if the effective
address is naturally aligned.
FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
As described in <<ldst>>, the execution environment defines whether misaligned floating-point loads and stores are handled invisibly or raise a contained or fatal trap.
[[single-float-compute]]
=== Single-Precision Floating-Point Computational Instructions
Floating-point arithmetic instructions with one or two source operands
use the R-type format with the OP-FP major opcode. FADD.S and FMUL.S
perform single-precision floating-point addition and multiplication
respectively, between _rs1_ and _rs2_. FSUB.S performs the
single-precision floating-point subtraction of _rs2_ from _rs1_. FDIV.S performs the single-precision floating-point division of _rs1_ by _rs2_. FSQRT.S computes the square root of _rs1_. In each case, the result is written to _rd_.
The 2-bit floating-point format field _fmt_ is encoded as shown in
<<fmt>>. It is set to _S_ (00) for all instructions in the F extension.
[[fmt]]
.Format field encoding
[%autowidth,float="center",align="center",cols="^,^,<",options="header",]
|===
|_fmt_ field |Mnemonic |Meaning
|00 |S |32-bit single-precision
|01 |D |64-bit double-precision
|10 |H |16-bit half-precision
|11 |Q |128-bit quad-precision
|===
All floating-point operations that perform rounding can select the
rounding mode using the _rm_ field with the encoding shown in
<<rm>>.
Floating-point minimum-number and maximum-number instructions FMIN.S and FMAX.S write, respectively, the smaller or larger of _rs1_ and _rs2_ to _rd_. For the purposes of these instructions only, the value
latexmath:[$-0.0$] is considered to be less than the value
latexmath:[$+0.0$]. If both inputs are NaNs, the result is the canonical NaN. If only one operand is a NaN, the result is the non-NaN operand.
Signaling NaN inputs set the invalid operation exception flag, even when the result is not NaN.
[NOTE]
====
Note that in version 2.2 of the F extension, the FMIN.S and FMAX.S
instructions were amended to implement the proposed IEEE 754-201x
minimumNumber and maximumNumber operations, rather than the IEEE
754-2008 minNum and maxNum operations. These operations differ in their
handling of signaling NaNs.
====
include::images/wavedrom/spfloat.adoc[]
[[spfloat]]
//.Single-Precision Floating-Point Computational Instructions
(((floating point, fused multiply-add)))
Floating-point fused multiply-add instructions require a new standard
instruction format. R4-type instructions specify three source registers (_rs1_, _rs2_, and _rs3_) and a destination register (_rd_). This format is only used by the floating-point fused multiply-add instructions.
FMADD.S multiplies the values in _rs1_ and _rs2_, adds the value in
_rs3_, and writes the final result to _rd_. FMADD.S computes
_(rs1latexmath:[$\times$]rs2)latexmath:[$\+$]rs3_.
FMSUB.S multiplies the values in _rs1_ and _rs2_, subtracts the value in _rs3_, and writes the final result to _rd_. FMSUB.S computes
_(rs1latexmath:[$\times$]rs2)latexmath:[$\-$]rs3_.
FNMSUB.S multiplies the values in _rs1_ and _rs2_, negates the product, adds the value in _rs3_, and writes the final result to _rd_. FNMSUB.S computes _-(rs1latexmath:[$\times$]rs2)latexmath:[$\+$]rs3_.
FNMADD.S multiplies the values in _rs1_ and _rs2_, negates the product, subtracts the value in _rs3_, and writes the final result to _rd_. FNMADD.S computes _-(rs1latexmath:[$\times$]rs2)latexmath:[$\-$]rs3_.
[NOTE]
====
The FNMSUB and FNMADD instructions are counterintuitively named, owing
to the naming of the corresponding instructions in MIPS-IV. The MIPS
instructions were defined to negate the sum, rather than negating the
product as the RISC-V instructions do, so the naming scheme was more
rational at the time. The two definitions differ with respect to
signed-zero results. The RISC-V definition matches the behavior of the
x86 and ARM fused multiply-add instructions, but unfortunately the
RISC-V FNMSUB and FNMADD instruction names are swapped compared to x86
and ARM.
====
include::images/wavedrom/spfloat2.adoc[]
[[fnmaddsub]]
//.F[N]MADD/F[N]MSUB instructions
[NOTE]
====
The fused multiply-add (FMA) instructions consume a large part of the
32-bit instruction encoding space. Some alternatives considered were to
restrict FMA to only use dynamic rounding modes, but static rounding
modes are useful in code that exploits the lack of product rounding.
Another alternative would have been to use rd to provide rs3, but this
would require additional move instructions in some common sequences. The current design still leaves a large portion of the 32-bit encoding space open while avoiding having FMA be non-orthogonal.
====
The fused multiply-add instructions must set the invalid operation
exception flag when the multiplicands are latexmath:[$\infty$] and zero, even when the addend is a quiet NaN.
[NOTE]
====
The IEEE 754-2008 standard permits, but does not require, raising the
invalid exception for the operation latexmath:[$\infty\times 0\ +$]qNaN.
====
=== Single-Precision Floating-Point Conversion and Move Instructions
Floating-point-to-integer and integer-to-floating-point conversion
instructions are encoded in the OP-FP major opcode space. FCVT.W.S or
FCVT.L.S converts a floating-point number in floating-point register
_rs1_ to a signed 32-bit or 64-bit integer, respectively, in integer
register _rd_. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed
integer, respectively, in integer register _rs1_ into a floating-point
number in floating-point register _rd_. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU,
and FCVT.S.LU variants convert to or from unsigned integer values. For
XLENlatexmath:[$>32$], FCVT.W[U].S sign-extends the 32-bit result to the
destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only
instructions. If the rounded result is not representable in the
destination format, it is clipped to the nearest value and the invalid
flag is set. <<int_conv>> gives the range of valid inputs
for FCVT._int_.S and the behavior for invalid inputs.
(((floating-point, conversion)))
All floating-point to integer and integer to floating-point conversion
instructions round according to the _rm_ field. A floating-point
register can be initialized to floating-point positive zero using
FCVT.S.W _rd_, `x0`, which will never set any exception flags.
[[int_conv]]
.Domains of float-to-integer conversions and behavior for invalid inputs
[%autowidth,float="center",align="center",cols="<,>,>,>,>",options="header",]
|===
| |FCVT.W.S |FCVT.WU.S |FCVT.L.S |FCVT.LU.S
|Minimum valid input (after rounding) |latexmath:[$-2^{31}$] |0
|latexmath:[$-2^{63}$] |0
|Maximum valid input (after rounding) |latexmath:[$2^{31}-1$]
|latexmath:[$2^{32}-1$] |latexmath:[$2^{63}-1$] |latexmath:[$2^{64}-1$]
|Output for out-of-range negative input |latexmath:[$-2^{31}$] |0
|latexmath:[$-2^{63}$] |0
|Output for latexmath:[$-\infty$] |latexmath:[$-2^{31}$] |0
|latexmath:[$-2^{63}$] |0
|Output for out-of-range positive input |latexmath:[$2^{31}-1$]
|latexmath:[$2^{32}-1$] |latexmath:[$2^{63}-1$] |latexmath:[$2^{64}-1$]
|Output for latexmath:[$+\infty$] or NaN |latexmath:[$2^{31}-1$]
|latexmath:[$2^{32}-1$] |latexmath:[$2^{63}-1$] |latexmath:[$2^{64}-1$]
|===
All floating-point conversion instructions set the Inexact exception
flag if the rounded result differs from the operand value and the
Invalid exception flag is not set.
include::images/wavedrom/spfloat-cn-cmp.adoc[]
[[fcvt]]
//.SP float convert and move
Floating-point to floating-point sign-injection instructions, FSGNJ.S,
FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the
sign bit from _rs1_. For FSGNJ, the result's sign bit is _rs2_'s sign
bit; for FSGNJN, the result's sign bit is the opposite of _rs2_'s sign
bit; and for FSGNJX, the sign bit is the XOR of the sign bits of _rs1_
and _rs2_. Sign-injection instructions do not set floating-point
exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S _rx, ry,
ry_ moves _ry_ to _rx_ (assembler pseudoinstruction FMV.S _rx, ry_);
FSGNJN.S _rx, ry, ry_ moves the negation of _ry_ to _rx_ (assembler
pseudoinstruction FNEG.S _rx, ry_); and FSGNJX.S _rx, ry, ry_ moves the absolute value of _ry_ to _rx_ (assembler pseudoinstruction FABS.S _rx,
ry_).
include::images/wavedrom/spfloat-sign-inj.adoc[]
[[inj]]
[NOTE]
====
The sign-injection instructions provide floating-point MV, ABS, and NEG, as well as supporting a few other operations, including the IEEE
copySign operation and sign manipulation in transcendental math function libraries. Although MV, ABS, and NEG only need a single register operand, whereas FSGNJ instructions need two, it is unlikely most microarchitectures would add optimizations to benefit from the reduced number of register reads for these relatively infrequent instructions. Even in this case, a microarchitecture can simply detect when both source registers are the same for FSGNJ instructions and only read a single copy.
====
Instructions are provided to move bit patterns between the
floating-point and integer registers. FMV.X.W moves the single-precision value in floating-point register _rs1_ represented in IEEE 754-2008 encoding to the lower 32 bits of integer register _rd_. The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved. For RV64, the higher 32 bits of the destination register are filled with copies of the floating-point number's sign bit.
FMV.W.X moves the single-precision value encoded in IEEE 754-2008
standard encoding from the lower 32 bits of integer register _rs1_ to
the floating-point register _rd_. The bits are not modified in the
transfer, and in particular, the payloads of non-canonical NaNs are
preserved.
[NOTE]
====
The FMV.W.X and FMV.X.W instructions were previously called FMV.S.X and FMV.X.S. The use of W is more consistent with their semantics as an instruction that moves 32 bits without interpreting them. This became clearer after defining NaN-boxing. To avoid disturbing existing code, both the W and S versions will be supported by tools.
====
include::images/wavedrom/spfloat-mv.adoc[]
[[spfloat-mv]]
//.SP floating point move
[TIP]
====
The base floating-point ISA was defined so as to allow implementations
to employ an internal recoding of the floating-point format in registers to simplify handling of subnormal values and possibly to reduce functional unit latency. To this end, the F extension avoids
representing integer values in the floating-point registers by defining conversion and comparison operations that read and write the integer register file directly. This also removes many of the common cases where explicit moves between integer and floating-point registers are required, reducing instruction count and critical paths for common mixed-format code sequences.
====
=== Single-Precision Floating-Point Compare Instructions
Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the
specified comparison between floating-point registers
(latexmath:[$\mbox{\em rs1}
= \mbox{\em rs2}$], latexmath:[$\mbox{\em rs1} < \mbox{\em rs2}$],
latexmath:[$\mbox{\em rs1} \leq
\mbox{\em rs2}$]) writing 1 to the integer register _rd_ if the
condition holds, and 0 otherwise.
FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as
_signaling_ comparisons: that is, they set the invalid operation
exception flag if either input is NaN. FEQ.S performs a _quiet_
comparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For all three instructions, the result is 0 if either operand is NaN.
include::images/wavedrom/spfloat-comp.adoc[]
[[spfloat-comp]]
//.SP floating point compare
[NOTE]
====
The F extension provides a latexmath:[$\leq$] comparison, whereas the
base ISAs provide a latexmath:[$\geq$] branch comparison. Because
latexmath:[$\leq$] can be synthesized from latexmath:[$\geq$] and
vice-versa, there is no performance implication to this inconsistency,
but it is nevertheless an unfortunate incongruity in the ISA.
====
=== Single-Precision Floating-Point Classify Instruction
The FCLASS.S instruction examines the value in floating-point register
_rs1_ and writes to integer register _rd_ a 10-bit mask that indicates
the class of the floating-point number. The format of the mask is
described in <<fclass>>. The corresponding bit in _rd_ will
be set if the property is true and clear otherwise. All other bits in
_rd_ are cleared. Note that exactly one bit in _rd_ will be set.
FCLASS.S does not set the floating-point exception flags.
(((floating-point, classification)))
include::images/wavedrom/spfloat-classify.adoc[]
[[spfloat-classify]]
//.SP floating point classify
[[fclass]]
.Format of result of FCLASS instruction.
[%autowidth,float="center",align="center",cols="^,<",options="header",]
|===
|_rd_ bit |Meaning
|0 |_rs1_ is latexmath:[$-\infty$].
|1 |_rs1_ is a negative normal number.
|2 |_rs1_ is a negative subnormal number.
|3 |_rs1_ is latexmath:[$-0$].
|4 |_rs1_ is latexmath:[$+0$].
|5 |_rs1_ is a positive subnormal number.
|6 |_rs1_ is a positive normal number.
|7 |_rs1_ is latexmath:[$+\infty$].
|8 |_rs1_ is a signaling NaN.
|9 |_rs1_ is a quiet NaN.
|===

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[[history]]
== History and Acknowledgments
=== "Why Develop a new ISA?" Rationale from Berkeley Group
We developed RISC-V to support our own needs in research and education,
where our group is particularly interested in actual hardware
implementations of research ideas (we have completed eleven different
silicon fabrications of RISC-V since the first edition of this
specification), and in providing real implementations for students to
explore in classes (RISC-V processor RTL designs have been used in
multiple undergraduate and graduate classes at Berkeley). In our current
research, we are especially interested in the move towards specialized
and heterogeneous accelerators, driven by the power constraints imposed
by the end of conventional transistor scaling. We wanted a highly
flexible and extensible base ISA around which to build our research
effort.
A question we have been repeatedly asked is "Why develop a new ISA?"
The biggest obvious benefit of using an existing commercial ISA is the
large and widely supported software ecosystem, both development tools
and ported applications, which can be leveraged in research and
teaching. Other benefits include the existence of large amounts of
documentation and tutorial examples. However, our experience of using
commercial instruction sets for research and teaching is that these
benefits are smaller in practice, and do not outweigh the disadvantages:
* *Commercial ISAs are proprietary.* Except for SPARC V8, which is an
open IEEE standard cite:[sparcieee1994] , most owners of commercial ISAs carefully guard
their intellectual property and do not welcome freely available
competitive implementations. This is much less of an issue for academic
research and teaching using only software simulators, but has been a
major concern for groups wishing to share actual RTL implementations. It
is also a major concern for entities who do not want to trust the few
sources of commercial ISA implementations, but who are prohibited from
creating their own clean room implementations. We cannot guarantee that
all RISC-V implementations will be free of third-party patent
infringements, but we can guarantee we will not attempt to sue a RISC-V
implementor.
* *Commercial ISAs are only popular in certain market domains.* The most
obvious examples at time of writing are that the ARM architecture is not
well supported in the server space, and the Intel x86 architecture (or
for that matter, almost every other architecture) is not well supported
in the mobile space, though both Intel and ARM are attempting to enter
each other's market segments. Another example is ARC and Tensilica,
which provide extensible cores but are focused on the embedded space.
This market segmentation dilutes the benefit of supporting a particular
commercial ISA as in practice the software ecosystem only exists for
certain domains, and has to be built for others.
* *Commercial ISAs come and go.* Previous research infrastructures have
been built around commercial ISAs that are no longer popular (SPARC,
MIPS) or even no longer in production (Alpha). These lose the benefit of
an active software ecosystem, and the lingering intellectual property
issues around the ISA and supporting tools interfere with the ability of
interested third parties to continue supporting the ISA. An open ISA
might also lose popularity, but any interested party can continue using
and developing the ecosystem.
* *Popular commercial ISAs are complex.* The dominant commercial ISAs
(x86 and ARM) are both very complex to implement in hardware to the
level of supporting common software stacks and operating systems. Worse,
nearly all the complexity is due to bad, or at least outdated, ISA
design decisions rather than features that truly improve efficiency.
* *Commercial ISAs alone are not enough to bring up applications.* Even
if we expend the effort to implement a commercial ISA, this is not
enough to run existing applications for that ISA. Most applications need
a complete ABI (application binary interface) to run, not just the
user-level ISA. Most ABIs rely on libraries, which in turn rely on
operating system support. To run an existing operating system requires
implementing the supervisor-level ISA and device interfaces expected by
the OS. These are usually much less well-specified and considerably more
complex to implement than the user-level ISA.
* *Popular commercial ISAs were not designed for extensibility.* The
dominant commercial ISAs were not particularly designed for
extensibility, and as a consequence have added considerable instruction
encoding complexity as their instruction sets have grown. Companies such
as Tensilica (acquired by Cadence) and ARC (acquired by Synopsys) have
built ISAs and toolchains around extensibility, but have focused on
embedded applications rather than general-purpose computing systems.
* *A modified commercial ISA is a new ISA.* One of our main goals is to
support architecture research, including major ISA extensions. Even
small extensions diminish the benefit of using a standard ISA, as
compilers have to be modified and applications rebuilt from source code
to use the extension. Larger extensions that introduce new architectural
state also require modifications to the operating system. Ultimately,
the modified commercial ISA becomes a new ISA, but carries along all the
legacy baggage of the base ISA.
Our position is that the ISA is perhaps the most important interface in
a computing system, and there is no reason that such an important
interface should be proprietary. The dominant commercial ISAs are based
on instruction-set concepts that were already well known over 30 years
ago. Software developers should be able to target an open standard
hardware target, and commercial processor designers should compete on
implementation quality.
We are far from the first to contemplate an open ISA design suitable for
hardware implementation. We also considered other existing open ISA
designs, of which the closest to our goals was the OpenRISC
architecture cite:[openriscarch]. We decided against adopting the OpenRISC ISA for several
technical reasons:
* OpenRISC has condition codes and branch delay slots, which complicate
higher performance implementations.
* OpenRISC uses a fixed 32-bit encoding and 16-bit immediates, which
precludes a denser instruction encoding and limits space for later
expansion of the ISA.
* OpenRISC does not support the 2008 revision to the IEEE 754
floating-point standard.
* The OpenRISC 64-bit design had not been completed when we began.
By starting from a clean slate, we could design an ISA that met all of
our goals, though of course, this took far more effort than we had
planned at the outset. We have now invested considerable effort in
building up the RISC-V ISA infrastructure, including documentation,
compiler tool chains, operating system ports, reference ISA simulators,
FPGA implementations, efficient ASIC implementations, architecture test
suites, and teaching materials. Since the last edition of this manual,
there has been considerable uptake of the RISC-V ISA in both academia
and industry, and we have created the non-profit RISC-V Foundation to
protect and promote the standard. The RISC-V Foundation website at
https://riscv.org contains the latest information on the Foundation
membership and various open-source projects using RISC-V.
=== History from Revision 1.0 of ISA manual
The RISC-V ISA and instruction-set manual builds upon several earlier
projects. Several aspects of the supervisor-level machine and the
overall format of the manual date back to the T0 (Torrent-0) vector
microprocessor project at UC Berkeley and ICSI, begun in 1992. T0 was a
vector processor based on the MIPS-II ISA, with Krste Asanović as main
architect and RTL designer, and Brian Kingsbury and Bertrand Irrisou as
principal VLSI implementors. David Johnson at ICSI was a major
contributor to the T0 ISA design, particularly supervisor mode, and to
the manual text. John Hauser also provided considerable feedback on the
T0 ISA design.
The Scale (Software-Controlled Architecture for Low Energy) project at
MIT, begun in 2000, built upon the T0 project infrastructure, refined
the supervisor-level interface, and moved away from the MIPS scalar ISA
by dropping the branch delay slot. Ronny Krashinsky and Christopher
Batten were the principal architects of the Scale Vector-Thread
processor at MIT, while Mark Hampton ported the GCC-based compiler
infrastructure and tools for Scale.
A lightly edited version of the T0 MIPS scalar processor specification
(MIPS-6371) was used in teaching a new version of the MIT 6.371
Introduction to VLSI Systems class in the Fall 2002 semester, with Chris
Terman and Krste Asanović as lecturers. Chris Terman contributed most of
the lab material for the class (there was no TA!). The 6.371 class
evolved into the trial 6.884 Complex Digital Design class at MIT, taught
by Arvind and Krste Asanović in Spring 2005, which became a regular
Spring class 6.375. A reduced version of the Scale MIPS-based scalar
ISA, named SMIPS, was used in 6.884/6.375. Christopher Batten was the TA
for the early offerings of these classes and developed a considerable
amount of documentation and lab material based around the SMIPS ISA.
This same SMIPS lab material was adapted and enhanced by TA Yunsup Lee
for the UC Berkeley Fall 2009 CS250 VLSI Systems Design class taught by
John Wawrzynek, Krste Asanović, and John Lazzaro.
The Maven (Malleable Array of Vector-thread ENgines) project was a
second-generation vector-thread architecture. Its design was led by
Christopher Batten when he was an Exchange Scholar at UC Berkeley
starting in summer 2007. Hidetaka Aoki, a visiting industrial fellow
from Hitachi, gave considerable feedback on the early Maven ISA and
microarchitecture design. The Maven infrastructure was based on the
Scale infrastructure but the Maven ISA moved further away from the MIPS
ISA variant defined in Scale, with a unified floating-point and integer
register file. Maven was designed to support experimentation with
alternative data-parallel accelerators. Yunsup Lee was the main
implementor of the various Maven vector units, while Rimas Avižienis was
the main implementor of the various Maven scalar units. Yunsup Lee and
Christopher Batten ported GCC to work with the new Maven ISA.
Christopher Celio provided the initial definition of a traditional
vector instruction set ("Flood") variant of Maven.
Based on experience with all these previous projects, the RISC-V ISA
definition was begun in Summer 2010, with Andrew Waterman, Yunsup Lee,
Krste Asanović, and David Patterson as principal designers. An initial
version of the RISC-V 32-bit instruction subset was used in the UC
Berkeley Fall 2010 CS250 VLSI Systems Design class, with Yunsup Lee as
TA. RISC-V is a clean break from the earlier MIPS-inspired designs. John
Hauser contributed to the floating-point ISA definition, including the
sign-injection instructions and a register encoding scheme that permits
internal recoding of floating-point values.
=== History from Revision 2.0 of ISA manual
Multiple implementations of RISC-V processors have been completed,
including several silicon fabrications, as shown in
<<silicon, Fabricated RISC-V testchips table>>.
[[silicon]]
[%autowidth,float="center",align="center",cols="^,^,^,^",options="header",]
|===
|Name |Tapeout Date |Process |ISA
|Raven-1 |May 29, 2011 |ST 28nm FDSOI |RV64G1_Xhwacha1
|EOS14 |April 1, 2012 |IBM 45nm SOI |RV64G1p1_Xhwacha2
|EOS16 |August 17, 2012 |IBM 45nm SOI |RV64G1p1_Xhwacha2
|Raven-2 |August 22, 2012 |ST 28nm FDSOI |RV64G1p1_Xhwacha2
|EOS18 |February 6, 2013 |IBM 45nm SOI |RV64G1p1_Xhwacha2
|EOS20 |July 3, 2013 |IBM 45nm SOI |RV64G1p99_Xhwacha2
|Raven-3 |September 26, 2013 |ST 28nm SOI |RV64G1p99_Xhwacha2
|EOS22 |March 7, 2014 |IBM 45nm SOI |RV64G1p9999_Xhwacha3
|===
The first RISC-V processors to be fabricated were written in Verilog and
manufactured in a pre-production FDSOI technology from ST as the Raven-1
testchip in 2011. Two cores were developed by Yunsup Lee and Andrew
Waterman, advised by Krste Asanović, and fabricated together: 1) an RV64
scalar core with error-detecting flip-flops, and 2) an RV64 core with an
attached 64-bit floating-point vector unit. The first microarchitecture
was informally known as "TrainWreck", due to the short time available
to complete the design with immature design libraries.
Subsequently, a clean microarchitecture for an in-order decoupled RV64
core was developed by Andrew Waterman, Rimas Avižienis, and Yunsup Lee,
advised by Krste Asanović, and, continuing the railway theme, was
codenamed "Rocket" after George Stephenson's successful steam
locomotive design. Rocket was written in Chisel, a new hardware design
language developed at UC Berkeley. The IEEE floating-point units used in
Rocket were developed by John Hauser, Andrew Waterman, and Brian
Richards. Rocket has since been refined and developed further, and has
been fabricated two more times in FDSOI (Raven-2, Raven-3), and five
times in IBM SOI technology (EOS14, EOS16, EOS18, EOS20, EOS22) for a
photonics project. Work is ongoing to make the Rocket design available
as a parameterized RISC-V processor generator.
EOS14-EOS22 chips include early versions of Hwacha, a 64-bit IEEE
floating-point vector unit, developed by Yunsup Lee, Andrew Waterman,
Huy Vo, Albert Ou, Quan Nguyen, and Stephen Twigg, advised by Krste
Asanović. EOS16-EOS22 chips include dual cores with a cache-coherence
protocol developed by Henry Cook and Andrew Waterman, advised by Krste
Asanović. EOS14 silicon has successfully run at 1.25 GHz. EOS16 silicon suffered
from a bug in the IBM pad libraries. EOS18 and EOS20 have successfully
run at 1.35 GHz.
Contributors to the Raven testchips include Yunsup Lee, Andrew Waterman,
Rimas Avižienis, Brian Zimmer, Jaehwa Kwak, Ruzica Jevtić, Milovan
Blagojević, Alberto Puggelli, Steven Bailey, Ben Keller, Pi-Feng Chiu,
Brian Richards, Borivoje Nikolić, and Krste Asanović.
Contributors to the EOS testchips include Yunsup Lee, Rimas Avižienis,
Andrew Waterman, Henry Cook, Huy Vo, Daiwei Li, Chen Sun, Albert Ou,
Quan Nguyen, Stephen Twigg, Vladimir Stojanović, and Krste Asanović.
Andrew Waterman and Yunsup Lee developed the C++ ISA simulator
"Spike", used as a golden model in development and named after the
golden spike used to celebrate completion of the US transcontinental
railway. Spike has been made available as a BSD open-source project.
Andrew Waterman completed a Master's thesis with a preliminary design of
the RISC-V compressed instruction set cite:[waterman-ms].
Various FPGA implementations of the RISC-V have been completed,
primarily as part of integrated demos for the Par Lab project research
retreats. The largest FPGA design has 3 cache-coherent RV64IMA
processors running a research operating system. Contributors to the FPGA
implementations include Andrew Waterman, Yunsup Lee, Rimas Avižienis,
and Krste Asanović.
RISC-V processors have been used in several classes at UC Berkeley.
Rocket was used in the Fall 2011 offering of CS250 as a basis for class
projects, with Brian Zimmer as TA. For the undergraduate CS152 class in
Spring 2012, Christopher Celio used Chisel to write a suite of
educational RV32 processors, named "Sodor" after the island on which
"Thomas the Tank Engine" and friends live. The suite includes a
microcoded core, an unpipelined core, and 2, 3, and 5-stage pipelined
cores, and is publicly available under a BSD license. The suite was
subsequently updated and used again in CS152 in Spring 2013, with Yunsup
Lee as TA, and in Spring 2014, with Eric Love as TA. Christopher Celio
also developed an out-of-order RV64 design known as BOOM (Berkeley
Out-of-Order Machine), with accompanying pipeline visualizations, that
was used in the CS152 classes. The CS152 classes also used
cache-coherent versions of the Rocket core developed by Andrew Waterman
and Henry Cook.
Over the summer of 2013, the RoCC (Rocket Custom Coprocessor) interface
was defined to simplify adding custom accelerators to the Rocket core.
Rocket and the RoCC interface were used extensively in the Fall 2013
CS250 VLSI class taught by Jonathan Bachrach, with several student
accelerator projects built to the RoCC interface. The Hwacha vector unit
has been rewritten as a RoCC coprocessor.
Two Berkeley undergraduates, Quan Nguyen and Albert Ou, have
successfully ported Linux to run on RISC-V in Spring 2013.
Colin Schmidt successfully completed an LLVM backend for RISC-V 2.0 in
January 2014.
Darius Rad at Bluespec contributed soft-float ABI support to the GCC
port in March 2014.
John Hauser contributed the definition of the floating-point
classification instructions.
We are aware of several other RISC-V core implementations, including one
in Verilog by Tommy Thorn, and one in Bluespec by Rishiyur Nikhil.
=== Acknowledgments
Thanks to Christopher F. Batten, Preston Briggs, Christopher Celio,
David Chisnall, Stefan Freudenberger, John Hauser, Ben Keller, Rishiyur
Nikhil, Michael Taylor, Tommy Thorn, and Robert Watson for comments on
the draft ISA version 2.0 specification.
=== History from Revision 2.1
Uptake of the RISC-V ISA has been very rapid since the introduction of
the frozen version 2.0 in May 2014, with too much activity to record in
a short history section such as this. Perhaps the most important single
event was the formation of the non-profit RISC-V Foundation in August
2015. The Foundation will now take over stewardship of the official
RISC-V ISA standard, and the official website `riscv.org` is the best
place to obtain news and updates on the RISC-V standard.
=== Acknowledgments
Thanks to Scott Beamer, Allen J. Baum, Christopher Celio, David
Chisnall, Paul Clayton, Palmer Dabbelt, Jan Gray, Michael Hamburg, and
John Hauser for comments on the version 2.0 specification.
=== History from Revision 2.2
=== Acknowledgments
Thanks to Jacob Bachmeyer, Alex Bradbury, David Horner, Stefan O’Rear,
and Joseph Myers for comments on the version 2.1 specification.
=== History for Revision 2.3
Uptake of RISC-V continues at a breakneck pace.
John Hauser and Andrew Waterman contributed a hypervisor ISA extension
based upon a proposal from Paolo Bonzini.
Daniel Lustig, Arvind, Krste Asanović, Shaked Flur, Paul Loewenstein,
Yatin Manerkar, Luc Maranget, Margaret Martonosi, Vijayanand Nagarajan,
Rishiyur Nikhil, Jonas Oberhauser, Christopher Pulte, Jose Renau, Peter
Sewell, Susmit Sarkar, Caroline Trippel, Muralidaran Vijayaraghavan,
Andrew Waterman, Derek Williams, Andrew Wright, and Sizhuo Zhang
contributed the memory consistency model.
=== Funding
Development of the RISC-V architecture and implementations has been
partially funded by the following sponsors.
* *Par Lab:* Research supported by Microsoft (Award # 024263) and Intel
(Award # 024894) funding and by matching funding by U.C. Discovery (Award
# DIG07-10227). Additional support came from Par Lab affiliates Nokia,
NVIDIA, Oracle, and Samsung.
* *Project Isis:* DoE Award DE-SC0003624.
* *ASPIRE Lab*: DARPA PERFECT program, Award HR0011-12-2-0016. DARPA
POEM program Award HR0011-11-C-0100. The Center for Future Architectures
Research (C-FAR), a STARnet center funded by the Semiconductor Research
Corporation. Additional support from ASPIRE industrial sponsor, Intel,
and ASPIRE affiliates, Google, Hewlett Packard Enterprise, Huawei,
Nokia, NVIDIA, Oracle, and Samsung.
The content of this paper does not necessarily reflect the position or
the policy of the US government and no official endorsement should be
inferred.

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[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback"}])
(def row-height 45)
(def row-header-fn nil)
(def boxes-per-row 32)
(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "1" "2" "" "3" "" "4" "" "5" "6" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "28" "" "29" "" "30" "" "31"])})
(draw-box "HPM31" {:span 2})
(draw-box "HPM30" {:span 2})
(draw-box "HPM29" {:span 2})
(draw-box "..." {:span 17})
(draw-box "HPM5" {:span 2})
(draw-box "HPM4" {:span 2})
(draw-box "HPM3" {:span 2})
(draw-box "IR" {:span 1})
(draw-box "TM" {:span 1})
(draw-box "CY" {:span 1})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "23" {:span 17 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
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[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback"}])
(def row-height 45)
(def row-header-fn nil)
(def boxes-per-row 32)
(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "1" "2" "" "3" "" "4" "" "5" "6" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "28" "" "29" "" "30" "" "31"])})
(draw-box "HPM31" {:span 2})
(draw-box "HPM30" {:span 2})
(draw-box "HPM29" {:span 2})
(draw-box "..." {:span 17})
(draw-box "HPM5" {:span 2})
(draw-box "HPM4" {:span 2})
(draw-box "HPM3" {:span 2})
(draw-box "IR" {:span 1})
(draw-box "0" {:span 1})
(draw-box "CY" {:span 1})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "23" {:span 17 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
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----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback"}])
(def row-height 35 )
(def row-header-fn nil)
(def left-margin 0)
(def right-margin 40)
(def boxes-per-row 32)
(draw-column-headers {:height 24 :font-size 20 :labels (reverse ["" "" "" "" "" "" "" "0" "" "6" "7" "" "11" "12" "" "14" "15" "" "" "" "" "" "" "" "" "25" "26" "" "" "" "" "31"])})
(draw-box "funct6" {:span 6})
(draw-box "custom" {:span 10})
(draw-box "funct3" {:span 3})
(draw-box "custom" {:span 3})
(draw-box "opcode" {:span 3})
(draw-box (text "Recommended Purpose" {}) {:span 7 :text-anchor "middle" :borders {}})
(draw-box "6" {:span 6 :borders {}})
(draw-box "11" {:span 10 :borders {}})
(draw-box "3" {:span 3 :borders {}})
(draw-box "5" {:span 3 :borders {}})
(draw-box "7" {:span 3 :borders {}})
(draw-box nil {:span 7 :borders {}})
(draw-box "100011" {:span 6 :borders {}})
(draw-box (text "custom" {:font-style "italic"}) {:span 10 :borders {}})
(draw-box "0" {:span 3 :borders {}})
(draw-box (text "custom" {:font-style "italic"}) {:span 3 :borders {}})
(draw-box "SYSTEM" {:span 3 :borders {}})
(draw-box (text "Unprivileged or User-Level" {}) {:span 7 :text-anchor "middle" :borders {}})
(draw-box "110011" {:span 6 :borders {}})
(draw-box (text "custom" {:font-style "italic"}) {:span 10 :borders {}})
(draw-box "0" {:span 3 :borders {}})
(draw-box (text "custom" {:font-style "italic"}) {:span 3 :borders {}})
(draw-box "SYSTEM" {:span 3 :borders {}})
(draw-box (text "Unprivileged or User-Level" {}) {:span 7 :text-anchor "middle" :borders {}})
(draw-box "100111" {:span 6 :borders {}})
(draw-box (text "custom" {:font-style "italic"}) {:span 10 :borders {}})
(draw-box "0" {:span 3 :borders {}})
(draw-box (text "custom" {:font-style "italic"}) {:span 3 :borders {}})
(draw-box "SYSTEM" {:span 3 :borders {}})
(draw-box (text " Supervisor-Level" {}) {:span 7 :text-anchor "middle" :borders {}})
(draw-box "110111" {:span 6 :borders {}})
(draw-box (text "custom" {:font-style "italic"}) {:span 10 :borders {}})
(draw-box "0" {:span 3 :borders {}})
(draw-box (text "custom" {:font-style "italic"}) {:span 3 :borders {}})
(draw-box "SYSTEM" {:span 3 :borders {}})
(draw-box (text "Supervisor-Level" {}) {:span 7 :text-anchor "middle" :borders {}})
(draw-box "101011" {:span 6 :borders {}})
(draw-box (text "custom" {:font-style "italic"}) {:span 10 :borders {}})
(draw-box "0" {:span 3 :borders {}})
(draw-box (text "custom" {:font-style "italic"}) {:span 3 :borders {}})
(draw-box "SYSTEM" {:span 3 :borders {}})
(draw-box (text "Hypervisor-Level" {}) {:span 7 :text-anchor "middle" :borders {}})
(draw-box "111011" {:span 6 :borders {}})
(draw-box (text "custom" {:font-style "italic"}) {:span 10 :borders {}})
(draw-box "0" {:span 3 :borders {}})
(draw-box (text "custom" {:font-style "italic"}) {:span 3 :borders {}})
(draw-box "SYSTEM" {:span 3 :borders {}})
(draw-box (text "Hypervisor-Level" {}) {:span 7 :text-anchor "middle" :borders {}})
(draw-box "101111" {:span 6 :borders {}})
(draw-box (text "custom" {:font-style "italic"}) {:span 10 :borders {}})
(draw-box "0" {:span 3 :borders {}})
(draw-box (text "custom" {:font-style "italic"}) {:span 3 :borders {}})
(draw-box "SYSTEM" {:span 3 :borders {}})
(draw-box (text "Machine-Level" {}) {:span 7 :text-anchor "middle" :borders {}})
(draw-box "111111" {:span 6 :borders {}})
(draw-box (text "custom" {:font-style "italic"}) {:span 10 :borders {}})
(draw-box "0" {:span 3 :borders {}})
(draw-box (text "custom" {:font-style "italic"}) {:span 3 :borders {}})
(draw-box "SYSTEM" {:span 3 :borders {}})
(draw-box (text "Machine-Level" {}) {:span 7 :text-anchor "middle" :borders {}})
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----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "SXLEN-1" {:span 16 :text-anchor "start" :borders {}})
(draw-box "0" {:span 16 :text-anchor "end" :borders {}})
(draw-box "sepc" {:span 32})
(draw-box "SXLEN" {:span 32 :borders {}})
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----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "31" {:span 2 :borders {}})
(draw-box "30" {:span 2 :borders {}})
(draw-box "29" {:span 2 :borders {}})
(draw-box "28" {:span 10 :text-anchor "start" :borders {}})
(draw-box "6" {:span 7 :text-anchor "end" :borders {}})
(draw-box "5" {:span 2 :borders {}})
(draw-box "4" {:span 2 :borders {}})
(draw-box "3" {:span 2 :borders {}})
(draw-box "2" {:borders {}})
(draw-box "1" {:borders {}})
(draw-box "0" {:borders {}})
(draw-box "HPM31" {:font-size 20 :span 2})
(draw-box "HPM30" {:font-size 20 :span 2})
(draw-box "HPM29" {:font-size 20 :span 2})
(draw-box "..." {:span 17})
(draw-box "HPM5" {:span 2})
(draw-box "HPM4" {:span 2})
(draw-box "HPM3" {:span 2})
(draw-box "IR" )
(draw-box "TM" )
(draw-box "CY" )
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "23" {:span 17 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:borders {}})
(draw-box "1" {:borders {}})
(draw-box "1" {:borders {}})
----

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----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "HSXLEN-1" {:span 16 :text-anchor "start" :borders{}})
(draw-box "0" {:span 16 :text-anchor "end" :borders{}})
(draw-box "Synchronous Exceptions" {:span 18 :text-anchor "end" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" { :font-weight "bold" :font-size 24}) {:span 14 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "HSXLEN" {:span 32 :borders {}})
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----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "63" {:span 2 :borders {}})
(draw-box "62" {:span 2 :borders {}})
(draw-box "61" {:span 9 :text-anchor "start" :borders {}})
(draw-box "8" {:span 9 :text-anchor "end" :borders {}})
(draw-box "7" {:span 2 :borders {}})
(draw-box "6" {:span 2 :borders {}})
(draw-box "5" {:borders {}})
(draw-box "4" {:borders {}})
(draw-box "3" {:borders {}})
(draw-box "1" {:borders {}})
(draw-box "0" {:span 2 :borders {}})
(draw-box "STCE" {:span 2})
(draw-box "PBMTE" {:font-size 22 :span 2})
(draw-box (text "WPRI" {:font-size 24 :font-weight "bold"}) {:span 18})
(draw-box "CBZE" {:span 2})
(draw-box "CBCFE" {:span 2})
(draw-box "CBIE" {:span 2})
(draw-box (text "WPRI" {:font-size 24 :font-weight "bold"}) {:span 2})
(draw-box "FIOM" {:span 2})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "54" {:span 18 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "3" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
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----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-column-headers {:height 24 :font-size 24 :labels (reverse ["0" "1" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "HSXLEN-1" ""])})
(draw-box "Guest External Interrupts" {:span 18 :text-anchor "end" :borders {:left :border-unrelated :top :border-unrelated :bottom :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 13 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated}})
(draw-box "0" )
(draw-box "HSXLEN" {:font-size 24 :span 31 :borders {}})
(draw-box "1" {:borders {}})
----

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[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-column-headers {:height 24 :font-size 24 :labels (reverse ["0" "1" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "HSXLEN-1" ""])})
(draw-box "Guest External Interrupts" {:span 31})
(draw-box "0" )
(draw-box "HSXLEN" {:span 31 :borders {}})
(draw-box "1" {:borders {}})
----

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[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "HSXLEN-1" {:span 16 :text-anchor "start" :borders{}})
(draw-box "0" {:span 16 :text-anchor "end" :borders{}})
(draw-box "Interrupts" {:span 16 :text-anchor "end" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" { :font-weight "bold" :font-size 24}) {:span 16 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "HSXLEN" {:span 32 :borders {}})
----

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[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "15" {:span 2 :text-anchor "start" :borders {}})
(draw-box "13" {:span 2 :text-anchor "end" :borders {}})
(draw-box "12" {:span 4 :borders {}})
(draw-box "11" {:span 4 :borders {}})
(draw-box "10" {:span 4 :borders {}})
(draw-box "9" {:span 2 :text-anchor "start" :borders {}})
(draw-box "7" {:span 2 :text-anchor "end" :borders {}})
(draw-box "6" {:span 4 :borders {}})
(draw-box "5" {:borders {}})
(draw-box "3" {:borders {}})
(draw-box "2" {:span 4 :borders {}})
(draw-box "1" {:borders {}})
(draw-box "0" {:borders {}})
(draw-box "0" {:span 4})
(draw-box "SGEIE" {:span 4})
(draw-box "0" {:span 4})
(draw-box "VSEIE" {:span 4})
(draw-box "0" {:span 4})
(draw-box "VSTIE" {:span 4})
(draw-box "0" {:span 2})
(draw-box "VSSIE" {:span 4})
(draw-box "0" {:span 2})
(draw-box "3" {:span 4 :borders{}})
(draw-box "1" {:span 4 :borders {}})
(draw-box "1" {:span 4 :borders {}})
(draw-box "1" {:span 4 :borders {}})
(draw-box "3" {:span 4 :borders {}})
(draw-box "1" {:span 4 :borders {}})
(draw-box "3" {:span 2 :borders {}})
(draw-box "1" {:span 4 :borders {}})
(draw-box "2" {:span 2 :borders {}})
----

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[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "HSXLEN-1" {:span 16 :text-anchor "start" :borders{}})
(draw-box "0" {:span 16 :text-anchor "end" :borders{}})
(draw-box "Interrupts" {:span 16 :text-anchor "end" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" { :font-weight "bold" :font-size 24}) {:span 16 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "HSXLEN" {:span 32 :borders {}})
----

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[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "15" {:span 2 :text-anchor "start" :borders {}})
(draw-box "13" {:span 2 :text-anchor "end" :borders {}})
(draw-box "12" {:span 4 :borders {}})
(draw-box "11" {:span 4 :borders {}})
(draw-box "10" {:span 4 :borders {}})
(draw-box "9" {:span 2 :text-anchor "start" :borders {}})
(draw-box "7" {:span 2 :text-anchor "end" :borders {}})
(draw-box "6" {:span 4 :borders {}})
(draw-box "5" {:borders {}})
(draw-box "3" {:borders {}})
(draw-box "2" {:span 4 :borders {}})
(draw-box "1" {:borders {}})
(draw-box "0" {:borders {}})
(draw-box "0" {:span 4})
(draw-box "SGEIP" {:span 4})
(draw-box "0" {:span 4})
(draw-box "VSEIP" {:span 4})
(draw-box "0" {:span 4})
(draw-box "VSTIP" {:span 4})
(draw-box "0" {:span 2})
(draw-box "VSSIP" {:span 4})
(draw-box "0" {:span 2})
(draw-box "3" {:span 4 :borders{}})
(draw-box "1" {:span 4 :borders {}})
(draw-box "1" {:span 4 :borders {}})
(draw-box "1" {:span 4 :borders {}})
(draw-box "3" {:span 4 :borders {}})
(draw-box "1" {:span 4 :borders {}})
(draw-box "3" {:span 2 :borders {}})
(draw-box "1" {:span 4 :borders {}})
(draw-box "2" {:span 2 :borders {}})
----

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[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "HSXLEN-1" {:span 16 :text-anchor "start" :borders{}})
(draw-box "0" {:span 16 :text-anchor "end" :borders{}})
(draw-box "Interrupts" {:span 16 :text-anchor "end" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" { :font-weight "bold" :font-size 24}) {:span 16 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "HSXLEN" {:span 32 :borders {}})
----

20
vendor/riscv/riscv-isa-manual/src/images/bytefield/hpmcounters.adoc vendored
View file

@ -1,20 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback"}])
(def row-header-fn nil)
(def boxes-per-row 14)
(def left-margin 200)
(def right-margin 200)
(draw-box "31" {:span 7 :text-anchor "start" :borders {}})
(draw-box "0" {:span 7 :text-anchor "end" :borders {}})
(draw-box "mcycleh" {:span 14})
(draw-box "minstreth" {:span 14})
(draw-box "mhpmcounter3h" {:span 14})
(draw-box "mhpmcounter4h" {:span 14})
(draw-box "⋮" {:span 14})
(draw-box "mhpmcounter30h" {:span 14})
(draw-box "mhpmcounter31h" {:span 14})
(draw-box "32" {:span 14 :borders {}})
----

47
vendor/riscv/riscv-isa-manual/src/images/bytefield/hpmevents.adoc vendored
View file

@ -1,47 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40)
(def row-header-fn nil)
(def left-margin 40)
(def right-margin 40)
(def boxes-per-row 32)
(draw-column-headers {:height 26 :font-size 24 :labels (reverse ["" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "0" "" "" "" "" "" "" "" "" "" "" "" "" "63"])})
(draw-box "mcycle" {:span 14})
(draw-box nil {:span 4 :borders {}})
(draw-box nil {:span 14 :borders {}})
(draw-box "minstret" {:span 14})
(draw-box nil {:span 4 :borders {}})
(draw-box nil {:span 14 :borders {}})
(draw-box nil {:span 14 :borders {}})
(draw-box nil {:span 4 :borders {}})
(draw-box "MXLEN-1" {:span 7 :text-anchor "start" :borders{}})
(draw-box "0" {:span 7 :text-anchor "end" :borders{}})
(draw-box "mhpmcounter3" {:span 14})
(draw-box nil {:span 4 :borders {}})
(draw-box "mhpmevent3" {:span 14})
(draw-box "mhpmcounter4" {:span 14})
(draw-box nil {:span 4 :borders {}})
(draw-box "mhpmevent4" {:span 14})
(draw-box "⋮" {:span 14 :borders {}})
(draw-box nil {:span 4 :borders {}})
(draw-box "⋮" {:span 14 :borders {}})
(draw-box "mhpmcounter30" {:span 14})
(draw-box nil {:span 4 :borders {}})
(draw-box "mhpmevent30" {:span 14})
(draw-box "mhpmcounter31" {:span 14})
(draw-box nil {:span 4 :borders {}})
(draw-box "mhpmevent31" {:span 14})
(draw-box "64" {:span 14 :borders {}})
(draw-box nil {:span 4 :borders {}})
(draw-box "MXLEN" {:span 14 :borders {}})
----

59
vendor/riscv/riscv-isa-manual/src/images/bytefield/hstatusreg-rv32.edn vendored
View file

@ -1,59 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box nil {:borders {}})
(draw-box "31" {:span 2 :borders {} :text-anchor "start"})
(draw-box "23" {:borders {}})
(draw-box "22" {:span 2 :borders {}})
(draw-box "21" {:span 2 :borders {}})
(draw-box "20" {:span 2 :borders {}})
(draw-box "19" {:borders {}})
(draw-box "18" {:borders {}})
(draw-box "17" {:span 2 :borders {} :text-anchor "start"})
(draw-box "12" {:span 3:borders {}})
(draw-box "11" {:borders {}})
(draw-box "10" {:borders {}})
(draw-box "9" {:borders {}})
(draw-box "8" {:span 2 :borders {}})
(draw-box "7" {:span 3 :borders {}})
(draw-box "6" {:span 3 :borders {}})
(draw-box "5" {:span 2 :borders {}})
(draw-box "4" {:borders {}})
(draw-box "0" {:borders {}})
(draw-box nil {:borders {}})
(draw-box (text "WPRI" {:font-weight "bold" :font-size 24}) {:span 3})
(draw-box "VTSR" {:span 2})
(draw-box "VTW" {:span 2})
(draw-box "VTVM" {:span 2})
(draw-box (text "WPRI" {:font-weight "bold" :font-size 24}) {:span 2})
(draw-box "VGEIN[5:0]" {:span 5})
(draw-box (text "WPRI" {:font-weight "bold" :font-size 24}) {:span 2})
(draw-box "HU")
(draw-box "SPVP" {:span 2})
(draw-box "SPV" {:span 3})
(draw-box "GVA" {:span 3})
(draw-box "VSBE" {:span 2})
(draw-box (text "WPRI" {:font-weight "bold" :font-size 24}) {:span 2})
(draw-box nil {:borders {}})
(draw-box "9" {:span 3 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "6" {:span 5 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "1" {:borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "5" {:span 2 :borders {}})
----

86
vendor/riscv/riscv-isa-manual/src/images/bytefield/hstatusreg.edn vendored
View file

@ -1,86 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box nil {:span 3 :borders {}})
(draw-box "HSXLEN-1" {:span 8 :borders {} :text-anchor "start"})
(draw-box "34" {:borders {}})
(draw-box "33" {:span 2 :borders {} :text-anchor "start"})
(draw-box "32" {:span 2 :borders {} :text-anchor "end"})
(draw-box "31" {:span 3 :borders {} :text-anchor "start"})
(draw-box "23" {:span 3 :borders {} :text-anchor "end"})
(draw-box "22" {:span 2:borders {}})
(draw-box "21" {:span 2 :borders {}})
(draw-box "20" {:span 2:borders {}})
(draw-box nil {:borders {}})
(draw-box nil {:span 3 :borders {}})
(draw-box nil {:span 3 :borders {}})
(draw-box (text "WPRI" {:font-weight "bold" :font-size 24}) {:span 9})
(draw-box "VSXL[1:0]" {:span 4})
(draw-box (text "WPRI" {:font-weight "bold" :font-size 24}) {:span 6})
(draw-box "VTSR" {:span 2})
(draw-box "VTW" {:span 2})
(draw-box "VTVM" {:span 2})
(draw-box nil {:borders {:top :border-unrelated :bottom :border-unrelated}})
(draw-box nil {:span 3 :borders {}})
(draw-box nil {:span 3 :borders {}})
(draw-box "HSXLEN-34" {:span 9 :borders {}})
(draw-box "2" {:span 4 :borders {}})
(draw-box "9" {:span 6 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box nil {:span 4 :borders {}})
(draw-box nil {:span 32 :borders {}})
(draw-box nil {:span 6 :borders {}})
(draw-box nil {:borders {}})
(draw-box "19" {:borders {}})
(draw-box "18" {:borders {}})
(draw-box "17" {:span 2 :borders {} :text-anchor "start"})
(draw-box "12" {:span 2 :borders {} :text-anchor "end"})
(draw-box "11" {:borders {}})
(draw-box "10" {:borders {}})
(draw-box "9" {:borders {}})
(draw-box "8" {:span 2 :borders {}})
(draw-box "7" {:span 2 :borders {}})
(draw-box "6" {:span 2:borders {}})
(draw-box "5" {:span 2 :borders {}})
(draw-box "4" {:span 2 :borders {} :text-anchor "start"})
(draw-box "0" {:span 2 :borders {} :text-anchor "end"})
(draw-box nil {:span 4 :borders {}})
(draw-box nil {:span 6 :borders {}})
(draw-box nil {:borders {:top :border-unrelated :bottom :border-unrelated}})
(draw-box (text "WPRI" {:font-weight "bold" :font-size 24}) {:span 2})
(draw-box "VGEIN[5:0]" {:span 4})
(draw-box (text "WPRI" {:font-weight "bold" :font-size 24}) {:span 2})
(draw-box "HU")
(draw-box "SPVP" {:span 2})
(draw-box "SPV" {:span 2})
(draw-box "GVA" {:span 2})
(draw-box "VSBE" {:span 2})
(draw-box (text "WPRI" {:font-weight "bold" :font-size 24}) {:span 4})
(draw-box nil {:span 4 :borders {}})
(draw-box nil {:span 7 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "6" {:span 4 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "1" {:borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "5" {:span 4 :borders {}})
(draw-box nil {:span 4 :borders {}})
----

16
vendor/riscv/riscv-isa-manual/src/images/bytefield/htimedelta.edn vendored
View file

@ -1,16 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "63" {:span 31 :text-anchor "start" :borders {}})
(draw-box "0" {:borders {}})
(draw-box "htimedelta" {:font-size 20 :span 32})
(draw-box "64" {:span 32 :borders {}})
----

17
vendor/riscv/riscv-isa-manual/src/images/bytefield/htimedeltah.edn vendored
View file

@ -1,17 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 22}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 200)
(def right-margin 200)
(def boxes-per-row 32)
(draw-box "31" {:span 31 :text-anchor "start" :borders {}})
(draw-box "0" {:borders {}})
(draw-box "htimedelta" {:font-size 20 :span 32})
(draw-box "htimedeltah" {:font-size 20 :span 32})
(draw-box "32" {:span 32 :borders {}})
----

16
vendor/riscv/riscv-isa-manual/src/images/bytefield/htinstreg.edn vendored
View file

@ -1,16 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "HSXLEN-1" {:span 31 :text-anchor "start" :borders {}})
(draw-box "0" {:borders {}})
(draw-box "htinst" {:font-size 20 :span 32})
(draw-box "HSXLEN" {:span 32 :borders {}})
----

16
vendor/riscv/riscv-isa-manual/src/images/bytefield/htvalreg.edn vendored
View file

@ -1,16 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "HSXLEN-1" {:span 31 :text-anchor "start" :borders {}})
(draw-box "0" {:borders {}})
(draw-box "htval" {:font-size 20 :span 32})
(draw-box "HSXLEN" {:span 32 :borders {}})
----

37
vendor/riscv/riscv-isa-manual/src/images/bytefield/hvipreg-standard.edn vendored
View file

@ -1,37 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "15" {:span 4 :text-anchor "start" :borders {}})
(draw-box "11" {:span 4 :text-anchor "end" :borders {}})
(draw-box "10" {:span 4 :borders {}})
(draw-box "9" {:span 2 :text-anchor "start" :borders {}})
(draw-box "7" {:span 2 :text-anchor "end" :borders {}})
(draw-box "6" {:span 4 :borders {}})
(draw-box "5" {:span 2 :text-anchor "start" :borders {}})
(draw-box "3" {:span 2 :text-anchor "end" :borders {}})
(draw-box "2" {:span 4 :borders {}})
(draw-box "1" {:span 2 :text-anchor "start" :borders {}})
(draw-box "0" {:span 2 :text-anchor "end" :borders {}})
(draw-box "0" {:span 8})
(draw-box "VSEIP" {:span 4})
(draw-box "0" {:span 4})
(draw-box "VSTIP" {:span 4})
(draw-box "0" {:span 4})
(draw-box "VSSIP" {:span 4})
(draw-box "0" {:span 4})
(draw-box "5" {:span 8 :borders{}})
(draw-box "1" {:span 4 :borders {}})
(draw-box "3" {:span 4 :borders {}})
(draw-box "1" {:span 4 :borders {}})
(draw-box "3" {:span 4 :borders {}})
(draw-box "1" {:span 4 :borders {}})
(draw-box "2" {:span 4 :borders {}})
----

17
vendor/riscv/riscv-isa-manual/src/images/bytefield/hvipreg.edn vendored
View file

@ -1,17 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "HSXLEN-1" {:span 16 :text-anchor "start" :borders{}})
(draw-box "0" {:span 16 :text-anchor "end" :borders{}})
(draw-box "Virtual Interrupts" {:span 18 :text-anchor "end" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" { :font-weight "bold" :font-size 24}) {:span 14 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "HSXLEN" {:span 32 :borders {}})
----

56
vendor/riscv/riscv-isa-manual/src/images/bytefield/hypv-miereg-standard.edn vendored
View file

@ -1,56 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "15" {:borders {}})
(draw-box nil {:span 2 :borders {}})
(draw-box "13" {:borders {}})
(draw-box "12" {:span 3 :borders {}})
(draw-box "11" {:span 2 :borders {}})
(draw-box "10" {:span 3 :borders {}})
(draw-box "9" {:span 2 :borders {}})
(draw-box "8" {:span 2 :borders {}})
(draw-box "7" {:span 2 :borders {}})
(draw-box "6" {:span 2 :borders {}})
(draw-box "5" {:span 2 :borders {}})
(draw-box "4" {:span 2 :borders {}})
(draw-box "3" {:span 2 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "0" {:span 2 :borders {}})
(draw-box "0" {:span 4})
(draw-box "SGEIE" {:span 3})
(draw-box "MEIE" {:span 2})
(draw-box "VSEIE" {:span 3})
(draw-box "SEIE" {:span 2})
(draw-box "0" {:span 2})
(draw-box "MTIE" {:span 2})
(draw-box "VSTIE" {:span 2})
(draw-box "STIE" {:span 2})
(draw-box "0" {:span 2})
(draw-box "MSIE" {:span 2})
(draw-box "VSSIE" {:span 2})
(draw-box "SSIE" {:span 2})
(draw-box "0" {:span 2})
(draw-box "3" {:span 4 :borders {}})
(draw-box "1" {:span 3:borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
----

56
vendor/riscv/riscv-isa-manual/src/images/bytefield/hypv-mipreg-standard.edn vendored
View file

@ -1,56 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "15" {:borders {}})
(draw-box nil {:span 2 :borders {}})
(draw-box "13" {:borders {}})
(draw-box "12" {:span 3 :borders {}})
(draw-box "11" {:span 2 :borders {}})
(draw-box "10" {:span 3 :borders {}})
(draw-box "9" {:span 2 :borders {}})
(draw-box "8" {:span 2 :borders {}})
(draw-box "7" {:span 2 :borders {}})
(draw-box "6" {:span 2 :borders {}})
(draw-box "5" {:span 2 :borders {}})
(draw-box "4" {:span 2 :borders {}})
(draw-box "3" {:span 2 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "0" {:span 2 :borders {}})
(draw-box "0" {:span 4})
(draw-box "SGEIP" {:span 3})
(draw-box "MEIP" {:span 2})
(draw-box "VSEIP" {:span 3})
(draw-box "SEIP" {:span 2})
(draw-box "0" {:span 2})
(draw-box "MTIP" {:span 2})
(draw-box "VSTIP" {:span 2})
(draw-box "STIP" {:span 2})
(draw-box "0" {:span 2})
(draw-box "MSIP" {:span 2})
(draw-box "VSSIP" {:span 2})
(draw-box "SSIP" {:span 2})
(draw-box "0" {:span 2})
(draw-box "3" {:span 4 :borders {}})
(draw-box "1" {:span 3:borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
----

129
vendor/riscv/riscv-isa-manual/src/images/bytefield/hypv-mstatus.edn vendored
View file

@ -1,129 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "MSXLEN-1" {:span 3 :borders {}})
(draw-box "MXLEN-2" {:span 4 :text-anchor "start" :borders {}})
(draw-box "40" {:span 4 :text-anchor "end" :borders {}})
(draw-box "39" {:span 3 :borders {}})
(draw-box "38" {:span 3 :borders {}})
(draw-box "37" {:span 3 :borders {}})
(draw-box "36" {:span 3 :borders {}})
(draw-box "35" {:span 2 :borders {}})
(draw-box "34" {:span 2 :borders {}})
(draw-box "33" {:span 2 :borders {}})
(draw-box "32" {:span 2 :borders {}})
(draw-box nil {:borders {}})
(draw-box "SD" {:span 3})
(draw-box (text "WPRI" {:font-weight "bold" :font-size 24}) {:span 8})
(draw-box "MPV" {:span 3})
(draw-box "GVA" {:span 3})
(draw-box "MBE" {:span 3})
(draw-box "SBE" {:span 3})
(draw-box "SXL[1:0]" {:span 4})
(draw-box "UXL[1:0]" {:span 4})
(draw-box nil {:borders {:top :border-unrelated :bottom :border-unrelated}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "MXLEN-41" {:span 8 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "2" {:span 4 :borders {}})
(draw-box "2" {:span 4 :borders {}})
(draw-box nil {:borders {}})
(draw-box nil {:span 32 :borders {}})
(draw-box nil {:borders {}})
(draw-box "31" {:span 3 :text-align "start" :borders {}})
(draw-box "23" {:span 3 :text-align "end" :borders {}})
(draw-box "22" {:span 3 :borders {}})
(draw-box "21" {:span 3 :borders {}})
(draw-box "20" {:span 3 :borders {}})
(draw-box "19" {:span 3 :borders {}})
(draw-box "18" {:span 3 :borders {}})
(draw-box "17" {:span 3 :borders {}})
(draw-box "16" {:span 2 :borders {}})
(draw-box "15" {:borders {}})
(draw-box "14" {:span 2 :borders {}})
(draw-box "13" {:borders {}})
(draw-box nil {:borders {}})
(draw-box nil {:borders {:top :border-unrelated :bottom :border-unrelated}})
(draw-box (text "WPRI" {:font-weight "bold" :font-size 24}) {:span 6})
(draw-box "TSR" {:span 3})
(draw-box "TW" {:span 3})
(draw-box "TVM" {:span 3})
(draw-box "MXR" {:span 3})
(draw-box "SUM" {:span 3})
(draw-box "MPRV" {:span 3})
(draw-box "XS[1:0]" {:span 3})
(draw-box "FS[1:0]" {:span 3})
(draw-box nil {:borders {:top :border-unrelated :bottom :border-unrelated}})
(draw-box nil {:borders {}})
(draw-box "9" {:span 6 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "2" {:span 3 :borders {}})
(draw-box "2" {:span 3 :borders {}})
(draw-box nil {:borders {}})
(draw-box nil {:span 32 :borders {}})
(draw-box nil {:borders {}})
(draw-box "12" {:borders {}})
(draw-box nil {:borders {}})
(draw-box "11" {:borders {}})
(draw-box "10" {:borders {}})
(draw-box nil {:borders {}})
(draw-box "9" {:borders {}})
(draw-box "8" {:span 2 :borders {}})
(draw-box "7" {:span 3 :borders {}})
(draw-box "6" {:span 2 :borders {}})
(draw-box "5" {:span 3 :borders {}})
(draw-box "4" {:span 3 :borders {}})
(draw-box "3" {:span 3 :borders {}})
(draw-box "2" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "0" {:span 3 :borders {}})
(draw-box nil {:borders {:top :border-unrelated :bottom :border-unrelated}})
(draw-box "MPP[1:0]" {:span 3})
(draw-box "VS[1:0]" {:span 3})
(draw-box "SPP" {:span 2})
(draw-box "MPIE" {:span 3})
(draw-box "UBE" {:span 2})
(draw-box "SPIE" {:span 3})
(draw-box (text "WPRI" {:font-weight "bold" :font-size 24}) {:span 3})
(draw-box "MIE" {:span 3})
(draw-box (text "WPRI" {:font-weight "bold" :font-size 24}) {:span 3})
(draw-box "SIE" {:span 3})
(draw-box (text "WPRI" {:font-weight "bold" :font-size 24}) {:span 3})
(draw-box nil {:borders {}})
(draw-box "2" {:span 3 :borders {}})
(draw-box "2" {:span 3 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
----

32
vendor/riscv/riscv-isa-manual/src/images/bytefield/hypv-mstatush.edn vendored
View file

@ -1,32 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "31" {:span 8 :text-anchor "start" :borders {}})
(draw-box "8" {:span 8 :text-anchor "end" :borders {}})
(draw-box "7" {:span 3 :borders {}})
(draw-box "6" {:span 3 :borders {}})
(draw-box "5" {:span 3 :borders {}})
(draw-box "4" {:span 3 :borders {}})
(draw-box "3" {:span 2 :text-anchor "start" :borders {}})
(draw-box "0" {:span 2 :text-anchor "end" :borders {}})
(draw-box (text "WPRI" {:font-weight "bold" :font-size 24}) {:span 16})
(draw-box "MPV" {:span 3})
(draw-box "GVA" {:span 3})
(draw-box "MBE" {:span 3})
(draw-box "SBE" {:span 3})
(draw-box (text "WPRI" {:font-weight "bold" :font-size 24}) {:span 4})
(draw-box "24" {:span 16 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "4" {:span 4 :borders {}})
----

14
vendor/riscv/riscv-isa-manual/src/images/bytefield/marchid.adoc vendored
View file

@ -1,14 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback"}])
(def row-height 35 )
(def row-header-fn nil)
(def left-margin 100)
(def right-margin 100)
(def boxes-per-row 32)
(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" """" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1" ""])})
(draw-box "Architecture ID" {:span 32 :vertical-align "middle"})
(draw-box "MXLEN" {:span 32 :borders {}})
----

20
vendor/riscv/riscv-isa-manual/src/images/bytefield/mcausereg.adoc vendored
View file

@ -1,20 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 200)
(def right-margin 200)
(def boxes-per-row 32)
(draw-box "MXLEN-1" {:span 4 :borders {}})
(draw-box "MXLEN-2" {:span 14 :borders {} :text-anchor "start"})
(draw-box "0" {:span 14 :borders {} :text-anchor "end"})
(draw-box "Interrupt" {:span 4})
(draw-box "Exception Code " {:span 15 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WLRL)" {:font-weight "bold"}) {:span 13 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "1" {:span 4 :borders {}})
(draw-box "MXLEN-1" {:font-size 24 :span 28 :borders {}})
----

13
vendor/riscv/riscv-isa-manual/src/images/bytefield/mconfigptrreg.adoc vendored
View file

@ -1,13 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 200)
(def right-margin 200)
(def boxes-per-row 32)
(draw-column-headers {:height 26 :font-size 24 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1" ""])})
(draw-box "mconfigptr" {:span 32})
(draw-box "MXLEN" {:font-size 24 :span 32 :borders {}})
----

17
vendor/riscv/riscv-isa-manual/src/images/bytefield/medeleg.adoc vendored
View file

@ -1,17 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 35)
(def row-header-fn nil)
(def left-margin 100)
(def right-margin 100)
(def boxes-per-row 32)
(draw-box "MXLEN-1" {:span 16 :text-anchor "start" :borders {}})
(draw-box "0" {:span 16 :text-anchor "end" :borders {}})
(draw-box "Synchronous Exceptions" {:font-size 18 :span 18 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold"}) {:font-size 18 :span 14 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "MXLEN" {:font-size 24 :span 32 :borders {}})
----

26
vendor/riscv/riscv-isa-manual/src/images/bytefield/menvcfgreg.adoc vendored
View file

@ -1,26 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback"}])
(def row-height 45)
(def row-header-fn nil)
(def boxes-per-row 32)
(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "1" "3" "4" "5" "6" "" "7" "" "8" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "61" "" "62" "" "63"])})
(draw-box "STCE" {:span 2})
(draw-box "PBMTE" {:span 2})
(draw-box (text "WPRI" {:font-weight "bold"}) {:span 18})
(draw-box "CBZE" {:span 2})
(draw-box "CBCFE" {:span 2})
(draw-box "CBIE" {:span 2})
(draw-box "WPRI" {:span 2})
(draw-box "FIOM" {:span 2})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "54" {:span 18 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "3" {:span 2 :borders {}})
(draw-box "1" {:span 2 :borders {}})
----

15
vendor/riscv/riscv-isa-manual/src/images/bytefield/mepcreg.adoc vendored
View file

@ -1,15 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 100)
(def right-margin 100)
(def boxes-per-row 32)
(draw-box "MXLEN-1" {:span 16 :text-anchor "start" :borders {}})
(draw-box "0" {:span 16 :text-anchor "end" :borders {}})
(draw-box "mepc" {:span 32})
(draw-box "MXLEN" {:font-size 24 :span 32 :borders {}})
----

14
vendor/riscv/riscv-isa-manual/src/images/bytefield/mhartid.adoc vendored
View file

@ -1,14 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback"}])
(def row-height 35 )
(def row-header-fn nil)
(def left-margin 100)
(def right-margin 100)
(def boxes-per-row 32)
(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" """" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1" ""])})
(draw-box "Hart ID" {:span 32 :vertical-align "middle"})
(draw-box "MXLEN" {:span 32 :borders {}})
----

17
vendor/riscv/riscv-isa-manual/src/images/bytefield/mideleg.adoc vendored
View file

@ -1,17 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 100)
(def right-margin 100)
(def boxes-per-row 32)
(draw-box "MXLEN-1" {:span 16 :text-anchor "start" :borders {}})
(draw-box "0" {:span 16 :text-anchor "end" :borders {}})
(draw-box "Interrupts" {:font-size 18 :span 17 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold"}) {:font-size 18 :span 15 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "MXLEN" {:font-size 24 :span 32 :borders {}})
----

38
vendor/riscv/riscv-isa-manual/src/images/bytefield/miereg-standard.adoc vendored
View file

@ -1,38 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 12}])
(def row-height 30 )
(def row-header-fn nil)
(def left-margin 100)
(def right-margin 100)
(def boxes-per-row 16)
(draw-column-headers {:labels (reverse ["0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "" "" "15"])})
(draw-box "0" {:span 4})
(draw-box "MEIE" {:span 1})
(draw-box "0" {:span 1})
(draw-box "SEIE" {:span 1})
(draw-box "0" {:span 1})
(draw-box "MTIE" {:span 1})
(draw-box "0" {:span 1})
(draw-box "STIE" {:span 1})
(draw-box "0" {:span 1})
(draw-box "MSIE" {:span 1})
(draw-box "0" {:span 1})
(draw-box "SSIE" {:span 1})
(draw-box "0" {:span 1})
(draw-box "4" {:span 4 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
----

14
vendor/riscv/riscv-isa-manual/src/images/bytefield/mimpid.adoc vendored
View file

@ -1,14 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback"}])
(def row-height 35 )
(def row-header-fn nil)
(def left-margin 100)
(def right-margin 100)
(def boxes-per-row 32)
(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" """" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1" ""])})
(draw-box "Implementation" {:span 32})
(draw-box "MXLEN" {:span 32 :borders {}})
----

38
vendor/riscv/riscv-isa-manual/src/images/bytefield/mipreg-standard.adoc vendored
View file

@ -1,38 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 12}])
(def row-height 30 )
(def row-header-fn nil)
(def left-margin 100)
(def right-margin 100)
(def boxes-per-row 16)
(draw-column-headers {:labels (reverse ["0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "" "" "15"])})
(draw-box "0" {:span 4})
(draw-box "MEIP" {:span 1})
(draw-box "0" {:span 1})
(draw-box "SEIP" {:span 1})
(draw-box "0" {:span 1})
(draw-box "MTIP" {:span 1})
(draw-box "0" {:span 1})
(draw-box "STIP" {:span 1})
(draw-box "0" {:span 1})
(draw-box "MSIP" {:span 1})
(draw-box "0" {:span 1})
(draw-box "SSIP" {:span 1})
(draw-box "0" {:span 1})
(draw-box "4" {:span 4 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
----

27
vendor/riscv/riscv-isa-manual/src/images/bytefield/misareg.edn vendored
View file

@ -1,27 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 16}])
(def row-height 30 )
(def row-header-fn nil)
(def left-margin 100)
(def right-margin 100)
(def boxes-per-row 32)
(draw-box "MXLEN-1" {:span 6 :borders {}})
(draw-box "MXLEN-2" {:span 6 :borders {}})
(draw-box "MXLEN-3" {:span 5 :text-anchor "start" :borders {}})
(draw-box "26" {:borders {}})
(draw-box "25" {:span 7 :text-anchor "start" :borders {}})
(draw-box "0" {:span 7 :text-anchor "end" :borders {}})
(draw-box "MXL[1:0]" {:span 6 :text-anchor "end" :borders {:left :border-unrelated :top :border-unrelated :bottom :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold"}) {:span 6 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated}})
(draw-box "0" {:span 3 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold"}) {:span 3 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "Extensions[25:0]" {:span 7 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold"}) {:span 7 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "2" {:span 12 :borders {}})
(draw-box "MXLEN-28" {:span 6 :borders {}})
(draw-box "26" {:span 14 :borders {}})
----

16
vendor/riscv/riscv-isa-manual/src/images/bytefield/mncause.edn vendored
View file

@ -1,16 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-column-headers {:height 24 :font-size 24 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-2" "" "" "" "MXLEN-1" ""])})
(draw-box "1" {:span 4})
(draw-box (text "NMI Cause" {:font-size 24}) {:span 14 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 14 :text-anchor "start" :borders {:top :border-unrelated :right :border-unrelated :bottom :border-unrelated}})
(draw-box "1" {:span 4 :borders {}})
(draw-box "MXLEN-1" {:font-size 24 :span 28 :borders {}})
----

14
vendor/riscv/riscv-isa-manual/src/images/bytefield/mnepc.edn vendored
View file

@ -1,14 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-column-headers {:height 24 :font-size 24 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1" ""])})
(draw-box (text "mnepc " {:font-size 24}) {:span 16 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)"{:font-weight "bold" :font-size 24}) {:span 16 :text-anchor "start" :borders {:top :border-unrelated :right :border-unrelated :bottom :border-unrelated}})
(draw-box "MXLEN" {:span 32 :borders {}})
----

13
vendor/riscv/riscv-isa-manual/src/images/bytefield/mnscratch.adoc vendored
View file

@ -1,13 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-column-headers {:height 24 :font-size 24 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1" ""])})
(draw-box (text "mnscratch" {:font-size 24}) {:span 32})
(draw-box "MXLEN" {:font-size 24 :span 32 :borders {}})
----

29
vendor/riscv/riscv-isa-manual/src/images/bytefield/mnstatus.edn vendored
View file

@ -1,29 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-column-headers {:height 24 :font-size 24 :labels (reverse ["0" "" "" "2" "" "3" "4" "" "" "6" "" "" "" "7" "" "" "8" "" "" "10" "11" "" "" "12" "13" "" "" "" "" "" "MXLEN-1" ""])})
(draw-box (text "Reserved" {:font-style "italic" :font-size 24}) {:span 8})
(draw-box (text "MNPP" {:font-size 24}) {:span 2 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 20}) {:span 2 :text-anchor "start" :borders {:top :border-unrelated :right :border-unrelated :bottom :border-unrelated}})
(draw-box (text "Reserved" {:font-style "italic" :font-size 24}) {:span 4})
(draw-box (text "MNPV" {:font-size 24}) {:span 3 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 3 :text-anchor "start" :borders {:top :border-unrelated :right :border-unrelated :bottom :border-unrelated}})
(draw-box (text "Reserved" {:font-style "italic" :font-size 24}) {:span 4})
(draw-box "NMIE" {:span 2})
(draw-box (text "Reserved" {:font-style "italic" :font-size 24}) {:span 4})
(draw-box "MXLEN-13" {:span 8 :borders {}})
(draw-box "2" {:span 4 :borders {}})
(draw-box "3" {:span 4 :borders {}})
(draw-box "1" {:span 6 :borders {}})
(draw-box "3" {:span 4 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "3" {:span 4 :borders {}})
----

16
vendor/riscv/riscv-isa-manual/src/images/bytefield/mscratch.adoc vendored
View file

@ -1,16 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 100)
(def right-margin 100)
(def boxes-per-row 32)
(draw-box "MXLEN-1" {:span 16 :text-anchor "start" :borders {}})
(draw-box "0" {:span 16 :text-anchor "end" :borders {}})
(draw-box "mscratch" {:font-size 18 :span 32})
(draw-box "MXLEN" {:font-size 24 :span 32 :borders {}})
----

24
vendor/riscv/riscv-isa-manual/src/images/bytefield/mseccfg.adoc vendored
View file

@ -1,24 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback"}])
(def row-height 45)
(def row-header-fn nil)
(def boxes-per-row 32)
(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["" "0" "" "1" "" "2" "" "3" "" "7" "" "8" "" "" "9" "" "10" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "63"])})
(draw-box (text "WPRI" {:font-weight "bold"}) {:span 16})
(draw-box "SSEED" {:span 3})
(draw-box "USEED" {:span 3})
(draw-box (text "WPRI" {:font-weight "bold"}) {:span 3})
(draw-box "RLB" {:span 2})
(draw-box "MMWP" {:span 3})
(draw-box "MML" {:span 2})
(draw-box "54" {:span 16 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "5" {:span 3 :borders {}})
(draw-box "1" {:span 2 :borders {}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "1" {:span 2 :borders {}})
----

20
vendor/riscv/riscv-isa-manual/src/images/bytefield/mstatushreg.adoc vendored
View file

@ -1,20 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-size 14 :font-family "M+ 1p Fallback" :vertical-align "middle"}])
(def row-height 45 )
(def row-header-fn nil)
(def left-margin 0)
(def right-margin 0)
(def boxes-per-row 32)
(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "3" "4" "5" "6" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "31"])})
(draw-box (text "WPRI" {:font-weight "bold"}) {:span 26})
(draw-box "MBE" {:span 1})
(draw-box "SBE" {:span 1})
(draw-box (text "WPRI" {:font-weight "bold"}) {:span 4})
(draw-box "26" {:span 26 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "4" {:span 4 :borders {}})
----

54
vendor/riscv/riscv-isa-manual/src/images/bytefield/mstatusreg-rv32.adoc vendored
View file

@ -1,54 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-size 14 :font-family "M+ 1p Fallback" :vertical-align "middle"}])
(def row-height 45 )
(def row-header-fn nil)
(def left-margin 0)
(def right-margin 0)
(def boxes-per-row 32)
(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "20" "21" "22" "23" "" "" "" "" "" "" "30" "31"])})
(draw-box "SD" {:span 1})
(draw-box (text "WPRI" {:font-weight "bold"}) {:span 8})
(draw-box "TSR" {:span 1})
(draw-box "TW" {:span 1})
(draw-box "TVM" {:span 1})
(draw-box "MXR" {:span 1})
(draw-box "SUM" {:span 1})
(draw-box "MPRV" {:span 1})
(draw-box "XS[1:0]" {:span 2})
(draw-box "FS[1:0]" {:span 2})
(draw-box "MPP[1:0]" {:span 2})
(draw-box "VS[1:0]" {:span 2})
(draw-box "SPP" {:span 1})
(draw-box "MPIE" {:span 1})
(draw-box "UBE" {:span 1})
(draw-box "SPIE" {:span 1})
(draw-box (text "WPRI" {:font-weight "bold"}) {:span 1})
(draw-box "MIE" {:span 1})
(draw-box (text "WPRI" {:font-weight "bold"}) {:span 1})
(draw-box "SIE" {:span 1})
(draw-box (text "WPRI" {:font-weight "bold"}) {:span 1})
(draw-box "1" {:span 1 :borders {}})
(draw-box "8" {:span 8 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
----

26
vendor/riscv/riscv-isa-manual/src/images/bytefield/mstatusreg.adoc vendored
View file

@ -1,26 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-size 14 :font-family "M+ 1p Fallback" :vertical-align "middle"}])
(def row-height 45 )
(def row-header-fn nil)
(def left-margin 0)
(def right-margin 0)
(def boxes-per-row 33)
(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["" "32" "33" "34" "35" "36" "37" "38" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "62" "63"])})
(draw-box "SD" {:span 1})
(draw-box (text "WPRI" {:font-weight "bold"}) {:span 25})
(draw-box "MBE" {:span 1})
(draw-box "SBE" {:span 1})
(draw-box "SXL[1:0]" {:span 2})
(draw-box "UXL[1:0]" {:span 2})
(draw-box "" {:span 1 :borders {:top :border-unrelated :bottom :border-unrelated}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "25" {:span 25 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "" {:span 1 :borders {}})
----

54
vendor/riscv/riscv-isa-manual/src/images/bytefield/mstatusreg2.adoc vendored
View file

@ -1,54 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-size 14 :font-family "M+ 1p Fallback" :vertical-align "middle"}])
(def row-height 45 )
(def row-header-fn nil)
(def left-margin 0)
(def right-margin 0)
(def boxes-per-row 33)
(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "20" "21" "22" "23" "" "" "" "" "" "" "30" "31" ""])})
(draw-box "" {:span 1 :borders{:top :border-unrelated :bottom :border-unrelated}})
(draw-box (text "WPRI" {:font-eight "bold"}) {:span 9})
(draw-box "TSR" {:span 1})
(draw-box "TW" {:span 1})
(draw-box "TVM" {:span 1})
(draw-box "MXR" {:span 1})
(draw-box "SUM" {:span 1})
(draw-box "MPRV" {:span 1})
(draw-box "XS[1:0]" {:span 2})
(draw-box "FS[1:0]" {:span 2})
(draw-box "MPP[1:0]" {:span 2})
(draw-box "VS[1:0]" {:span 2})
(draw-box "SPP" {:span 1})
(draw-box "MPIE" {:span 1})
(draw-box "UBE" {:span 1})
(draw-box "SPIE" {:span 1})
(draw-box (text "WPRI" {:font-weight "bold"}) {:span 1})
(draw-box "MIE" {:span 1})
(draw-box (text "WPRI" {:font-weight "bold"}) {:span 1})
(draw-box "SIE" {:span 1})
(draw-box (text "WPRI" {:font-weight "bold"}) {:span 1})
(draw-box "" {:span 1 :borders {}})
(draw-box "9" {:span 9 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "2" {:span 2 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
(draw-box "1" {:span 1 :borders {}})
----

13
vendor/riscv/riscv-isa-manual/src/images/bytefield/mtime.adoc vendored
View file

@ -1,13 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 200)
(def right-margin 200)
(def boxes-per-row 32)
(draw-column-headers {:height 24 :font-size 24 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "63"])})
(draw-box "mtime" {:span 32})
(draw-box "64" {:font-size 24 :span 32 :borders {}})
----

13
vendor/riscv/riscv-isa-manual/src/images/bytefield/mtimecmp.adoc vendored
View file

@ -1,13 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 200)
(def right-margin 200)
(def boxes-per-row 32)
(draw-column-headers {:height 26 :font-size 24 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "63"])})
(draw-box "mtimecmp" {:span 32})
(draw-box "64" {:font-size 24 :span 32 :borders {}})
----

14
vendor/riscv/riscv-isa-manual/src/images/bytefield/mtinstreg.edn vendored
View file

@ -1,14 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "MXLEN-1" {:span 16 :text-anchor "start" :borders {}})
(draw-box "0" {:span 16 :text-anchor "end" :borders {}})
(draw-box "mtinst" {:span 32})
(draw-box "MXLEN" {:span 32 :borders {}})
----

14
vendor/riscv/riscv-isa-manual/src/images/bytefield/mtval2reg.edn vendored
View file

@ -1,14 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "MXLEN-1" {:span 16 :text-anchor "start" :borders {}})
(draw-box "0" {:span 16 :text-anchor "end" :borders {}})
(draw-box "mtval2" {:span 32})
(draw-box "MXLEN" {:span 32 :borders {}})
----

13
vendor/riscv/riscv-isa-manual/src/images/bytefield/mtvalreg.adoc vendored
View file

@ -1,13 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 200)
(def right-margin 200)
(def boxes-per-row 32)
(draw-column-headers {:height 26 :font-size 24 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1" ""])})
(draw-box "mtval" {:span 32})
(draw-box "MXLEN" {:font-size 24 :span 32 :borders {}})
----

18
vendor/riscv/riscv-isa-manual/src/images/bytefield/mtvec.adoc vendored
View file

@ -1,18 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback"}])
(def row-height 35 )
(def row-header-fn nil)
(def left-margin 100)
(def right-margin 100)
(def boxes-per-row 32)
(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "1" "2" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1" ""])})
(draw-box "BASE[MXLEN-1:2]" {:span 12 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold"}) {:span 12 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "MODE" {:span 4 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold"}) {:span 4 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "MXLEN-2" {:span 24 :borders {}})
(draw-box "2" {:span 8 :borders {}})
----

15
vendor/riscv/riscv-isa-manual/src/images/bytefield/mvendorid.adoc vendored
View file

@ -1,15 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback"}])
(def row-height 35 )
(def row-header-fn nil)
(def left-margin 100)
(def right-margin 100)
(def boxes-per-row 32)
(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "6" "7" """" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "31"])})
(draw-box "Bank" {:span 25 :vertical-align "middle"})
(draw-box "Offset" {:span 7})
(draw-box "25" {:span 25 :borders {}})
(draw-box "7" {:span 7 :borders{}})
----

79
vendor/riscv/riscv-isa-manual/src/images/bytefield/pmp-rv32.adoc vendored
View file

@ -1,79 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback"}])
(def row-header-fn nil)
(def boxes-per-row 20)
(def left-margin 200)
(def right-margin 200)
(draw-box "31" {:span 2 :text-anchor "start" :borders {}})
(draw-box "24" {:span 2 :text-anchor "end" :borders {}})
(draw-box "23" {:span 2 :text-anchor "start" :borders {}})
(draw-box "16" {:span 2 :text-anchor "end" :borders {}})
(draw-box "15" {:span 2 :text-anchor "start" :borders {}})
(draw-box "8" {:span 2 :text-anchor "end" :borders {}})
(draw-box "7" {:span 2 :text-anchor "start" :borders {}})
(draw-box "0" {:span 2 :text-anchor "end" :borders {}})
(draw-box nil {:span 4 :text-anchor "start" :borders {}})
(draw-box "pmp3cfg" {:span 4})
(draw-box "pmp2cfg" {:span 4})
(draw-box "pmp1cfg" {:span 4})
(draw-box "pmp0cfg" {:span 4})
(draw-box "pmpcfg0" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box nil {:span 4 :borders {}})
(draw-box "31" {:span 2 :text-anchor "start" :borders {}})
(draw-box "24" {:span 2 :text-anchor "end" :borders {}})
(draw-box "23" {:span 2 :text-anchor "start" :borders {}})
(draw-box "16" {:span 2 :text-anchor "end" :borders {}})
(draw-box "15" {:span 2 :text-anchor "start" :borders {}})
(draw-box "8" {:span 2 :text-anchor "end" :borders {}})
(draw-box "7" {:span 2 :text-anchor "start" :borders {}})
(draw-box "0" {:span 2 :text-anchor "end" :borders {}})
(draw-box nil {:span 4 :text-anchor "start" :borders {}})
(draw-box "pmp7cfg" {:span 4})
(draw-box "pmp6cfg" {:span 4})
(draw-box "pmp5cfg" {:span 4})
(draw-box "pmp4cfg" {:span 4})
(draw-box "pmpcfg1" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box nil {:span 4 :borders {}})
(draw-box nil {:span 20 :borders {}})
(draw-box nil {:span 8 :borders {}})
(draw-box "⋮" {:span 12 :text-anchor "start" :borders {}})
(draw-box nil {:span 20 :borders {}})
(draw-box "31" {:span 2 :text-anchor "start" :borders {}})
(draw-box "24" {:span 2 :text-anchor "end" :borders {}})
(draw-box "23" {:span 2 :text-anchor "start" :borders {}})
(draw-box "16" {:span 2 :text-anchor "end" :borders {}})
(draw-box "15" {:span 2 :text-anchor "start" :borders {}})
(draw-box "8" {:span 2 :text-anchor "end" :borders {}})
(draw-box "7" {:span 2 :text-anchor "start" :borders {}})
(draw-box "0" {:span 2 :text-anchor "end" :borders {}})
(draw-box nil {:span 4 :text-anchor "start" :borders {}})
(draw-box "pmp63cfg" {:span 4})
(draw-box "pmp62cfg" {:span 4})
(draw-box "pmp61cfg" {:span 4})
(draw-box "pmp60cfg" {:span 4})
(draw-box "pmpcfg15" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box nil {:span 4 :borders {}})
----

131
vendor/riscv/riscv-isa-manual/src/images/bytefield/pmp-rv64.adoc vendored
View file

@ -1,131 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 22}])
(def row-header-fn nil)
(def boxes-per-row 40)
(def left-margin 200)
(def right-margin 200)
(def row-height 50)
(draw-box "63" {:span 2 :text-anchor "start" :borders {}})
(draw-box "56" {:span 2 :text-anchor "end" :borders {}})
(draw-box "55" {:span 2 :text-anchor "start" :borders {}})
(draw-box "48" {:span 2 :text-anchor "end" :borders {}})
(draw-box "47" {:span 2 :text-anchor "start" :borders {}})
(draw-box "40" {:span 2 :text-anchor "end" :borders {}})
(draw-box "39" {:span 2 :text-anchor "start" :borders {}})
(draw-box "32" {:span 2 :text-anchor "end" :borders {}})
(draw-box "31" {:span 2 :text-anchor "start" :borders {}})
(draw-box "24" {:span 2 :text-anchor "end" :borders {}})
(draw-box "23" {:span 2 :text-anchor "start" :borders {}})
(draw-box "16" {:span 2 :text-anchor "end" :borders {}})
(draw-box "15" {:span 2 :text-anchor "start" :borders {}})
(draw-box "8" {:span 2 :text-anchor "end" :borders {}})
(draw-box "7" {:span 2 :text-anchor "start" :borders {}})
(draw-box "0" {:span 2 :text-anchor "end" :borders {}})
(draw-box nil {:span 8 :text-anchor "start" :borders {}})
(draw-box "pmp7cfg" {:span 4})
(draw-box "pmp6cfg" {:span 4})
(draw-box "pmp5cfg" {:span 4})
(draw-box "pmp4cfg" {:span 4})
(draw-box "pmp3cfg" {:span 4})
(draw-box "pmp2cfg" {:span 4})
(draw-box "pmp1cfg" {:span 4})
(draw-box "pmp0cfg" {:span 4})
(draw-box "pmpcfg0" {:span 4 :borders {}})
(draw-box nil {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box nil {:span 8 :borders {}})
(draw-box "63" {:span 2 :text-anchor "start" :borders {}})
(draw-box "56" {:span 2 :text-anchor "end" :borders {}})
(draw-box "55" {:span 2 :text-anchor "start" :borders {}})
(draw-box "48" {:span 2 :text-anchor "end" :borders {}})
(draw-box "47" {:span 2 :text-anchor "start" :borders {}})
(draw-box "40" {:span 2 :text-anchor "end" :borders {}})
(draw-box "39" {:span 2 :text-anchor "start" :borders {}})
(draw-box "32" {:span 2 :text-anchor "end" :borders {}})
(draw-box "31" {:span 2 :text-anchor "start" :borders {}})
(draw-box "24" {:span 2 :text-anchor "end" :borders {}})
(draw-box "23" {:span 2 :text-anchor "start" :borders {}})
(draw-box "16" {:span 2 :text-anchor "end" :borders {}})
(draw-box "15" {:span 2 :text-anchor "start" :borders {}})
(draw-box "8" {:span 2 :text-anchor "end" :borders {}})
(draw-box "7" {:span 2 :text-anchor "start" :borders {}})
(draw-box "0" {:span 2 :text-anchor "end" :borders {}})
(draw-box nil {:span 8 :text-anchor "start" :borders {}})
(draw-box "pmp15cfg" {:span 4})
(draw-box "pmp14cfg" {:span 4})
(draw-box "pmp13cfg" {:span 4})
(draw-box "pmp12cfg" {:span 4})
(draw-box "pmp11cfg" {:span 4})
(draw-box "pmp10cfg" {:span 4})
(draw-box "pmp9cfg" {:span 4})
(draw-box "pmp8cfg" {:span 4})
(draw-box "pmpcfg2" {:span 4 :borders {}})
(draw-box nil {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box nil {:span 8 :borders {}})
(draw-box nil {:span 40 :borders {}})
(draw-box nil {:span 16 :borders {}})
(draw-box "⋮" {:span 24 :text-anchor "start" :borders {}})
(draw-box nil {:span 40 :borders {}})
(draw-box "63" {:span 2 :text-anchor "start" :borders {}})
(draw-box "56" {:span 2 :text-anchor "end" :borders {}})
(draw-box "55" {:span 2 :text-anchor "start" :borders {}})
(draw-box "48" {:span 2 :text-anchor "end" :borders {}})
(draw-box "47" {:span 2 :text-anchor "start" :borders {}})
(draw-box "40" {:span 2 :text-anchor "end" :borders {}})
(draw-box "39" {:span 2 :text-anchor "start" :borders {}})
(draw-box "32" {:span 2 :text-anchor "end" :borders {}})
(draw-box "31" {:span 2 :text-anchor "start" :borders {}})
(draw-box "24" {:span 2 :text-anchor "end" :borders {}})
(draw-box "23" {:span 2 :text-anchor "start" :borders {}})
(draw-box "16" {:span 2 :text-anchor "end" :borders {}})
(draw-box "15" {:span 2 :text-anchor "start" :borders {}})
(draw-box "8" {:span 2 :text-anchor "end" :borders {}})
(draw-box "7" {:span 2 :text-anchor "start" :borders {}})
(draw-box "0" {:span 2 :text-anchor "end" :borders {}})
(draw-box nil {:span 8 :text-anchor "start" :borders {}})
(draw-box "pmp63cfg" {:span 4})
(draw-box "pmp62cfg" {:span 4})
(draw-box "pmp61cfg" {:span 4})
(draw-box "pmp60cfg" {:span 4})
(draw-box "pmp59cfg" {:span 4})
(draw-box "pmp58cfg" {:span 4})
(draw-box "pmp57cfg" {:span 4})
(draw-box "pmp56cfg" {:span 4})
(draw-box "pmpcfg14" {:span 4 :borders {}})
(draw-box nil {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box "8" {:span 4 :borders {}})
(draw-box nil {:span 8 :borders {}})
----

15
vendor/riscv/riscv-isa-manual/src/images/bytefield/pmpaddr-rv32.adoc vendored
View file

@ -1,15 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 200)
(def right-margin 200)
(def boxes-per-row 32)
(draw-column-headers {:height 24 :font-size 24 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "31"])})
(draw-box "address[33:2]" {:span 16 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-size 24 :font-weight "bold"}) {:span 16 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "32" {:font-size 24 :span 32 :borders {}})
----

18
vendor/riscv/riscv-isa-manual/src/images/bytefield/pmpaddr-rv64.adoc vendored
View file

@ -1,18 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 50 )
(def row-header-fn nil)
(def left-margin 200)
(def right-margin 200)
(def boxes-per-row 32)
(draw-column-headers {:height 24 :font-size 24 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "53" "" "" "" "" "54" "" "" "63"])})
(draw-box "0" {:span 4 :text-anchor "end" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-size 24 :font-weight "bold"}) {:span 4 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "address[55:2]" {:span 12 :text-anchor "end" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-size 24 :font-weight "bold"}) {:span 12 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "10" {:font-size 24 :span 8 :borders {}})
(draw-box "54" {:font-size 24 :span 24 :borders {}})
----

38
vendor/riscv/riscv-isa-manual/src/images/bytefield/pmpcfg.adoc vendored
View file

@ -1,38 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 100)
(def right-margin 100)
(def boxes-per-row 32)
(draw-box "7" {:span 5 :borders {}})
(draw-box "6" {:span 3 :text-anchor "start" :borders {}})
(draw-box "5" {:span 3 :text-anchor "end" :borders {}})
(draw-box "4" {:span 3 :text-anchor "left" :borders {}})
(draw-box "3" {:span 3 :text-anchor "end" :borders {}})
(draw-box "2" {:span 5 :borders {}})
(draw-box "1" {:span 5 :borders {}})
(draw-box "0" {:span 5 :borders {}})
(draw-box "L " {:span 2 :text-anchor "end" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 3 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "0 " {:span 3 :text-anchor "end" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 3 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "A " {:span 3 :text-anchor "end" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 3 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "X " {:span 2 :text-anchor "end" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 3 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "W " {:span 2 :text-anchor "end" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 3 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "R " {:span 2 :text-anchor "end" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 3 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "1" {:span 5 :borders {}})
(draw-box "2" {:span 6 :borders {}})
(draw-box "2" {:span 6 :borders {}})
(draw-box "1" {:span 5 :borders {}})
(draw-box "1" {:span 5 :borders {}})
(draw-box "1" {:span 5 :borders {}})
----

267
vendor/riscv/riscv-isa-manual/src/images/bytefield/priv-instr-set.edn vendored
View file

@ -1,267 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40)
(def row-header-fn nil)
(def boxes-per-row 32)
(draw-box "31" {:span 4 :text-anchor "start" :borders{}})
(draw-box "27" {:span 2 :text-anchor "start" :borders {}})
(draw-box "26" {:borders {}})
(draw-box "25" {:borders {}})
(draw-box "24" {:span 2 :text-anchor "start" :borders {}})
(draw-box "20" {:span 2 :text-anchor "end" :borders {}})
(draw-box "19" {:span 2 :text-anchor "start" :borders {}})
(draw-box "15" {:span 2 :text-anchor "end" :borders {}})
(draw-box "14" {:borders {}})
(draw-box nil {:borders {}})
(draw-box "12" {:borders {}})
(draw-box "11" {:span 2 :text-anchor "start" :borders {}})
(draw-box "7" {:span 2 :text-anchor "end" :borders {}})
(draw-box "6" {:span 2 :text-anchor "start" :borders {}})
(draw-box "0" {:span 2 :text-anchor "end" :borders {}})
(draw-box nil {:span 5 :borders {}})
(draw-box "funct7" {:span 8})
(draw-box "rs2" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "funct3" {:span 3})
(draw-box "rd" {:span 4})
(draw-box "opcode" {:span 4})
(draw-box " R-type" {:span 5 :text-anchor "start" :borders {}})
(draw-box "imm[11:0]" {:span 12})
(draw-box "rs1" {:span 4})
(draw-box "funct3" {:span 3})
(draw-box "rd" {:span 4})
(draw-box "opcode" {:span 4})
(draw-box " I-type" {:span 5 :text-anchor "start" :borders {}})
(draw-box nil {:span 32 :borders {}})
(draw-box (text "Trap-Return Instructions" {:font-weight "bold" :font-size 24}) {:span 27 :borders {}})
(draw-box nil {:span 5 :borders {}})
(draw-box "0001000" {:span 8})
(draw-box "00010" {:span 4})
(draw-box "00000" {:span 4})
(draw-box "000" {:span 3})
(draw-box "00000" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box " SRET" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0011000" {:span 8})
(draw-box "00010" {:span 4})
(draw-box "00000" {:span 4})
(draw-box "000" {:span 3})
(draw-box "00000" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box " MRET" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0111000" {:span 8})
(draw-box "00010" {:span 4})
(draw-box "00000" {:span 4})
(draw-box "000" {:span 3})
(draw-box "00000" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box " MNRET" {:span 5 :text-anchor "start" :borders {}})
(draw-box nil {:span 32 :borders {}})
(draw-box (text "Interrupt-Management Instructions" {:font-weight "bold" :font-size 24}) {:span 27 :borders {}})
(draw-box nil {:span 5 :borders {}})
(draw-box "0001000" {:span 8})
(draw-box "00101" {:span 4})
(draw-box "00000" {:span 4})
(draw-box "000" {:span 3})
(draw-box "00000" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box "WFI" {:span 5 :text-anchor "start" :borders {}})
(draw-box nil {:span 32 :borders {}})
(draw-box (text "Supervisor Memory-Management Instructions" {:font-weight "bold" :font-size 24}) {:span 27 :borders {}})
(draw-box nil {:span 5 :borders {}})
(draw-box "0001001" {:span 8})
(draw-box "rs2" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "000" {:span 3})
(draw-box "00000" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box "SFENCE.VMA" {:span 5 :text-anchor "start" :borders {}})
(draw-box nil {:span 32 :borders {}})
(draw-box (text "Hypervisor Memory-Management Instructions" {:font-weight "bold" :font-size 24}) {:span 27 :borders {}})
(draw-box nil {:span 5 :borders {}})
(draw-box "0010001" {:span 8})
(draw-box "rs2" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "000" {:span 3})
(draw-box "00000" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box "HFENCE.VVMA" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0110001" {:span 8})
(draw-box "rs2" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "000" {:span 3})
(draw-box "00000" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box "HFENCE.GVMA" {:span 5 :text-anchor "start" :borders {}})
(draw-box nil {:span 32 :borders {}})
(draw-box (text "Hypervisor Virtual-Machine Load and Store Instructions" {:font-weight "bold" :font-size 24}) {:span 27 :borders {}})
(draw-box nil {:span 5 :borders {}})
(draw-box "0110001" {:span 8})
(draw-box "00000" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "100" {:span 3})
(draw-box "rd" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box "HLV.B" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0110001" {:span 8})
(draw-box "00001" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "100" {:span 3})
(draw-box "rd" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box "HLV.BU" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0110010" {:span 8})
(draw-box "00000" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "100" {:span 3})
(draw-box "rd" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box "HLV.H" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0110010" {:span 8})
(draw-box "00001" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "100" {:span 3})
(draw-box "rd" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box "HLV.HU" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0110100" {:span 8})
(draw-box "00000" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "100" {:span 3})
(draw-box "rd" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box "HLV.W" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0110010" {:span 8})
(draw-box "00011" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "100" {:span 3})
(draw-box "rd" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box "HLVX.HU" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0110010" {:span 8})
(draw-box "00011" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "100" {:span 3})
(draw-box "rd" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box "HLVX.WU" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0110001" {:span 8})
(draw-box "rs2" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "100" {:span 3})
(draw-box "00000" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box "HSV.B" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0110011" {:span 8})
(draw-box "rs2" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "100" {:span 3})
(draw-box "00000" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box "HSV.H" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0110101" {:span 8})
(draw-box "rs2" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "100" {:span 3})
(draw-box "00000" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box "HSV.W" {:span 5 :text-anchor "start" :borders {}})
(draw-box nil {:span 32 :borders {}})
(draw-box (text "Hypervisor Virtual-Machine Load and Store Instructions, RV64 only" {:font-weight "bold" :font-size 24}) {:span 27 :borders {}})
(draw-box nil {:span 5 :borders {}})
(draw-box "0110100" {:span 8})
(draw-box "00001" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "100" {:span 3})
(draw-box "rd" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box " HLV.WU" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0110110" {:span 8})
(draw-box "00000" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "100" {:span 3})
(draw-box "rd" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box " HLV.D" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0110111" {:span 8})
(draw-box "rs2" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "100" {:span 3})
(draw-box "00000" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box " HSV.D" {:span 5 :text-anchor "start" :borders {}})
(draw-box nil {:span 32 :borders {}})
(draw-box (text "Svinval Memory-Management Extension" {:font-weight "bold" :font-size 24}) {:span 27 :borders {}})
(draw-box nil {:span 5 :borders {}})
(draw-box "0001011" {:span 8})
(draw-box "rs2" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "000" {:span 3})
(draw-box "00000" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box " SINVAL.VMA" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0001100" {:span 8})
(draw-box "00000" {:span 4})
(draw-box "00000" {:span 4})
(draw-box "000" {:span 3})
(draw-box "00000" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box " SFENCE.W.INVAL" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0001100" {:span 8})
(draw-box "00001" {:span 4})
(draw-box "00000" {:span 4})
(draw-box "000" {:span 3})
(draw-box "00000" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box " SFENCE.INVAL.IR" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0010011" {:span 8})
(draw-box "rs2" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "000" {:span 3})
(draw-box "00000" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box " HINVAL.VVMA" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0110011" {:span 8})
(draw-box "rs2" {:span 4})
(draw-box "rs1" {:span 4})
(draw-box "000" {:span 3})
(draw-box "00000" {:span 4})
(draw-box "1110011" {:span 4})
(draw-box " HINVAL.GVMA" {:span 5 :text-anchor "start" :borders {}})
----

30
vendor/riscv/riscv-isa-manual/src/images/bytefield/rv32hgatp.edn vendored
View file

@ -1,30 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "31" {:span 3 :borders {}})
(draw-box "30" {:span 3 :text-anchor "start" :borders {}})
(draw-box "29" {:span 4 :text-anchor "end" :borders {}})
(draw-box "28" {:span 4 :text-anchor "start" :borders {}})
(draw-box "22" {:span 3 :text-anchor "end" :borders {}})
(draw-box "21" {:span 7 :text-anchor "start" :borders {}})
(draw-box "0" {:span 8 :text-anchor "end" :borders {}})
(draw-box "MODE" {:span 3})
(draw-box "0" {:span 3 :text-anchor "end" :borders {:left :border-unrelated :top :border-unrelated :bottom :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 4 :text-anchor "start":borders {:right :border-unrelated :top :border-unrelated :bottom :border-unrelated}})
(draw-box "VMID" {:span 4 :text-anchor "end" :borders {:left :border-unrelated :top :border-unrelated :bottom :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 3 :text-anchor "start" :borders {:right :border-unrelated :top :border-unrelated :bottom :border-unrelated}})
(draw-box "PPN" {:span 7 :text-anchor "end":borders {:left :border-unrelated :top :border-unrelated :bottom :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 8 :text-anchor "start" :borders {:right :border-unrelated :top :border-unrelated :bottom :border-unrelated}})
(draw-box "1" {:span 3 :borders {}})
(draw-box "2" {:span 7 :borders {}})
(draw-box "7" {:span 7 :borders {}})
(draw-box "22" {:span 15 :borders {}})
----

26
vendor/riscv/riscv-isa-manual/src/images/bytefield/rv32satp.edn vendored
View file

@ -1,26 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "31" {:span 8 :borders {}})
(draw-box "30" {:span 3 :text-anchor "start" :borders {}})
(draw-box "22" {:span 5 :text-anchor "end" :borders {}})
(draw-box "21" {:span 8 :text-anchor "start" :borders {}})
(draw-box "0" {:span 8 :text-anchor "end" :borders {}})
(draw-box "MODE" {:span 3 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 5 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "ASID" {:span 3 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 5 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "PPN" {:span 8 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 8 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "1" {:span 8 :borders {}})
(draw-box "9" {:span 8 :borders {}})
(draw-box "22" {:span 16 :borders {}})
----

26
vendor/riscv/riscv-isa-manual/src/images/bytefield/rv32vsatpreg.edn vendored
View file

@ -1,26 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "31" {:span 8 :borders {}})
(draw-box "30" {:span 4 :text-anchor "start" :borders {}})
(draw-box "22" {:span 4 :text-anchor "end" :borders {}})
(draw-box "21" {:span 8 :text-anchor "start" :borders {}})
(draw-box "0" {:span 8 :text-anchor "end" :borders {}})
(draw-box "Mode" {:span 4 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 4 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "ASID" {:span 4 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 4 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "PPN" {:span 8 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 8 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "1" {:span 8 :borders {}})
(draw-box "9" {:span 8 :borders {}})
(draw-box "22" {:span 16 :borders {}})
----

32
vendor/riscv/riscv-isa-manual/src/images/bytefield/rv64hgatp.edn vendored
View file

@ -1,32 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "63" {:span 4 :text-anchor "start" :borders {}})
(draw-box "60" {:span 4 :text-anchor "end" :borders {}})
(draw-box "59" {:span 3 :text-anchor "start" :borders {}})
(draw-box "58" {:span 3 :text-anchor "end" :borders {}})
(draw-box "57" {:span 4 :text-anchor "start" :borders {}})
(draw-box "44" {:span 4 :text-anchor "end" :borders {}})
(draw-box "43" {:span 5 :text-anchor "start" :borders {}})
(draw-box "0" {:span 5 :text-anchor "end" :borders {}})
(draw-box "MODE" {:span 4 :text-anchor "end" :borders {:left :border-unrelated :top :border-unrelated :bottom :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 4 :text-anchor "start":borders {:right :border-unrelated :top :border-unrelated :bottom :border-unrelated}})
(draw-box "0" {:span 3 :text-anchor "end" :borders {:left :border-unrelated :top :border-unrelated :bottom :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 3 :text-anchor "start":borders {:right :border-unrelated :top :border-unrelated :bottom :border-unrelated}})
(draw-box "VMID" {:span 4 :text-anchor "end" :borders {:left :border-unrelated :top :border-unrelated :bottom :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 4 :text-anchor "start" :borders {:right :border-unrelated :top :border-unrelated :bottom :border-unrelated}})
(draw-box "PPN" {:span 5 :text-anchor "end":borders {:left :border-unrelated :top :border-unrelated :bottom :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 5 :text-anchor "start" :borders {:right :border-unrelated :top :border-unrelated :bottom :border-unrelated}})
(draw-box "4" {:span 8 :borders {}})
(draw-box "2" {:span 6 :borders {}})
(draw-box "14" {:span 8 :borders {}})
(draw-box "44" {:span 10 :borders {}})
----

27
vendor/riscv/riscv-isa-manual/src/images/bytefield/rv64satp.edn vendored
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@ -1,27 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "63" {:span 5 :text-anchor "start" :borders {}})
(draw-box "60" {:span 5 :text-anchor "end" :borders {}})
(draw-box "59" {:span 5 :text-anchor "start" :borders {}})
(draw-box "44" {:span 5 :text-anchor "end" :borders {}})
(draw-box "43" {:span 6 :text-anchor "start" :borders {}})
(draw-box "0" {:span 6 :text-anchor "end" :borders {}})
(draw-box "MODE" {:span 5 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 5 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "ASID" {:span 5 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 5 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "PPN" {:span 6 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 6 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "4" {:span 10 :borders {}})
(draw-box "16" {:span 10 :borders {}})
(draw-box "44" {:span 12 :borders {}})
----

27
vendor/riscv/riscv-isa-manual/src/images/bytefield/rv64vsatpreg.edn vendored
View file

@ -1,27 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "63" {:span 4 :text-anchor "start" :borders {}})
(draw-box "60" {:span 4 :text-anchor "end" :borders {}})
(draw-box "59" {:span 4 :text-anchor "start" :borders {}})
(draw-box "44" {:span 4 :text-anchor "end" :borders {}})
(draw-box "43" {:span 8 :text-anchor "start" :borders {}})
(draw-box "0" {:span 8 :text-anchor "end" :borders {}})
(draw-box "Mode" {:span 4 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 4 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "ASID" {:span 4 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 4 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "PPN" {:span 8 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WARL)" {:font-weight "bold" :font-size 24}) {:span 8 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "4" {:span 8 :borders {}})
(draw-box "16" {:span 8 :borders {}})
(draw-box "44" {:span 16 :borders {}})
----

106
vendor/riscv/riscv-isa-manual/src/images/bytefield/rvc-instr-quad0.adoc vendored
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@ -1,106 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback"}])
(def row-height 35 )
(def row-header-fn nil)
(def left-margin 0)
(def right-margin 40)
(def boxes-per-row 23)
(draw-column-headers {:labels (reverse ["" "" "" "" "" "" "" "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15"])})
(draw-box "000" {:span 3 :vertical-align "middle"})
(draw-box "0" {:span 8})
(draw-box "0" {:span 3})
(draw-box "00" {:span 2})
(draw-box (text "Illegal instruction" {:font-style "italic"}) {:span 7 :text-anchor "start" :borders {}})
(draw-box "000" {:span 3})
(draw-box "uimm[5:4|9:6|2|3]" {:span 8})
(draw-box (text "rd′" [:plain {:font-family "M+ 1p Fallback"}]) {:span 3})
(draw-box "00" {:span 2})
(draw-box (text "C.ADDI4SPN" :math [:sub "RES, uimm=0"]) {:span 7 :text-anchor "start" :borders {}})
(draw-box "001" {:span 3})
(draw-box "uimm[5:3]" {:span 3})
(draw-box "rs1′" {:span 3})
(draw-box (text "uimm[7:6]" {:font-size 16}) {:span 2})
(draw-box "rd′" {:span 3})
(draw-box "00" {:span 2})
(draw-box (text "C.FLD" :math [:sub "(RV32/64)"]) {:span 7 :text-anchor "start" :borders {}})
(draw-box "001" {:span 3})
(draw-box "uimm[5:4|8]" {:span 3})
(draw-box "rs1′" {:span 3})
(draw-box (text "uimm[7:6]" {:font-size 16}) {:span 2})
(draw-box "rd′" {:span 3})
(draw-box "00" {:span 2})
(draw-box (text "C.LQ" :math [:sub "(RV128)"]) {:span 7 :text-anchor "start" :borders {}})
(draw-box "010" {:span 3})
(draw-box "uimm[5:3]" {:span 3})
(draw-box "rs1′" {:span 3})
(draw-box (text "uimm[2|6]" {:font-size 16}) {:span 2})
(draw-box "rd′" {:span 3})
(draw-box "00" {:span 2})
(draw-box "C.LW" {:span 7 :text-anchor "start" :borders {}})
(draw-box "011" {:span 3})
(draw-box "uimm[5:3]" {:span 3})
(draw-box "rs1′" {:span 3})
(draw-box (text "uimm[2|6]" {:font-size 16}) {:span 2})
(draw-box "rd′" {:span 3})
(draw-box "00" {:span 2})
(draw-box (text "C.FLW" :math [:sub "(RV32)"]) {:span 7 :text-anchor "start" :borders {}})
(draw-box "011" {:span 3})
(draw-box "uimm[5:3]" {:span 3})
(draw-box "rs1′" {:span 3})
(draw-box (text "uimm[7:6]" {:font-size 16}) {:span 2})
(draw-box "rd′" {:span 3})
(draw-box "00" {:span 2})
(draw-box (text "C.LD" :math [:sub "(RV64/128)"]) {:span 7 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box "---" {:span 11})
(draw-box "00" {:span 2})
(draw-box (text "Reserved" {:font-style "italic"}) {:span 7 :text-anchor "start" :borders {}})
(draw-box "101" {:span 3})
(draw-box "uimm[5:3]" {:span 3})
(draw-box "rs1′" {:span 3})
(draw-box (text "uimm[7:6]" {:font-size 16}) {:span 2})
(draw-box "rs2′" {:span 3})
(draw-box "00" {:span 2})
(draw-box (text "C.FSD" :math [:sub "(RV32/64)"]) {:span 7 :text-anchor "start" :borders {}})
(draw-box "101" {:span 3})
(draw-box "uimm[5:4|8]" {:span 3})
(draw-box "rs1′" {:span 3})
(draw-box (text "uimm[7:6]" {:font-size 16}) {:span 2})
(draw-box "rs2′" {:span 3})
(draw-box "00" {:span 2})
(draw-box (text "C.SQ" :math [:sub "(RV128)"]) {:span 7 :text-anchor "start" :borders {}})
(draw-box "110" {:span 3})
(draw-box "uimm[5:3]" {:span 3})
(draw-box "rs1′" {:span 3})
(draw-box (text "uimm[2|6]" {:font-size 16}) {:span 2})
(draw-box "rs2′" {:span 3})
(draw-box "00" {:span 2})
(draw-box "C.SW" {:span 7 :text-anchor "start" :borders {}})
(draw-box "111" {:span 3})
(draw-box "uimm[5:3]" {:span 3})
(draw-box "rs1′" {:span 3})
(draw-box (text "uimm[2|6]" {:font-size 16}) {:span 2})
(draw-box "rs2′" {:span 3})
(draw-box "00" {:span 2})
(draw-box (text "C.FSW" :math [:sub "(RV32)"]) {:span 7 :text-anchor "start" :borders {}})
(draw-box "111" {:span 3})
(draw-box "uimm[5:3]" {:span 3})
(draw-box "rs1′" {:span 3})
(draw-box (text "uimm[7:6]" {:font-size 16}) {:span 2})
(draw-box "rs2′" {:span 3})
(draw-box "00" {:span 2})
(draw-box (text "C.SD" :math [:sub "(RV64/128)"]) {:span 7 :text-anchor "start" :borders {}})
----

189
vendor/riscv/riscv-isa-manual/src/images/bytefield/rvc-instr-quad1.adoc vendored
View file

@ -1,189 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-weight "bold" :font-family "M+ 1p Fallback"}])
(def row-height 50 )
(def row-header-fn nil)
(def left-margin 0)
(def right-margin 0)
(def boxes-per-row 19)
(def box-width 70)
(draw-column-headers {:labels (reverse ["" "" "" "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15"])})
(draw-box "000" {:span 3})
(draw-box "imm[5]" {:span 1})
(draw-box "0" {:span 5})
(draw-box "imm[4:0]" {:span 5})
(draw-box "01" {:span 2})
(draw-box (text "C.NOP" :math [:sub "(HINT, imm=0)"]) {:span 3 :text-anchor "start" :borders {}})
(draw-box "000" {:span 3})
(draw-box "imm[5]") {:span 1}
(draw-box "rs1/rd≠0" {:span 5})
(draw-box "imm[4:0]" {:span 5})
(draw-box "01" {:span 2})
(draw-box (text "C.ADDI" :math [:sub "(HINT, imm=0)"]) {:span 3 :text-anchor "start" :borders {}})
(draw-box "001" {:span 3})
(draw-box "imm[11|4|9:8|10|6|7|3:1|5]" {:span 11})
(draw-box "01" {:span 2})
(draw-box (text "C.JAL" :math [:sub "(RV32)"]) {:span 3 :text-anchor "start" :borders {}})
(draw-box "001" {:span 3})
(draw-box "imm[5]" {:span 1})
(draw-box "rs1/rd≠0" {:span 5})
(draw-box "imm[4:0]" {:span 5})
(draw-box "01" {:span 2})
(draw-box (text "C.ADDIW" :math [:sub "(RV64/128; RES, rd=0)"]) {:span 3 :text-anchor "start" :borders {}})
(draw-box "010" {:span 3})
(draw-box "imm[5]" {:span 1})
(draw-box "rd̸=0" {:span 5})
(draw-box "imm[4:0]" {:span 5})
(draw-box "01" {:span 2})
(draw-box (text "C.LI" :math [:sub "(HINT, rd=0)"]) {:span 3 :text-anchor "start" :borders {}})
(draw-box "011" {:span 3})
(draw-box "imm[9]" {:span 1})
(draw-box "2" {:span 5})
(draw-box "imm[4|6|8:7|5]" {:span 5})
(draw-box "01" {:span 2})
(draw-box (text "C.ADDI16SP" :math [:sub "(RES, imm=0)"]) {:span 3 :text-anchor "start" :borders {}})
(draw-box "011" {:span 3})
(draw-box (text "imm[17]" {:font-width 11}) {:span 1})
(draw-box "rd̸={0, 2}" {:span 5})
(draw-box "imm[16:12]" {:span 5})
(draw-box "01" {:span 2})
(draw-box (text "C.LUI" :math [:sub "(RES, imm=0; HINT, rd=0)"]) {:span 3 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box (text "uimm[5]" {:font-width 11}) {:span 1})
(draw-box "00" {:span 2})
(draw-box "rs1ʹ/rdʹ" {:span 3})
(draw-box "uimm[4:0]" {:span 5})
(draw-box "01" {:span 2})
(draw-box (text "C.SRLI" :math [:sub "(RV32 Custom, uimm[5]=1)"]) {:span 3 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box "0" {:span 1})
(draw-box "00" {:span 2})
(draw-box "rs1ʹ/rdʹ" {:span 3})
(draw-box "0" {:span 5})
(draw-box "01" {:span 2})
(draw-box (text "C.SRLI64" :math [:sub "(RV128; RV32/64 HINT)"]) {:span 3 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box (text "uimm[5]" {:font-width 11}) {:span 1})
(draw-box "01" {:span 2})
(draw-box "rs1ʹ/rdʹ" {:span 3})
(draw-box "uimm[4:0]" {:span 5})
(draw-box "01" {:span 2})
(draw-box (text "C.SRAI" :math [:sub "(RV32 Custom, uimm[5]=1)"]) {:span 3 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box "0" {:span 1})
(draw-box "01" {:span 2})
(draw-box "rs1ʹ/rdʹ" {:span 3})
(draw-box "0" {:span 5})
(draw-box "01" {:span 2})
(draw-box (text "C.SRAI64" :math [:sub "(RV128; RV32/64 HINT)"]) {:span 3 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box "imm[5]" {:span 1})
(draw-box "10" {:span 2})
(draw-box "rs1ʹ/rdʹ" {:span 3})
(draw-box "imm[4:0]" {:span 5})
(draw-box "01" {:span 2})
(draw-box "C.ANDI" {:span 3 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box "0" {:span 1})
(draw-box "11" {:span 2})
(draw-box "rs1ʹ/rdʹ" {:span 3})
(draw-box "00" {:span 2})
(draw-box "rs2′" {:span 3})
(draw-box "01" {:span 2})
(draw-box "C.SUB" {:span 3 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box "0" {:span 1})
(draw-box "11" {:span 2})
(draw-box "rs1ʹ/rdʹ" {:span 3})
(draw-box "01" {:span 2})
(draw-box "rs2′" {:span 3})
(draw-box "01" {:span 2})
(draw-box "C.XOR" {:span 3 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box "0" {:span 1})
(draw-box "11" {:span 2})
(draw-box "rs1ʹ/rdʹ" {:span 3})
(draw-box "10" {:span 2})
(draw-box "rs2′" {:span 3})
(draw-box "01" {:span 2})
(draw-box "C.OR" {:span 3 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box "0" {:span 1})
(draw-box "11" {:span 2})
(draw-box "rs1ʹ/rdʹ" {:span 3})
(draw-box "11" {:span 2})
(draw-box "rs2′" {:span 3})
(draw-box "01" {:span 2})
(draw-box "C.AND" {:span 3 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box "1" {:span 1})
(draw-box "11" {:span 2})
(draw-box "rs1ʹ/rdʹ" {:span 3})
(draw-box "00" {:span 2})
(draw-box "rs2′" {:span 3})
(draw-box "01" {:span 2})
(draw-box (text "C.SUBW" :math [:sub "(RV64/128; RV32 RES)"]) {:span 3 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box "1" {:span 1})
(draw-box "11" {:span 2})
(draw-box "rs1ʹ/rdʹ" {:span 3})
(draw-box "01" {:span 2})
(draw-box "rs2′" {:span 3})
(draw-box "01" {:span 2})
(draw-box (text "C.ADDW" :math [:sub "(RV64/128; RV32 RES)"]) {:span 3 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box "1" {:span 1})
(draw-box "11" {:span 2})
(draw-box "---" {:span 3})
(draw-box "10" {:span 2})
(draw-box "---" {:span 3})
(draw-box "01" {:span 2})
(draw-box (text "Reserved" {:font-style "italic"}) {:span 3 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box "1" {:span 1})
(draw-box "11" {:span 2})
(draw-box "---" {:span 3})
(draw-box "11" {:span 2})
(draw-box "---" {:span 3})
(draw-box "01" {:span 2})
(draw-box (text "Reserved" {:font-style "italic"}) {:span 3 :text-anchor "start" :borders {}})
(draw-box "101" {:span 3})
(draw-box "imm[11|4|9:8|10|6|7|3:1|5]" {:span 11})
(draw-box "01" {:span 2})
(draw-box "C.J" {:span 3 :text-anchor "start" :borders {}})
(draw-box "110" {:span 3})
(draw-box "imm[8|4:3]" {:span 3})
(draw-box "rs1′" {:span 3})
(draw-box "imm[7:6|2:1|5]" {:span 5})
(draw-box "01" {:span 2})
(draw-box "C.BEQZ" {:span 3 :text-anchor "start" :borders {}})
(draw-box "111" {:span 3})
(draw-box "imm[8|4:3]" {:span 3})
(draw-box "rs1′" {:span 3})
(draw-box "imm[7:6|2:1|5]" {:span 5})
(draw-box "01" {:span 2})
(draw-box "C.BNEZ" {:span 3 :text-anchor "start" :borders {}})
----

125
vendor/riscv/riscv-isa-manual/src/images/bytefield/rvc-instr-quad2.adoc vendored
View file

@ -1,125 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback"}])
(def row-height 50 )
(def row-header-fn nil)
(def left-margin 0)
(def right-margin 40)
(def boxes-per-row 22)
(def box-width 70)
(draw-column-headers {:labels (reverse ["" "" "" "" "" "" "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15"])})
(draw-box "000" {:span 3})
(draw-box (text "uimm[5]" {:font-size 16}) {:span 1})
(draw-box "rs1/rd≠0" {:span 5})
(draw-box "uimm[4:0]" {:span 5})
(draw-box "10" {:span 2})
(draw-box (text "C.SLLI" :math [:sub "(HINT, rd=0; RV32 Custom, uimm[5]=1)"]) {:span 6 :text-anchor "start" :borders {}})
(draw-box "000" {:span 3})
(draw-box "0" {:span 1})
(draw-box "rs1/rd≠0" {:span 5})
(draw-box "0" {:span 5})
(draw-box "10" {:span 2})
(draw-box (text "C.SLLI64" :math [:sub "(RV128; RV32/64 HINT; HINT, rd=0)"]) {:span 6 :text-anchor "start" :borders {}})
(draw-box "001" {:span 3})
(draw-box (text "uimm[5]" {:font-size 16}) {:span 1})
(draw-box "rd" {:span 5})
(draw-box "uimm[4:3|8:6]" {:span 5})
(draw-box "10" {:span 2})
(draw-box (text "C.FLDSP" :math [:sub "(RV32/64)"]) {:span 6 :text-anchor "start" :borders {}})
(draw-box "001" {:span 3})
(draw-box (text "uimm[5]" {:font-size 16}) {:span 1})
(draw-box "rd≠0" {:span 5})
(draw-box "uimm[4|9:6]" {:span 5})
(draw-box "10" {:span 2})
(draw-box (text "C.LQSP" :math [:sub "(RV128; RES, rd=0)"]) {:span 6 :text-anchor "start" :borders {}})
(draw-box "010" {:span 3})
(draw-box (text "uimm[5]" {:font-size 16}) {:span 1})
(draw-box "rd≠0" {:span 5})
(draw-box "uimm[4:2|7:6]" {:span 5})
(draw-box "10" {:span 2})
(draw-box (text "C.LWSP" :math [:sub "(RES, rd=0)"]) {:span 6 :text-anchor "start" :borders {}})
(draw-box "011" {:span 3})
(draw-box (text "uimm[5]" {:font-size 16}) {:span 1})
(draw-box "rd" {:span 5})
(draw-box "uimm[4:2|7:6]" {:span 5})
(draw-box "10" {:span 2})
(draw-box (text "C.FLWSP" :math [:sub "(RV32)"]) {:span 6 :text-anchor "start" :borders {}})
(draw-box "011" {:span 3})
(draw-box (text "uimm[5]" {:font-size 16}) {:span 1})
(draw-box "rd≠0" {:span 5})
(draw-box "uimm[4:3|8:6]" {:span 5})
(draw-box "10" {:span 2})
(draw-box (text "C.LDSP" :math [:sub "(RV64/128; RES, rd=0)"]) {:span 6 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box "0" {:span 1})
(draw-box "rs1≠0" {:span 5})
(draw-box "0" {:span 5})
(draw-box "10" {:span 2})
(draw-box (text "C.JR" :math [:sub "(RES, rs1=0)"]) {:span 6 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box "0" {:span 1})
(draw-box "rd≠0" {:span 5})
(draw-box "rs2≠0" {:span 5})
(draw-box "10" {:span 2})
(draw-box (text "C.MV" :math [:sub "(HINT, rd=0)"]) {:span 6 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box "1" {:span 1})
(draw-box "0" {:span 5})
(draw-box "0" {:span 5})
(draw-box "10" {:span 2})
(draw-box "C.EBREAK" {:span 6 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box "1" {:span 1})
(draw-box "rs1≠0" {:span 5})
(draw-box "0" {:span 5})
(draw-box "10" {:span 2})
(draw-box "C.JALR" {:span 6 :text-anchor "start" :borders {}})
(draw-box "100" {:span 3})
(draw-box "1" {:span 1})
(draw-box "rs1/rd≠0" {:span 5})
(draw-box "rs2≠0" {:span 5})
(draw-box "10" {:span 2})
(draw-box (text "C.ADD" :math [:sub "(HINT, rd=0)"]) {:span 6 :text-anchor "start" :borders {}})
(draw-box "101" {:span 3})
(draw-box "uimm[5:3|8:6]" {:span 6})
(draw-box "rs2" {:span 5})
(draw-box "10" {:span 2})
(draw-box (text "C.FSDSP" :math [:sub "(RV32/64)"]) {:span 6 :text-anchor "start" :borders {}})
(draw-box "101" {:span 3})
(draw-box "uimm[5:4|9:6]" {:span 6})
(draw-box "rs2" {:span 5})
(draw-box "10" {:span 2})
(draw-box (text "C.SQSP" :math [:sub "(RV128)"]) {:span 6 :text-anchor "start" :borders {}})
(draw-box "110" {:span 3})
(draw-box "uimm[5:2|7:6]" {:span 6})
(draw-box "rs2" {:span 5})
(draw-box "10" {:span 2})
(draw-box "C.SWSP" {:span 6 :text-anchor "start" :borders {}})
(draw-box "111" {:span 3})
(draw-box "uimm[5:2|7:6]" {:span 6})
(draw-box "rs2" {:span 5})
(draw-box "10" {:span 2})
(draw-box (text "C.FSWSP" :math [:sub "(RV32)"]) {:span 6 :text-anchor "start" :borders {}})
(draw-box "111" {:span 3})
(draw-box "uimm[5:3|8:6]" {:span 6})
(draw-box "rs2" {:span 5})
(draw-box "10" {:span 2})
(draw-box (text "C.SDSP" :math [:sub "(RV64/128)"]) {:span 6 :text-anchor "start" :borders {}})
----

21
vendor/riscv/riscv-isa-manual/src/images/bytefield/scausereg.edn vendored
View file

@ -1,21 +0,0 @@
[bytefield]
----
(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
(def row-height 40 )
(def row-header-fn nil)
(def left-margin 30)
(def right-margin 30)
(def boxes-per-row 32)
(draw-box "SXLEN-1" {:span 6 :borders {}})
(draw-box "SXLEN-2" {:span 12 :text-anchor "start" :borders {}})
(draw-box "0" {:span 14 :text-anchor "end" :borders {}})
(draw-box "Interrupt" {:span 6})
(draw-box "Exception Code" {:span 12 :text-anchor "end":borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
(draw-box (text "(WLRL)" {:font-weight "bold" :font-size 24}) {:span 14 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
(draw-box "1" {:span 6 :borders {}})
(draw-box "SXLEN-1" {:span 26 :borders {}})
----

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