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move pmp tests to synthesis tests stage
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parent
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commit
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3 changed files with 15 additions and 17 deletions
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@ -304,6 +304,20 @@ fpga-build:
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- mv corev_apu/fpga/work-fpga/ariane_xilinx.bit artifacts/ariane_xilinx_$TARGET.bit
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- python3 .gitlab-ci/scripts/report_fpga.py corev_apu/fpga/reports/ariane.utilization.rpt
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pmp_tests:
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timeout : 2 hours
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extends:
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- .synthesis_test
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variables:
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DASHBOARD_JOB_TITLE: "PMP $DV_TARGET"
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DASHBOARD_JOB_DESCRIPTION: "Physical Memory Protection tests"
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DASHBOARD_SORT_INDEX: 2
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DASHBOARD_JOB_CATEGORY: "Test suites"
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DV_SIMULATORS: "vcs-uvm"
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SPIKE_TANDEM: 1
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script: source verif/regress/pmp_cv32a60x_tests.sh
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after_script: *simu_after_script
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.regress_test:
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stage: heavy tests
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before_script:
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@ -420,20 +434,6 @@ mmu_sv32_tests:
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script: source verif/regress/dv-riscv-mmu-sv32-test.sh
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after_script: *simu_after_script
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pmp_tests:
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timeout : 2 hours
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extends:
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- .regress_test
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variables:
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DASHBOARD_JOB_TITLE: "PMP $DV_TARGET"
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DASHBOARD_JOB_DESCRIPTION: "Physical Memory Protection tests"
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DASHBOARD_SORT_INDEX: 2
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DASHBOARD_JOB_CATEGORY: "Test suites"
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DV_SIMULATORS: "vcs-uvm"
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SPIKE_TANDEM: 1
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script: source verif/regress/pmp_cv32a60x_tests.sh
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after_script: *simu_after_script
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generated_tests:
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extends:
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- .verif_test
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@ -6,7 +6,6 @@
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## Original Author: Konstantinos Leventos - Robert Bosch France SAS
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##-----------------------------------------------------------------------------
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# Where the tools are
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if ! [ -n "$RISCV" ]; then
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echo "Error: RISCV variable undefined"
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@ -19,7 +18,6 @@ source ./verif/regress/install-spike.sh
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# Setup sim env
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source ./verif/sim/setup-env.sh
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if ! [ -n "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=vcs-uvm
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fi
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@ -74,4 +74,4 @@ testlist:
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- test: lsu_tor_test
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<<: *common_test_config
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iterations: 1
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asm_tests: <path_var>/custom/pmp/lsu_tor_test.S
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asm_tests: <path_var>/custom/pmp/lsu_tor_test.S
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