move pmp tests to synthesis tests stage

This commit is contained in:
Valentin Thomazic 2025-03-12 17:09:14 +01:00
parent 12d26610cf
commit 9bdb41ecd5
3 changed files with 15 additions and 17 deletions

View file

@ -304,6 +304,20 @@ fpga-build:
- mv corev_apu/fpga/work-fpga/ariane_xilinx.bit artifacts/ariane_xilinx_$TARGET.bit
- python3 .gitlab-ci/scripts/report_fpga.py corev_apu/fpga/reports/ariane.utilization.rpt
pmp_tests:
timeout : 2 hours
extends:
- .synthesis_test
variables:
DASHBOARD_JOB_TITLE: "PMP $DV_TARGET"
DASHBOARD_JOB_DESCRIPTION: "Physical Memory Protection tests"
DASHBOARD_SORT_INDEX: 2
DASHBOARD_JOB_CATEGORY: "Test suites"
DV_SIMULATORS: "vcs-uvm"
SPIKE_TANDEM: 1
script: source verif/regress/pmp_cv32a60x_tests.sh
after_script: *simu_after_script
.regress_test:
stage: heavy tests
before_script:
@ -420,20 +434,6 @@ mmu_sv32_tests:
script: source verif/regress/dv-riscv-mmu-sv32-test.sh
after_script: *simu_after_script
pmp_tests:
timeout : 2 hours
extends:
- .regress_test
variables:
DASHBOARD_JOB_TITLE: "PMP $DV_TARGET"
DASHBOARD_JOB_DESCRIPTION: "Physical Memory Protection tests"
DASHBOARD_SORT_INDEX: 2
DASHBOARD_JOB_CATEGORY: "Test suites"
DV_SIMULATORS: "vcs-uvm"
SPIKE_TANDEM: 1
script: source verif/regress/pmp_cv32a60x_tests.sh
after_script: *simu_after_script
generated_tests:
extends:
- .verif_test

View file

@ -6,7 +6,6 @@
## Original Author: Konstantinos Leventos - Robert Bosch France SAS
##-----------------------------------------------------------------------------
# Where the tools are
if ! [ -n "$RISCV" ]; then
echo "Error: RISCV variable undefined"
@ -19,7 +18,6 @@ source ./verif/regress/install-spike.sh
# Setup sim env
source ./verif/sim/setup-env.sh
if ! [ -n "$DV_SIMULATORS" ]; then
DV_SIMULATORS=vcs-uvm
fi

View file

@ -74,4 +74,4 @@ testlist:
- test: lsu_tor_test
<<: *common_test_config
iterations: 1
asm_tests: <path_var>/custom/pmp/lsu_tor_test.S
asm_tests: <path_var>/custom/pmp/lsu_tor_test.S