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Performance tb (#2543)

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Anouar 2024-10-11 15:57:45 +01:00 • committed by GitHub
parent 7ae870e02f
commit 9c3aea232f
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10 changed files with 61 additions and 10 deletions
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14
verif/env/uvme/cov/uvme_interrupt_covg.sv vendored
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@ -105,7 +105,10 @@ function void uvme_interrupt_covg_c::build_phase(uvm_phase phase);
`uvm_fatal("CFG", "Configuration handle is null")
end
interrupt_cg = new("interrupt_cg");
if (!cfg.disable_all_csr_checks)
interrupt_cg = new("interrupt_cg");
else
`uvm_warning(get_type_name(), "Interrupt coverage will not be scored since config disable_all_csr_checks is true")
mon_trn_fifo = new("mon_trn_fifo" , this);
@ -117,10 +120,11 @@ task uvme_interrupt_covg_c::run_phase(uvm_phase phase);
`uvm_info(get_type_name(), "The Interrupt env coverage model is running", UVM_LOW);
forever begin
mon_trn_fifo.get(mon_trn);
interrupt_cg.sample(mon_trn.instr);
end
if (!cfg.disable_all_csr_checks)
forever begin
mon_trn_fifo.get(mon_trn);
interrupt_cg.sample(mon_trn.instr);
end
endtask : run_phase

30
verif/env/uvme/uvme_cva6_cfg.sv vendored
View file

@ -35,8 +35,11 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
rand bit tandem_enabled;
rand bit cov_model_enabled;
rand bit trn_log_enabled;
rand bit force_disable_csr_checks; // force disable all csr checks in RVFI. Note that all csrs info in instruction from RVFI will be removed
rand int unsigned sys_clk_period;
bit performance_mode; // Will force disable coverage, csr checks, scoreboard and loggers
// Agent cfg handles
rand uvma_clknrst_cfg_c clknrst_cfg;
rand uvma_axi_cfg_c axi_cfg;
@ -66,12 +69,14 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
`uvm_field_int ( tandem_enabled , UVM_DEFAULT )
`uvm_field_int ( cov_model_enabled , UVM_DEFAULT )
`uvm_field_int ( trn_log_enabled , UVM_DEFAULT )
`uvm_field_int ( force_disable_csr_checks , UVM_DEFAULT )
`uvm_field_int ( ext_zicond_supported , UVM_DEFAULT )
`uvm_field_int ( HPDCache_supported , UVM_DEFAULT )
`uvm_field_int ( nr_pmp_entries , UVM_DEFAULT )
`uvm_field_int ( ext_zihpm_supported , UVM_DEFAULT )
`uvm_field_int ( MmuPresent , UVM_DEFAULT )
`uvm_field_int ( sys_clk_period , UVM_DEFAULT + UVM_DEC)
`uvm_field_int ( performance_mode , UVM_DEFAULT )
`uvm_field_object(clknrst_cfg, UVM_DEFAULT)
@ -92,6 +97,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
soft scoreboard_enabled == 1;
soft cov_model_enabled == 1;
soft trn_log_enabled == 1;
soft force_disable_csr_checks == 0;
soft sys_clk_period == uvme_cva6_sys_default_clk_period; // see uvme_cva6_constants.sv
}
@ -183,12 +189,21 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
axi_cfg.trn_log_enabled == 1;
rvfi_cfg.trn_log_enabled == 1;
isacov_cfg.trn_log_enabled == 1;
} else {
clknrst_cfg.trn_log_enabled == 0;
axi_cfg.trn_log_enabled == 0;
rvfi_cfg.trn_log_enabled == 0;
isacov_cfg.trn_log_enabled == 0;
}
if (cov_model_enabled) {
isacov_cfg.cov_model_enabled == 1;
axi_cfg.cov_model_enabled == 1;
interrupt_cfg.cov_model_enabled == 1;
} else {
isacov_cfg.cov_model_enabled == 0;
axi_cfg.cov_model_enabled == 0;
interrupt_cfg.cov_model_enabled == 0;
}
}
@ -208,6 +223,8 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
*/
extern virtual function void set_unsupported_csr_mask();
extern virtual function void read_disable_csr_check_plusargs();
endclass : uvme_cva6_cfg_c
@ -226,6 +243,11 @@ function uvme_cva6_cfg_c::new(string name="uvme_cva6_cfg");
$value$plusargs("core_name=%s", this.core_name);
if ($test$plusargs("tb_performance_mode")) begin
performance_mode = 1;
`uvm_info(get_type_name(), "Testbench set in performance mode, coverage & csr checks & scoreboard & loggers will be deactivated", UVM_NONE);
end
endfunction : new
function void uvme_cva6_cfg_c::sample_parameters(uvma_core_cntrl_cntxt_c cntxt);
@ -322,4 +344,12 @@ function void uvme_cva6_cfg_c::set_unsupported_csr_mask();
endfunction : set_unsupported_csr_mask
function void uvme_cva6_cfg_c::read_disable_csr_check_plusargs();
super.read_disable_csr_check_plusargs();
if (force_disable_csr_checks)
disable_all_csr_checks = 1;
endfunction : read_disable_csr_check_plusargs
`endif // __UVME_CVA6_CFG_SV__

6
verif/env/uvme/uvme_cva6_env.sv vendored
View file

@ -223,7 +223,8 @@ function void uvme_cva6_env_c::connect_phase(uvm_phase phase);
csr_reg_predictor.map = csr_reg_block.default_map;
csr_reg_predictor.adapter = csr_reg_adapter;
csr_reg_block.default_map.set_auto_predict(0);
isacov_agent.monitor.ap.connect(csr_reg_predictor.bus_in);
if (cfg.cov_model_enabled)
isacov_agent.monitor.ap.connect(csr_reg_predictor.bus_in);
end
endfunction: connect_phase
@ -289,6 +290,9 @@ function void uvme_cva6_env_c::create_env_components();
if (cfg.scoreboard_enabled) begin
predictor = uvme_cva6_prd_c::type_id::create("predictor", this);
end
if (cfg.scoreboard_enabled || cfg.tandem_enabled) begin
sb = uvme_cva6_sb_c ::type_id::create("sb" , this);
end

4
verif/env/uvme/uvme_cva6_sb.sv vendored
View file

@ -457,6 +457,10 @@ task uvme_cva6_sb_c::run_phase(uvm_phase phase);
super.run_phase(phase);
if (cfg.scoreboard_enabled && cfg.disable_all_csr_checks)
`uvm_warning(get_type_name(),"Scoreboard enabled while config disable_all_csr_checks is true. Cycle and Trap will not be scoreboarded nor checked");
if (cfg.scoreboard_enabled && !cfg.disable_all_csr_checks)
fork
begin
forever begin

1
verif/regress/coremark.sh
View file

@ -92,4 +92,5 @@ python3 cva6.py \
--c_tests "$src0" \
--gcc_opts "${srcA[*]} ${cflags[*]}" \
--iss_timeout=2000 \
--issrun_opts="+tb_performance_mode" \
$DV_OPTS

1
verif/regress/dhrystone.sh
View file

@ -63,4 +63,5 @@ python3 cva6.py \
--iss="$DV_SIMULATORS" \
--iss_yaml=cva6.yaml \
--c_tests "$src0" \
--issrun_opts="+tb_performance_mode" \
--gcc_opts "${srcA[*]} ${cflags[*]}"

2
verif/regress/dv-riscv-arch-test.sh
View file

@ -36,4 +36,4 @@ else
fi
cd verif/sim
python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS --issrun_opts="+tb_performance_mode" $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld

2
verif/regress/dv-riscv-compliance.sh
View file

@ -29,5 +29,5 @@ if ! [ -n "$DV_SIMULATORS" ]; then
fi
cd verif/sim
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS --issrun_opts="+tb_performance_mode" $DV_OPTS
cd -

2
verif/regress/dv-riscv-tests.sh
View file

@ -36,6 +36,6 @@ fi
cd verif/sim
for TESTLIST in $DV_TESTLISTS
do
python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml $DV_OPTS
python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --issrun_opts="+tb_performance_mode" $DV_OPTS
done
cd -

9
verif/tests/uvmt/base-tests/uvmt_cva6_base_test.sv
View file

@ -70,7 +70,14 @@ class uvmt_cva6_base_test_c extends uvm_test;
constraint env_cfg_cons {
env_cfg.enabled == 1;
env_cfg.is_active == UVM_ACTIVE;
env_cfg.trn_log_enabled == 1;
if (!env_cfg.performance_mode) {
env_cfg.trn_log_enabled == 1;
} else {
env_cfg.trn_log_enabled == 0;
env_cfg.cov_model_enabled == 0;
env_cfg.force_disable_csr_checks == 1;
env_cfg.scoreboard_enabled == 0;
}
}
constraint axi_agent_cfg_cons {