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https://github.com/openhwgroup/cva6.git
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Make icache bypass-able
This commit is contained in:
Florian Zaruba
parent
5fb6f920d3
commit
9d1218529e
6 changed files with 28 additions and 59 deletions
2
Makefile
2
Makefile
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@ -176,7 +176,7 @@ $(tests): build
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verilate:
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$(verilator) $(ariane_pkg) $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) $(wildcard src/axi_slice/*.sv) \
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src/util/cluster_clock_gating.sv src/util/behav_sram.sv src/axi_mem_if/src/axi2mem.sv tb/agents/axi_if/axi_if.sv \
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--unroll-count 256 -Wno-fatal -LDFLAGS "-lfesvr" -CFLAGS "-std=c++11" -Wall --cc --trace \
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--unroll-count 256 -Wno-fatal -Werror-PINMISSING -LDFLAGS "-lfesvr" -CFLAGS "-std=c++11" -Wall --cc --trace \
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$(list_incdir) --top-module ariane_wrapped --exe tb/ariane_tb.cpp tb/simmem.cpp
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cd obj_dir && make -j8 -f Variane_wrapped.mk
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@ -68,9 +68,6 @@ module ariane #(
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logic if_ready_if_pcgen;
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logic fetch_valid_pcgen_if;
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// --------------
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// PCGEN <-> COMMIT
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// --------------
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// --------------
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// PCGEN <-> CSR
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// --------------
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logic [63:0] trap_vector_base_commit_pcgen;
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@ -186,6 +183,8 @@ module ariane #(
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logic tw_csr_id;
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logic tsr_csr_id;
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logic dcache_en_csr_nbdcache;
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logic icache_en_csr_frontend;
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// ----------------------------
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// Performance Counters <-> *
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// ----------------------------
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@ -214,22 +213,15 @@ module ariane #(
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logic halt_csr_ctrl;
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logic flush_dcache_ctrl_ex;
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logic flush_dcache_ack_ex_ctrl;
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// ----------------
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// ICache <-> *
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// ----------------
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logic flush_icache_ctrl_icache;
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logic bypass_icache_csr_icache;
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logic flush_icache_ctrl_icache;
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assign sec_lvl_o = priv_lvl;
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assign flush_dcache_ack_o = flush_dcache_ack_ex_ctrl;
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// --------------
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// Frontend
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// --------------
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frontend #(
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.BTB_ENTRIES ( BTB_ENTRIES ),
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.BHT_ENTRIES ( BHT_ENTRIES ),
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.RAS_DEPTH ( RAS_DEPTH )
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) i_frontend (
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frontend i_frontend (
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.en_cache_i ( icache_en_csr_frontend ),
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.flush_i ( flush_ctrl_if ), // not entirely correct
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.flush_bp_i ( 1'b0 ),
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.flush_icache_i ( flush_icache_ctrl_icache ),
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@ -478,7 +470,7 @@ module ariane #(
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.tw_o ( tw_csr_id ),
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.tsr_o ( tsr_csr_id ),
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.dcache_en_o ( dcache_en_csr_nbdcache ),
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.icache_en_o ( bypass_icache_csr_icache ),
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.icache_en_o ( icache_en_csr_frontend ),
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.perf_addr_o ( addr_csr_perf ),
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.perf_data_o ( data_csr_perf ),
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.perf_data_i ( data_perf_csr ),
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@ -29,8 +29,6 @@ module ariane_wrapped #(
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input logic clk_i,
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input logic rst_ni,
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input logic test_en_i, // enable all clock gates for testing
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// CPU Control Signals
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input logic fetch_enable_i,
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// Core ID, Cluster ID and boot address are considered more or less static
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input logic [63:0] boot_addr_i,
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input logic [ 3:0] core_id_i,
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@ -43,18 +41,7 @@ module ariane_wrapped #(
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output logic sec_lvl_o, // current privilege level oot
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// Timer facilities
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input logic [63:0] time_i, // global time (most probably coming from an RTC)
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input logic time_irq_i, // timer interrupt in
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// Debug Interface
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input logic debug_req_i,
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output logic debug_gnt_o,
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output logic debug_rvalid_o,
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input logic [15:0] debug_addr_i,
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input logic debug_we_i,
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input logic [63:0] debug_wdata_i,
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output logic [63:0] debug_rdata_o,
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output logic debug_halted_o,
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input logic debug_halt_i,
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input logic debug_resume_i
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input logic time_irq_i // timer interrupt in
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);
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localparam int unsigned AXI_NUMBYTES = AXI_DATA_WIDTH/8;
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@ -15,9 +15,6 @@
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import ariane_pkg::*;
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module frontend #(
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parameter int unsigned BTB_ENTRIES = 8,
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parameter int unsigned BHT_ENTRIES = 1024,
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parameter int unsigned RAS_DEPTH = 4,
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parameter int unsigned SET_ASSOCIATIVITY = 4,
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parameter int unsigned CACHE_LINE_WIDTH = 64, // in bit
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parameter int unsigned FETCH_WIDTH = 32
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@ -25,6 +22,7 @@ module frontend #(
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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input logic flush_i, // flush request for PCGEN
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input logic en_cache_i, // enable icache
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input logic flush_bp_i, // flush branch prediction
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input logic flush_icache_i, // instruction fence in
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// global input
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@ -65,7 +63,6 @@ module frontend #(
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logic instruction_valid;
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logic icache_speculative_d, icache_speculative_q;
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logic [63:0] icache_vaddr_d, icache_vaddr_q;
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// BHT, BTB and RAS prediction
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@ -104,7 +101,6 @@ module frontend #(
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logic [63:0] bp_vaddr;
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logic bp_valid; // we have a valid branch-prediction
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logic fetch_is_speculative; // is it a speculative fetch or a fetch which need to do for sure
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// branch-prediction which we inject into the pipeline
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branchpredict_sbe_t bp_sbe;
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logic fifo_valid, fifo_ready; // fetch FIFO
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@ -316,8 +312,6 @@ module frontend #(
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always_comb begin : npc_select
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automatic logic [63:0] fetch_address;
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fetch_is_speculative = 1'b0;
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fetch_address = npc_q;
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// keep stable by default
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npc_d = npc_q;
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@ -325,7 +319,6 @@ module frontend #(
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// 1. Branch Prediction
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// -------------------------------
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if (bp_valid) begin
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fetch_is_speculative = 1'b1;
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fetch_address = bp_vaddr;
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npc_d = bp_vaddr;
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end
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@ -334,7 +327,6 @@ module frontend #(
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// -------------------------------
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if (if_ready) begin
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npc_d = {fetch_address[63:2], 2'b0} + 64'h4;
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fetch_is_speculative = 1'b1;
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end
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// -------------------------------
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// 2. Control flow change request
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@ -374,7 +366,6 @@ module frontend #(
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npc_q <= boot_addr_i;
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icache_data_q <= '0;
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icache_valid_q <= 1'b0;
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icache_speculative_q <= 1'b0;
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icache_vaddr_q <= 'b0;
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icache_ex_q <= '0;
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unaligned_q <= 1'b0;
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@ -384,7 +375,6 @@ module frontend #(
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npc_q <= npc_d;
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icache_data_q <= icache_data_d;
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icache_valid_q <= icache_valid_d;
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icache_speculative_q <= icache_speculative_d;
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icache_vaddr_q <= icache_vaddr_d;
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icache_ex_q <= icache_ex_d;
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unaligned_q <= unaligned_d;
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@ -428,9 +418,11 @@ module frontend #(
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.CACHE_LINE_WIDTH ( 128 ),
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.FETCH_WIDTH ( FETCH_WIDTH )
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) i_icache (
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.clk_i,
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.rst_ni,
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.flush_i ( flush_icache_i ),
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.en_cache_i,
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.vaddr_i ( fetch_vaddr ), // 1st cycle
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.is_speculative_i ( fetch_is_speculative ), // 1st cycle
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.data_o ( icache_data_d ),
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.req_i ( icache_req ),
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.kill_s1_i ( kill_s1 ),
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@ -438,11 +430,14 @@ module frontend #(
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.ready_o ( icache_ready ),
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.valid_o ( icache_valid_d ),
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.ex_o ( icache_ex_d ),
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.is_speculative_o ( icache_speculative_d ),
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.vaddr_o ( icache_vaddr_d ),
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.axi ( axi ),
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.miss_o ( l1_icache_miss_o ),
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.*
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.axi,
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.fetch_req_o,
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.fetch_vaddr_o,
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.fetch_valid_i,
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.fetch_paddr_i,
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.fetch_exception_i,
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.miss_o ( l1_icache_miss_o )
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);
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for (genvar i = 0; i < INSTR_PER_FETCH; i++) begin
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@ -25,14 +25,13 @@ module icache #(
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input logic clk_i,
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input logic rst_ni,
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input logic flush_i, // flush the icache, flush and kill have to be asserted together
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input logic en_cache_i, // cache accesses
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input logic req_i, // we request a new word
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input logic is_speculative_i, // is this request speculative or not
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input logic kill_s1_i, // kill the current request
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input logic kill_s2_i, // kill the last request
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output logic ready_o, // icache is ready
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input logic [63:0] vaddr_i, // 1st cycle: 12 bit index is taken for lookup
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output logic [FETCH_WIDTH-1:0] data_o, // 2+ cycle out: tag
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output logic is_speculative_o, // the fetch was speculative
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output logic [63:0] vaddr_o, // virtual address out
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output logic valid_o, // signals a valid read
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output exception_t ex_o, // we've encountered an exception
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@ -57,7 +56,6 @@ module icache #(
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logic [$clog2(ICACHE_NUM_WORD)-1:0] cnt_d, cnt_q;
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logic [NR_AXI_REFILLS-1:0] burst_cnt_d, burst_cnt_q; // counter for AXI transfers
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logic [63:0] vaddr_d, vaddr_q;
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logic spec_d, spec_q; // request is speculative
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logic [TAG_WIDTH-1:0] tag_d, tag_q;
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logic [SET_ASSOCIATIVITY-1:0] evict_way_d, evict_way_q;
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logic flushing_d, flushing_q;
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@ -202,19 +200,19 @@ module icache #(
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// ------------------
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// Cache Ctrl
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// ------------------
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// for bypassing we use the existing infrastructure of the cache
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// but on every access we are re-fetching the cache-line
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always_comb begin : cache_ctrl
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// default assignments
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state_d = state_q;
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cnt_d = cnt_q;
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vaddr_d = vaddr_q;
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spec_d = spec_q;
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tag_d = tag_q;
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evict_way_d = evict_way_q;
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flushing_d = flushing_q;
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burst_cnt_d = burst_cnt_q;
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is_speculative_o = spec_q;
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vaddr_o = vaddr_q;
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vaddr_o = vaddr_q;
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req = '0;
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addr = vaddr_i[INDEX_WIDTH-1:BYTE_OFFSET];
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@ -244,7 +242,6 @@ module icache #(
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req = '1;
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// save the virtual address
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vaddr_d = vaddr_i;
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spec_d = is_speculative_i;
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state_d = TAG_CMP;
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end
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@ -264,7 +261,7 @@ module icache #(
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// -------
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// Hit
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// -------
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if (|hit && fetch_valid_i) begin
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if (|hit && fetch_valid_i && (en_cache_i || (state_q != TAG_CMP))) begin
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ready_o = 1'b1;
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valid_o = 1'b1;
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// we've got another request
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@ -273,7 +270,6 @@ module icache #(
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req = '1;
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// save the index and stay in compare mode
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vaddr_d = vaddr_i;
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spec_d = is_speculative_i;
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state_d = TAG_CMP;
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// no new request -> go back to idle
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end else begin
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@ -287,7 +283,8 @@ module icache #(
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// -------
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end else begin
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state_d = REFILL;
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evict_way_d = '0;
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// hit gonna be zero in most cases except for when the cache is disabled
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evict_way_d = hit;
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// save tag
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tag_d = fetch_paddr_i[TAG_WIDTH+INDEX_WIDTH-1:INDEX_WIDTH];
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miss_o = 1'b1;
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@ -296,7 +293,7 @@ module icache #(
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evict_way_d = random_way;
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// shift the lfsr
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update_lfsr = 1'b1;
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end else begin
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end else if (!|hit) begin
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evict_way_d[repl_invalid] = 1'b1;
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end
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end
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@ -438,7 +435,6 @@ module icache #(
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tag_q <= '0;
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evict_way_q <= '0;
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flushing_q <= 1'b0;
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spec_q <= 1'b0;
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burst_cnt_q <= '0;;
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end else begin
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state_q <= state_d;
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@ -447,7 +443,6 @@ module icache #(
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tag_q <= tag_d;
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evict_way_q <= evict_way_d;
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flushing_q <= flushing_d;
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spec_q <= spec_d;
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burst_cnt_q <= burst_cnt_d;
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end
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end
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2
tb
2
tb
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@ -1 +1 @@
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Subproject commit d5605a06ecf7e2fa881c55f25870fdcef5433a48
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Subproject commit aaf24e628e73575705afa15ce5456af60ac26d0a
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