mirror of
https://github.com/openhwgroup/cva6.git
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Improve Spike - Ariane alignment
- Don't increment instret on exception - Align cycle counter with instret counter (-> IPC 1 as in Spike) - Add mock uart functionality - Make the preloading elf a plus-arg
This commit is contained in:
Florian Zaruba
parent
0d6e4fe658
commit
9db50883da
16 changed files with 210 additions and 76 deletions
38
Makefile
38
Makefile
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@ -128,6 +128,29 @@ list_incdir := $(foreach dir, ${incdir}, +incdir+$(dir))
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riscv-torture-dir := tmp/riscv-torture
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riscv-torture-bin := java -Xmx1G -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar
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ifdef batch-mode
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questa-flags += -c
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questa-cmd := -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]"
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else
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questa-cmd := -do " log -r /*; run -all;"
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endif
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# we want to preload the memories
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ifdef preload
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questa-cmd += +PRELOAD=$(preload)
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elf-bin = none
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# tandem verify with spike, this requires pre-loading
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ifdef tandem
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compile_flag += +define+TANDEM
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questa-cmd += -gblso tb/riscv-isa-sim/install/lib/libriscv.so
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endif
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endif
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# remote bitbang is enabled
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ifdef rbb
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questa-cmd += +jtag_rbb_enable=1
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else
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questa-cmd += +jtag_rbb_enable=0
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endif
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# Build the TB and module using QuestaSim
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build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ariane_dpi.so
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# Optimize top level
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@ -163,18 +186,9 @@ $(dpi-library)/ariane_dpi.so: $(dpi)
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sim: build
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vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -gblso tb/riscv-isa-sim/install/lib/libriscv.so -sv_lib $(dpi-library)/ariane_dpi -do "log -r /*;" \
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${top_level}_optimized +permissive-off ++$(riscv-test-dir)$(riscv-test) ++$(target-options)
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simc: build
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vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -gblso tb/riscv-isa-sim/install/lib/libriscv.so -sv_lib $(dpi-library)/ariane_dpi -do "log -r /*;" \
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${top_level}_optimized +permissive-off ++$(riscv-test-dir)$(riscv-test) ++$(target-options)
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vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
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${top_level}_optimized +permissive-off ++$(elf-bin) ++$(target-options) | tee sim.log
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$(riscv-asm-tests): build
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vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
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17
README.md
17
README.md
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@ -76,7 +76,7 @@ $ work-ver/Variane_testharness $RISCV/riscv64-unknown-elf/bin/pk hello.elf
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If you want to use QuestaSim to run it you can use the following command:
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```
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$ make simc riscv-test-dir=$RISCV/riscv64-unknown-elf/bin riscv-test=pk target-options=hello.elf
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$ make sim riscv-test-dir=$RISCV/riscv64-unknown-elf/bin riscv-test=pk target-options=hello.elf batch-mode=1
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```
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> Be patient! RTL simulation is way slower than Spike. If you think that you ran into problems you can inspect the trace files.
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@ -139,10 +139,10 @@ The core has been developed with a full licensed version of QuestaSim. If you ha
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To specify the test to run use (e.g.: you want to run `rv64ui-p-sraw` inside the `tmp/risc-tests/build/isa` folder:
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```
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$ make sim riscv-test=tmp/risc-tests/build/isa/rv64ui-p-sraw
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$ make sim riscv-test=tmp/risc-tests/build/isa/rv64ui-p-sraw make
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```
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If you call `simc` instead of `sim` it will run without the GUI. QuestaSim uses `riscv-fesvr` for communication as well.
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If you call `sim` with `batch-mode=1` it will run without the GUI. QuestaSim uses `riscv-fesvr` for communication as well.
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### CI Testsuites and Randomized Constrained Testing with Torture
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@ -186,6 +186,17 @@ $ make
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$ [sudo] make install
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```
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### Tandem Verification with Spike
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```
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$ make sim preload=/home/zarubaf/Downloads/riscv-tests/build/benchmarks/dhrystone.riscv tandem=1
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```
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There are a couple of limitations:
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- Memories should be initialized to zero.
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- UART needs to be replaced by a mock uart which exhibits always ready behavior.
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- There is no end of test signaling at the moment. You are supposed to kill the simulation when sufficiently long run.
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# Contributing
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Check out the [contribution guide](CONTRIBUTING.md)
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@ -60,7 +60,9 @@ package ariane_pkg;
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// enables a commit log which matches spikes commit log format for easier trace comparison
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localparam bit ENABLE_SPIKE_COMMIT_LOG = 1'b0;
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// enable performance cycle counter, if set to zero mcycle will be incremented
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// with instret (non RISC-V conformal)
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localparam bit ENABLE_CYCLE_COUNT = 1'b0;
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// ------------- Dangerouse -------------
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// if set to zero a flush will not invalidate the cache-lines, in a single core environment
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// where coherence is not necessary this can improve performance. This needs to be switched on
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@ -445,6 +445,7 @@ package riscv;
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byte rd;
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longint unsigned data;
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int unsigned instr;
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byte was_exception;
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} commit_log_t;
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endpackage
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@ -233,11 +233,14 @@ module csr_regfile #(
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cycle_d = cycle_q;
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instret_d = instret_q;
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if (!debug_mode_q) begin
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// just increment the cycle count
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cycle_d = cycle_q + 1'b1;
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// increase instruction retired counter
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for (int i = 0; i < NR_COMMIT_PORTS; i++) if (commit_ack_i[i]) instret++;
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for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
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if (commit_ack_i[i] && !ex_i.valid) instret++;
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end
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instret_d = instret;
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// increment the cycle count
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if (ENABLE_CYCLE_COUNT) cycle_d = cycle_q + 1'b1;
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else cycle_d = instret;
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end
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eret_o = 1'b0;
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@ -1 +1 @@
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Subproject commit 3e925e169bd02ebf26e3d4ab65cd1832319cf580
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Subproject commit a3ba269c0fc6cfcee6f81e5d9af018a08e479d2b
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@ -13,11 +13,11 @@
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// Date: 15.08.2018
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// Description: SRAM wrapper for FPGA (requires the fpga-support submodule)
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//
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// Note: the wrapped module contains two different implementations for
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// ALTERA and XILINX tools, since these follow different coding styles for
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// inferrable RAMS with byte enable. define `FPGA_TARGET_XILINX or
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// Note: the wrapped module contains two different implementations for
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// ALTERA and XILINX tools, since these follow different coding styles for
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// inferrable RAMS with byte enable. define `FPGA_TARGET_XILINX or
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// `FPGA_TARGET_ALTERA in your build environment (default is ALTERA)
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module sram #(
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parameter DATA_WIDTH = 64,
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parameter NUM_WORDS = 1024,
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@ -52,23 +52,24 @@ end
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genvar k;
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generate
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for (k = 0; k<(DATA_WIDTH+63)/64; k++) begin
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for (k = 0; k<(DATA_WIDTH+63)/64; k++) begin
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// unused byte-enable segments (8bits) are culled by the tool
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SyncSpRamBeNx64 #(
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.ADDR_WIDTH($clog2(NUM_WORDS)),
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.DATA_DEPTH(NUM_WORDS),
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.OUT_REGS (0)
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.DATA_DEPTH(NUM_WORDS),
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.OUT_REGS (0),
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.SIM_INIT (1)
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) i_ram (
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.Clk_CI ( clk_i ),
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.Rst_RBI ( rst_ni ),
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.CSel_SI ( req_i ),
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.WrEn_SI ( we_i ),
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.BEn_SI ( be_aligned[k*8 +: 8] ),
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.WrData_DI ( wdata_aligned[k*64 +: 64] ),
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.Addr_DI ( addr_i ),
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.WrData_DI ( wdata_aligned[k*64 +: 64] ),
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.Addr_DI ( addr_i ),
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.RdData_DO ( rdata_aligned[k*64 +: 64] )
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);
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end
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);
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end
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endgenerate
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endmodule : sram
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@ -54,13 +54,22 @@ module ariane_tb;
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.exit_o
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);
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// `ifdef TANDEM
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// initial $display("Tandem defined",);
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spike i_spike (
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.clk_i,
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.rst_ni,
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.clint_tick_i ( dut.i_clint.rtc_i ),
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.commit_instr_i ( dut.i_ariane.commit_instr_id_commit ),
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.commit_ack_i ( dut.i_ariane.commit_ack )
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.commit_ack_i ( dut.i_ariane.commit_ack ),
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.exception_i ( dut.i_ariane.ex_commit ),
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.waddr_i ( dut.i_ariane.waddr_commit_id ),
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.wdata_i ( dut.i_ariane.wdata_commit_id ),
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.priv_lvl_i ( dut.i_ariane.priv_lvl )
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);
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// `else
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// initial $display("Tandem not defined",);
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// `endif
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// Clock process
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initial begin
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@ -110,12 +119,12 @@ module ariane_tb;
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byte buffer[];
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void'(uvcl.get_arg_value("+PRELOAD=", binary));
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binary = "/home/zarubaf/riscv/target/share/riscv-tests/benchmarks/dhrystone.riscv";
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if (binary != "") begin
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`uvm_info( "Core Test", $sformatf("Preloading ELF: %s", binary), UVM_LOW)
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void'(read_elf(binary));
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// wait with preloading, otherwise randomization will overwrite the existing value
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wait(rst_ni);
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// while there are more sections to process
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while (get_section(address, len)) begin
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@ -10,7 +10,7 @@
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//
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// Author: Florian Zaruba, ETH Zurich
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// Date: 28/09/2018
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// Description: Mock replacement for UART in testbench
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// Description: Mock replacement for UART in testbench (not synthesiesable!)
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module mock_uart (
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input logic clk_i,
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@ -24,6 +24,32 @@ module mock_uart (
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output logic pready_o,
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output logic pslverr_o
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);
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localparam RBR 0
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localparam THR 0
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localparam IER 1
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localparam IIR 2
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localparam FCR 2
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localparam LCR 3
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localparam MCR 4
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localparam LSR 5
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localparam MSR 6
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localparam SCR 7
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localparam DLL 0
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localparam DLM 1
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localparam THRE 5 // transmit holding register empty
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localparam TEMT 6 // transmit holding register empty
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byte lcr = 0;
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byte dlm = 0;
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byte dll = 0;
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byte mcr = 0;
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byte lsr = 0;
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byte ier = 0;
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byte msr = 0;
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byte scr = 0;
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logic fifo_enabled = 1'b0;
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// string buffer
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byte buffer [$];
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@ -54,7 +80,48 @@ module mock_uart (
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (rst_ni) begin
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if (psel_i & penable_i & pwrite_i & paddr_i[3:0] == 'h4) append(byte'(pwdata_i[7:0]));
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if (psel_i & penable_i & pwrite_i & (paddr_i >> 2)) begin
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case ((paddr_i >> 'h2) & 'h7)
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THR: begin
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if (lcr & 'h80) dll = byte'(pwdata_i[7:0]);
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else append(byte'(pwdata_i[7:0]));
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end
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IER: begin
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if (lcr & 'h80) dlm = byte'(pwdata_i[7:0]);
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else ier = byte'(pwdata_i[7:0] & 'hF)
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end
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FCR: begin
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if (pwdata_i[0]) fifo_enabled = 1'b1;
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else fifo_enabled = 1'b0;
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end
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LCR: lcr = byte'(pwdata_i[7:0]);
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MCR: mcr = byte'(pwdata_i[7:0] & 'h1F);
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LSR: lsr = byte'(pwdata_i[7:0]);
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MSR: msr = byte'(pwdata_i[7:0]);
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SCR: scr = byte'(pwdata_i[7:0]);
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default:;
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endcase
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end else if (psel_i & penable_i & ~pwrite_i) begin
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case ((paddr_i >> 'h2) & 'h7)
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THR: begin
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if (lcr & 'h80) prdata_o = {24'b0, dll};
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end
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IER: begin
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if (lcr & 'h80) prdata_o = {24'b0, dlm};
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else ier = prdata_o = {24'b0, ier};
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end
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IIR: begin
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if (fifo_enabled) prdata_o = {24'b0, 8'hc0};
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else prdata_o = {24'b0, 8'b0};
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end
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LCR: prdata_o = {24'b0, lcr};
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MCR: prdata_o = {24'b0, mcr};
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LSR: prdata_o = {24'b0, (lsr | (1 << THRE) | (1 << TEMT))};
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MSR: prdata_o = {24'b0, msr};
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SCR: prdata_o = {24'b0, scr};
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default:;
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endcase
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end
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end
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end
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endmodule
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@ -12,6 +12,14 @@
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// Date: 3/11/2018
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// Description: Wrapped Spike Model for Tandem Verification
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import uvm_pkg::*;
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`include "uvm_macros.svh"
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import "DPI-C" function int spike_create(string filename, longint unsigned dram_base, int unsigned size);
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import "DPI-C" function void spike_tick(output riscv::commit_log_t commit_log);
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import "DPI-C" function void clint_tick();
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module spike #(
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parameter longint unsigned DramBase = 'h8000_0000,
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parameter int unsigned Size = 64 * 1024 * 1024 // 64 Mega Byte
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@ -20,16 +28,20 @@ module spike #(
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input logic rst_ni,
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input logic clint_tick_i,
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input ariane_pkg::scoreboard_entry_t [ariane_pkg::NR_COMMIT_PORTS-1:0] commit_instr_i,
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input logic [ariane_pkg::NR_COMMIT_PORTS-1:0] commit_ack_i
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input logic [ariane_pkg::NR_COMMIT_PORTS-1:0] commit_ack_i,
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input ariane_pkg::exception_t exception_i,
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input logic [ariane_pkg::NR_COMMIT_PORTS-1:0][4:0] waddr_i,
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input logic [ariane_pkg::NR_COMMIT_PORTS-1:0][63:0] wdata_i,
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input riscv::priv_lvl_t priv_lvl_i
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);
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// Create a spike simulation object with base at dram_base and size (in bytes).
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// Bytes must be page aligned.
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import "DPI-C" function int spike_create(string filename, longint unsigned dram_base, int unsigned size);
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import "DPI-C" function void spike_tick(output riscv::commit_log_t commit_log);
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import "DPI-C" function void clint_tick();
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static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst();
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string binary = "";
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initial begin
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void'(spike_create("/home/zarubaf/riscv/target/share/riscv-tests/benchmarks/dhrystone.riscv", DramBase, Size));
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void'(uvcl.get_arg_value("+PRELOAD=", binary));
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assert(binary != "") else $error("We need a preloaded binary for tandem verification");
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void'(spike_create(binary, DramBase, Size));
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end
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riscv::commit_log_t commit_log;
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@ -40,8 +52,39 @@ module spike #(
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if (commit_instr_i[i].valid && commit_ack_i[i]) begin
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spike_tick(commit_log);
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instr = (commit_log.instr[1:0] != 2'b11) ? {16'b0, commit_log.instr[15:0]} : commit_log.instr;
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$display("\x1B[32m%h %h\x1B[0m", commit_log.pc, instr);
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$display("\x1B[37m%h %h\x1B[0m", commit_instr_i[i].pc, commit_instr_i[i].ex.tval[31:0]);
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// $display("\x1B[32m%h %h\x1B[0m", commit_log.pc, instr);
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// $display("%p", commit_log);
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// $display("\x1B[37m%h %h\x1B[0m", commit_instr_i[i].pc, commit_instr_i[i].ex.tval[31:0]);
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assert (commit_log.pc === commit_instr_i[i].pc) else begin
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$warning("\x1B[33m[Tandem] PCs Mismatch\x1B[0m");
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end
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assert (commit_log.was_exception === exception_i.valid) else begin
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$warning("\x1B[33m[Tandem] Exception not detected\x1B[0m");
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$display("Spike: %p", commit_log);
|
||||
$display("Ariane: %p", commit_instr_i[i]);
|
||||
end
|
||||
assert (commit_log.priv === priv_lvl_i) else begin
|
||||
$warning("\x1B[33m[Tandem] Privilege level mismatches\x1B[0m");
|
||||
$display("\x1B[37m @ PC %h\x1B[0m", commit_log.pc);
|
||||
end
|
||||
if (!exception_i.valid) begin
|
||||
assert (instr === commit_instr_i[i].ex.tval) else begin
|
||||
$warning("\x1B[33m[Tandem] Decoded instructions mismatch\x1B[0m");
|
||||
$display("\x1B[37m%h === %h @ PC %h\x1B[0m", commit_instr_i[i].ex.tval, instr, commit_log.pc);
|
||||
end
|
||||
// TODO(zarubaf): Adapt for floating point instructions
|
||||
if (commit_instr_i[i].rd != 0) begin
|
||||
// check the return value
|
||||
// $display("\x1B[37m%h === %h\x1B[0m", commit_instr_i[i].rd, commit_log.rd);
|
||||
assert (waddr_i[i] === commit_log.rd) else begin
|
||||
$warning("\x1B[33m[Tandem] Destination register mismatches\x1B[0m");
|
||||
end
|
||||
assert (wdata_i[i] === commit_log.data) else begin
|
||||
$warning("\x1B[33m[Tandem] Write back data mismatches\x1B[0m");
|
||||
$display("\x1B[37m%h === %h @ PC %h\x1B[0m", wdata_i[i], commit_log.data, commit_log.pc);
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
|||
|
|
@ -57,27 +57,14 @@ commit_log_t sim_spike_t::tick(size_t n)
|
|||
int xlen = procs[0]->get_state()->last_inst_xlen;
|
||||
int flen = procs[0]->get_state()->last_inst_flen;
|
||||
|
||||
// fprintf(stderr, "%1d ", priv);
|
||||
// fprintf(stderr, "%lx ", pc);
|
||||
// fprintf(stderr, "%lx ", xlen);
|
||||
// fprintf(stderr, "%1d ", fp);
|
||||
// fprintf(stderr, "%c%d ", fp ? 'f' : 'x', rd);
|
||||
if (procs[0]->get_state()->rd) {
|
||||
bool fp = procs[0]->get_state()->rd & 1;
|
||||
int rd = procs[0]->get_state()->rd >> 1;
|
||||
int size = fp ? flen : xlen;
|
||||
// fprintf(stderr, "%c%2d ", fp ? 'f' : 'x', rd);
|
||||
// fprintf(stderr, "0x%016" PRIx64 "\n", reg.data.v[0]);
|
||||
// fprintf(stderr, "\n");
|
||||
} else {
|
||||
// fprintf(stderr, "\n");
|
||||
}
|
||||
commit_log.priv = priv;
|
||||
commit_log.pc = pc;
|
||||
commit_log.is_fp = procs[0]->get_state()->rd & 1;
|
||||
commit_log.rd = procs[0]->get_state()->rd >> 2;
|
||||
commit_log.is_fp = reg.addr & 1;
|
||||
commit_log.rd = reg.addr >> 1;
|
||||
commit_log.data = reg.data.v[0];
|
||||
commit_log.instr = procs[0]->get_state()->last_insn;
|
||||
commit_log.was_exception = procs[0]->get_state()->was_exception;
|
||||
|
||||
return commit_log;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@ typedef struct
|
|||
char rd;
|
||||
uint64_t data;
|
||||
uint32_t instr;
|
||||
char was_exception;
|
||||
} commit_log_t;
|
||||
|
||||
// this class encapsulates the processors and memory in a RISC-V machine.
|
||||
|
|
|
|||
|
|
@ -29,8 +29,6 @@ commit_log_t commit_log_val;
|
|||
#define SHT_GROUP 0x11
|
||||
|
||||
void write_spike_mem (reg_t address, size_t len, uint8_t* buf) {
|
||||
fprintf(stderr, "Storing: %llx\n", address);
|
||||
|
||||
memcpy(mem[0].second->contents() + (address & ~(1 << 31)), buf,len);
|
||||
}
|
||||
|
||||
|
|
@ -126,6 +124,7 @@ extern "C" void spike_tick(commit_log_t* commit_log)
|
|||
commit_log->rd = commit_log_val.rd;
|
||||
commit_log->data = commit_log_val.data;
|
||||
commit_log->instr = commit_log_val.instr;
|
||||
commit_log->was_exception = commit_log_val.was_exception;
|
||||
}
|
||||
|
||||
extern "C" void clint_tick()
|
||||
|
|
|
|||
|
|
@ -43,24 +43,13 @@ static void commit_log_print_insn(state_t* state, reg_t pc, insn_t insn)
|
|||
int xlen = state->last_inst_xlen;
|
||||
int flen = state->last_inst_flen;
|
||||
|
||||
state->rd = reg.addr;
|
||||
state->last_insn = insn.bits();
|
||||
// fprintf(stderr, "%1d ", priv);
|
||||
// commit_log_print_value(xlen, 0, pc);
|
||||
// fprintf(stderr, " (");
|
||||
// commit_log_print_value(insn.length() * 8, 0, insn.bits());
|
||||
|
||||
if (reg.addr) {
|
||||
bool fp = reg.addr & 1;
|
||||
int rd = reg.addr >> 1;
|
||||
int size = fp ? flen : xlen;
|
||||
// fprintf(stderr, ") %c%2d ", fp ? 'f' : 'x', rd);
|
||||
// commit_log_print_value(size, reg.data.v[1], reg.data.v[0]);
|
||||
// fprintf(stderr, "\n");
|
||||
} else {
|
||||
// fprintf(stderr, ")\n");
|
||||
}
|
||||
reg.addr = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -93,6 +82,9 @@ bool processor_t::slow_path()
|
|||
// fetch/decode/execute loop
|
||||
void processor_t::step(size_t n)
|
||||
{
|
||||
#ifdef RISCV_ENABLE_COMMITLOG
|
||||
state.was_exception = false;
|
||||
#endif
|
||||
if (state.dcsr.cause == DCSR_CAUSE_NONE) {
|
||||
if (halt_request) {
|
||||
enter_debug_mode(DCSR_CAUSE_DEBUGINT);
|
||||
|
|
@ -210,6 +202,9 @@ void processor_t::step(size_t n)
|
|||
}
|
||||
catch(trap_t& t)
|
||||
{
|
||||
#ifdef RISCV_ENABLE_COMMITLOG
|
||||
state.was_exception = true;
|
||||
#endif
|
||||
take_trap(t, pc);
|
||||
n = instret;
|
||||
|
||||
|
|
|
|||
|
|
@ -143,8 +143,8 @@ struct state_t
|
|||
reg_t last_inst_priv;
|
||||
int last_inst_xlen;
|
||||
int last_inst_flen;
|
||||
reg_t rd;
|
||||
uint32_t last_insn;
|
||||
bool was_exception;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@ bool uart_t::load(reg_t addr, size_t len, uint8_t* bytes)
|
|||
if (lcr & 0x80) {
|
||||
bytes[0] = dll;
|
||||
} else {
|
||||
// TODO(zarubaf)
|
||||
// printf("%c", bytes[0]);
|
||||
}
|
||||
break;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue