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https://github.com/openhwgroup/cva6.git
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Update submodule core/cache_subsystem/hpdcache (#2265)
This commit is contained in:
Cesar Fuguet
GitHub
parent
c78ede91f9
commit
9df64701bd
5 changed files with 32 additions and 34 deletions
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@ -18,7 +18,7 @@ iterations = None
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# Will fail if the number of cycles is different from this one
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valid_cycles = {
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'dhrystone': 217900,
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'coremark': 686479,
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'coremark': 686072,
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}
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for arg in sys.argv[1:]:
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@ -14,7 +14,7 @@ module cva6_hpdcache_if_adapter
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// {{{
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#(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter hpdcache_pkg::hpdcache_cfg_t hpdcacheCfg = '0,
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parameter hpdcache_pkg::hpdcache_cfg_t HPDcacheCfg = '0,
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parameter type hpdcache_tag_t = logic,
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parameter type hpdcache_req_offset_t = logic,
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parameter type hpdcache_req_sid_t = logic,
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@ -120,8 +120,8 @@ module cva6_hpdcache_if_adapter
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// {{{
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always_comb begin : amo_op_comb
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amo_addr = cva6_amo_req_i.operand_a;
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amo_addr_offset = amo_addr[0+:hpdcacheCfg.reqOffsetWidth];
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amo_tag = amo_addr[hpdcacheCfg.reqOffsetWidth+:hpdcacheCfg.tagWidth];
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amo_addr_offset = amo_addr[0+:HPDcacheCfg.reqOffsetWidth];
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amo_tag = amo_addr[HPDcacheCfg.reqOffsetWidth+:HPDcacheCfg.tagWidth];
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unique case (cva6_amo_req_i.amo_op)
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ariane_pkg::AMO_LR: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_LR;
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ariane_pkg::AMO_SC: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_SC;
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@ -189,7 +189,7 @@ module cva6_hpdcache_subsystem
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// NumPorts + 1: Hardware Memory Prefetcher (hwpf)
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localparam int HPDCACHE_NREQUESTERS = NumPorts + 2;
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localparam hpdcache_pkg::hpdcache_user_cfg_t hpdcacheUserCfg = '{
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localparam hpdcache_pkg::hpdcache_user_cfg_t HPDcacheUserCfg = '{
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nRequesters: HPDCACHE_NREQUESTERS,
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paWidth: CVA6Cfg.PLEN,
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wordWidth: CVA6Cfg.XLEN,
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@ -223,12 +223,12 @@ module cva6_hpdcache_subsystem
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memDataWidth: CVA6Cfg.AxiDataWidth
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};
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localparam hpdcache_pkg::hpdcache_cfg_t hpdcacheCfg = hpdcache_pkg::hpdcacheBuildConfig(
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hpdcacheUserCfg
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localparam hpdcache_pkg::hpdcache_cfg_t HPDcacheCfg = hpdcache_pkg::hpdcacheBuildConfig(
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HPDcacheUserCfg
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);
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`HPDCACHE_TYPEDEF_MEM_ATTR_T(hpdcache_mem_addr_t, hpdcache_mem_id_t, hpdcache_mem_data_t,
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hpdcache_mem_be_t, hpdcacheCfg);
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hpdcache_mem_be_t, HPDcacheCfg);
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`HPDCACHE_TYPEDEF_MEM_REQ_T(hpdcache_mem_req_t, hpdcache_mem_addr_t, hpdcache_mem_id_t);
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`HPDCACHE_TYPEDEF_MEM_RESP_R_T(hpdcache_mem_resp_r_t, hpdcache_mem_id_t, hpdcache_mem_data_t);
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`HPDCACHE_TYPEDEF_MEM_REQ_W_T(hpdcache_mem_req_w_t, hpdcache_mem_data_t, hpdcache_mem_be_t);
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@ -236,14 +236,14 @@ module cva6_hpdcache_subsystem
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`HPDCACHE_TYPEDEF_REQ_ATTR_T(hpdcache_req_offset_t, hpdcache_data_word_t, hpdcache_data_be_t,
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hpdcache_req_data_t, hpdcache_req_be_t, hpdcache_req_sid_t,
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hpdcache_req_tid_t, hpdcache_tag_t, hpdcacheCfg);
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hpdcache_req_tid_t, hpdcache_tag_t, HPDcacheCfg);
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`HPDCACHE_TYPEDEF_REQ_T(hpdcache_req_t, hpdcache_req_offset_t, hpdcache_req_data_t,
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hpdcache_req_be_t, hpdcache_req_sid_t, hpdcache_req_tid_t,
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hpdcache_tag_t);
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`HPDCACHE_TYPEDEF_RSP_T(hpdcache_rsp_t, hpdcache_req_data_t, hpdcache_req_sid_t,
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hpdcache_req_tid_t);
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typedef logic [hpdcacheCfg.u.wbufTimecntWidth-1:0] hpdcache_wbuf_timecnt_t;
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typedef logic [HPDcacheCfg.u.wbufTimecntWidth-1:0] hpdcache_wbuf_timecnt_t;
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logic dcache_miss_ready;
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logic dcache_miss_valid;
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@ -287,7 +287,7 @@ module cva6_hpdcache_subsystem
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cva6_hpdcache_wrapper #(
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.CVA6Cfg(CVA6Cfg),
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.hpdcacheCfg(hpdcacheCfg),
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.HPDcacheCfg(HPDcacheCfg),
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.dcache_req_i_t(dcache_req_i_t),
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.dcache_req_o_t(dcache_req_o_t),
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.NumPorts(NumPorts),
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@ -467,13 +467,13 @@ module cva6_hpdcache_subsystem
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// {{{
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// pragma translate_off
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initial begin : initial_assertions
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assert (hpdcacheCfg.u.reqSrcIdWidth >= $clog2(HPDCACHE_NREQUESTERS))
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assert (HPDcacheCfg.u.reqSrcIdWidth >= $clog2(HPDCACHE_NREQUESTERS))
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else $fatal(1, "HPDCACHE_REQ_SRC_ID_WIDTH is not wide enough");
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assert (CVA6Cfg.MEM_TID_WIDTH <= CVA6Cfg.AxiIdWidth)
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else $fatal(1, "MEM_TID_WIDTH shall be less or equal to the AxiIdWidth");
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assert (CVA6Cfg.MEM_TID_WIDTH >= ($clog2(hpdcacheCfg.u.mshrSets * hpdcacheCfg.u.mshrWays) + 1))
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assert (CVA6Cfg.MEM_TID_WIDTH >= ($clog2(HPDcacheCfg.u.mshrSets * HPDcacheCfg.u.mshrWays) + 1))
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else $fatal(1, "MEM_TID_WIDTH shall allow to uniquely identify all D$ and I$ miss requests ");
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assert (CVA6Cfg.MEM_TID_WIDTH >= ($clog2(hpdcacheCfg.u.wbufDirEntries) + 1))
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assert (CVA6Cfg.MEM_TID_WIDTH >= ($clog2(HPDcacheCfg.u.wbufDirEntries) + 1))
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else $fatal(1, "MEM_TID_WIDTH shall allow to uniquely identify all D$ write requests ");
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end
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@ -8,9 +8,7 @@
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//
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// Authors: Cesar Fuguet
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// Date: February, 2023
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// Description: CVA6 cache subsystem integrating standard CVA6's
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// instruction cache and the Core-V High-Performance L1
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// data cache (CV-HPDcache).
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// Description: Wrapper for the Core-V High-Performance L1 data cache (CV-HPDcache)
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`include "hpdcache_typedef.svh"
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@ -19,7 +17,7 @@ module cva6_hpdcache_wrapper
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// {{{
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#(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter hpdcache_pkg::hpdcache_cfg_t hpdcacheCfg, // TODO
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parameter hpdcache_pkg::hpdcache_cfg_t HPDcacheCfg,
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parameter type dcache_req_i_t = logic,
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parameter type dcache_req_o_t = logic,
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parameter int NumPorts = 4,
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@ -153,14 +151,14 @@ module cva6_hpdcache_wrapper
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typedef logic [63:0] hwpf_stride_param_t;
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logic dcache_req_valid[HPDCACHE_NREQUESTERS-1:0];
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logic dcache_req_ready[HPDCACHE_NREQUESTERS-1:0];
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hpdcache_req_t dcache_req [HPDCACHE_NREQUESTERS-1:0];
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logic dcache_req_abort[HPDCACHE_NREQUESTERS-1:0];
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hpdcache_tag_t dcache_req_tag [HPDCACHE_NREQUESTERS-1:0];
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hpdcache_pkg::hpdcache_pma_t dcache_req_pma [HPDCACHE_NREQUESTERS-1:0];
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logic dcache_rsp_valid[HPDCACHE_NREQUESTERS-1:0];
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hpdcache_rsp_t dcache_rsp [HPDCACHE_NREQUESTERS-1:0];
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logic dcache_req_valid[HPDCACHE_NREQUESTERS];
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logic dcache_req_ready[HPDCACHE_NREQUESTERS];
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hpdcache_req_t dcache_req [HPDCACHE_NREQUESTERS];
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logic dcache_req_abort[HPDCACHE_NREQUESTERS];
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hpdcache_tag_t dcache_req_tag [HPDCACHE_NREQUESTERS];
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hpdcache_pkg::hpdcache_pma_t dcache_req_pma [HPDCACHE_NREQUESTERS];
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logic dcache_rsp_valid[HPDCACHE_NREQUESTERS];
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hpdcache_rsp_t dcache_rsp [HPDCACHE_NREQUESTERS];
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logic dcache_read_miss, dcache_write_miss;
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logic [ 2:0] snoop_valid;
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@ -175,14 +173,14 @@ module cva6_hpdcache_wrapper
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hwpf_stride_pkg::hwpf_stride_throttle_t [NrHwPrefetchers-1:0] hwpf_throttle_out;
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generate
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dcache_req_i_t dcache_req_ports[HPDCACHE_NREQUESTERS-1:0];
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dcache_req_i_t dcache_req_ports[NumPorts - 1];
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for (genvar r = 0; r < (NumPorts - 1); r++) begin : gen_cva6_hpdcache_load_if_adapter
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assign dcache_req_ports[r] = dcache_req_ports_i[r];
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cva6_hpdcache_if_adapter #(
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.CVA6Cfg (CVA6Cfg),
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.hpdcacheCfg (hpdcacheCfg),
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.HPDcacheCfg (HPDcacheCfg),
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.hpdcache_tag_t (hpdcache_tag_t),
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.hpdcache_req_offset_t(hpdcache_req_offset_t),
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.hpdcache_req_sid_t (hpdcache_req_sid_t),
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@ -216,7 +214,7 @@ module cva6_hpdcache_wrapper
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cva6_hpdcache_if_adapter #(
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.CVA6Cfg (CVA6Cfg),
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.hpdcacheCfg (hpdcacheCfg),
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.HPDcacheCfg (HPDcacheCfg),
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.hpdcache_tag_t (hpdcache_tag_t),
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.hpdcache_req_offset_t(hpdcache_req_offset_t),
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.hpdcache_req_sid_t (hpdcache_req_sid_t),
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@ -315,13 +313,13 @@ module cva6_hpdcache_wrapper
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generate
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for (genvar h = 0; h < NrHwPrefetchers; h++) begin : gen_hwpf_throttle
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assign hwpf_throttle_in[h] = hwpf_stride_pkg::hwpf_stride_throttle_t'(hwpf_throttle_i[h]),
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hwpf_throttle_o[h] = hwpf_stride_pkg::hwpf_stride_param_t'(hwpf_throttle_out[h]);
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assign hwpf_throttle_in[h] = hwpf_stride_pkg::hwpf_stride_throttle_t'(hwpf_throttle_i[h]);
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assign hwpf_throttle_o[h] = hwpf_stride_pkg::hwpf_stride_param_t'(hwpf_throttle_out[h]);
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end
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endgenerate
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hwpf_stride_wrapper #(
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.hpdcacheCfg (hpdcacheCfg),
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.HPDcacheCfg (HPDcacheCfg),
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.NUM_HW_PREFETCH (NrHwPrefetchers),
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.NUM_SNOOP_PORTS (3),
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.hpdcache_tag_t (hpdcache_tag_t),
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@ -366,7 +364,7 @@ module cva6_hpdcache_wrapper
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);
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hpdcache #(
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.hpdcacheCfg (hpdcacheCfg),
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.HPDcacheCfg (HPDcacheCfg),
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.wbuf_timecnt_t (hpdcache_wbuf_timecnt_t),
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.hpdcache_tag_t (hpdcache_tag_t),
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.hpdcache_data_word_t (hpdcache_data_word_t),
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@ -1 +1 @@
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Subproject commit 32407cb8f69b71824083abd72b2d4e8bcd0c2f01
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Subproject commit 25ffa3438c8150fef791dd165234694a51e3c529
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