mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-20 04:07:36 -04:00
fix some bad assignments and lint warning related to RVFI feature (#1947)
This commit is contained in:
Yannick Casamatta
GitHub
parent
c76b29a887
commit
9ecdaa1408
2 changed files with 87 additions and 38 deletions
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@ -31,15 +31,8 @@ module cva6_rvfi
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);
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// ------------------------------------------
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// CVA6 configuration
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// ------------------------------------------
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// Extended config
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localparam bit RVF = (CVA6Cfg.IS_XLEN64 | CVA6Cfg.IS_XLEN32) & CVA6Cfg.FpuEn;
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localparam bit RVD = (CVA6Cfg.IS_XLEN64 ? 1 : 0) & CVA6Cfg.FpuEn;
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localparam bit FpPresent = RVF | RVD | CVA6Cfg.XF16 | CVA6Cfg.XF16ALT | CVA6Cfg.XF8;
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localparam logic [CVA6Cfg.XLEN-1:0] IsaCode = (CVA6Cfg.XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension
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localparam logic [CVA6Cfg.XLEN-1:0] IsaCode =
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(CVA6Cfg.XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension
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| (CVA6Cfg.XLEN'(CVA6Cfg.RVB) << 1) // C - Bitmanip extension
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| (CVA6Cfg.XLEN'(CVA6Cfg.RVC) << 2) // C - Compressed extension
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| (CVA6Cfg.XLEN'(CVA6Cfg.RVD) << 3) // D - Double precision floating-point extension
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@ -74,7 +67,7 @@ module cva6_rvfi
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logic [CVA6Cfg.XLEN-1:0] rs2_forwarding;
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logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.VLEN-1:0] commit_instr_pc;
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fu_op [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] commit_instr_op;
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fu_op [CVA6Cfg.NrCommitPorts-1:0] commit_instr_op;
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logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rs1;
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logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rs2;
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logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rd;
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@ -246,7 +239,7 @@ module cva6_rvfi
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always_comb begin
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for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
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logic exception;
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exception = commit_instr_valid[i] && ex_commit_valid;
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exception = commit_instr_valid[i][0] && ex_commit_valid;
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rvfi_instr_o[i].valid = (commit_ack[i] && !ex_commit_valid) ||
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(exception && (ex_commit_cause == riscv::ENV_CALL_MMODE ||
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ex_commit_cause == riscv::ENV_CALL_SMODE ||
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@ -260,7 +253,7 @@ module cva6_rvfi
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rvfi_instr_o[i].rs1_addr = commit_instr_rs1[i][4:0];
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rvfi_instr_o[i].rs2_addr = commit_instr_rs2[i][4:0];
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rvfi_instr_o[i].rd_addr = commit_instr_rd[i][4:0];
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rvfi_instr_o[i].rd_wdata = (FpPresent && is_rd_fpr(commit_instr_op[i])) ?
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rvfi_instr_o[i].rd_wdata = (CVA6Cfg.FpPresent && is_rd_fpr(commit_instr_op[i])) ?
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commit_instr_result[i] : wdata[i];
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rvfi_instr_o[i].pc_rdata = commit_instr_pc[i];
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rvfi_instr_o[i].mem_addr = mem_q[commit_pointer[i]].lsu_addr;
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@ -284,27 +277,47 @@ module cva6_rvfi
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always_comb begin
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rvfi_csr_o.fflags = CVA6Cfg.FpPresent ?
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'{rdata: {'0, csr.fcsr_q.fflags}, wdata: {'0, csr.fcsr_q.fflags}, rmask: '1, wmask: '1}
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'{
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rdata: {{CVA6Cfg.XLEN - 5{1'b0}}, csr.fcsr_q.fflags},
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wdata: {{CVA6Cfg.XLEN - 5{1'b0}}, csr.fcsr_q.fflags},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.frm = CVA6Cfg.FpPresent ?
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'{rdata: {'0, csr.fcsr_q.frm}, wdata: {'0, csr.fcsr_q.frm}, rmask: '1, wmask: '1}
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'{
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rdata: {{CVA6Cfg.XLEN - 3{1'b0}}, csr.fcsr_q.frm},
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wdata: {{CVA6Cfg.XLEN - 3{1'b0}}, csr.fcsr_q.frm},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.fcsr = CVA6Cfg.FpPresent ?
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'{
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rdata: {'0, csr.fcsr_q.frm, csr.fcsr_q.fflags},
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wdata: {'0, csr.fcsr_q.frm, csr.fcsr_q.fflags},
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rdata: {{CVA6Cfg.XLEN - 8{1'b0}}, csr.fcsr_q.frm, csr.fcsr_q.fflags},
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wdata: {{CVA6Cfg.XLEN - 8{1'b0}}, csr.fcsr_q.frm, csr.fcsr_q.fflags},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.ftran = CVA6Cfg.FpPresent ?
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'{rdata: {'0, csr.fcsr_q.fprec}, wdata: {'0, csr.fcsr_q.fprec}, rmask: '1, wmask: '1}
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'{
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rdata: {{CVA6Cfg.XLEN - 7{1'b0}}, csr.fcsr_q.fprec},
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wdata: {{CVA6Cfg.XLEN - 7{1'b0}}, csr.fcsr_q.fprec},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.dcsr = CVA6Cfg.DebugEn ?
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'{rdata: {'0, csr.dcsr_q}, wdata: {'0, csr.dcsr_q}, rmask: '1, wmask: '1}
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'{
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.dcsr_q},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.dcsr_q},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.dpc = CVA6Cfg.DebugEn ?
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'{rdata: {csr.dpc_q}, wdata: csr.dpc_q, rmask: '1, wmask: '1}
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'{rdata: csr.dpc_q, wdata: csr.dpc_q, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.dscratch0 = CVA6Cfg.DebugEn ?
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'{rdata: csr.dscratch0_q, wdata: csr.dscratch0_q, rmask: '1, wmask: '1}
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@ -377,8 +390,8 @@ module cva6_rvfi
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rvfi_csr_o.mtval = '{rdata: csr.mtval_q, wdata: csr.mtval_q, rmask: '1, wmask: '1};
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rvfi_csr_o.mip = '{rdata: csr.mip_q, wdata: csr.mip_q, rmask: '1, wmask: '1};
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rvfi_csr_o.menvcfg = '{
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rdata: {'0, csr.fiom_q},
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wdata: {'0, csr.fiom_q},
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rdata: {{CVA6Cfg.XLEN - 1{1'b0}}, csr.fiom_q},
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wdata: {{CVA6Cfg.XLEN - 1{1'b0}}, csr.fiom_q},
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rmask: '1,
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wmask: '1
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};
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@ -386,16 +399,22 @@ module cva6_rvfi
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'{rdata: '0, wdata: '0, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.mvendorid = '{
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rdata: OPENHWGROUP_MVENDORID,
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wdata: OPENHWGROUP_MVENDORID,
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, OPENHWGROUP_MVENDORID},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, OPENHWGROUP_MVENDORID},
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rmask: '1,
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wmask: '1
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};
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rvfi_csr_o.marchid = '{rdata: ARIANE_MARCHID, wdata: ARIANE_MARCHID, rmask: '1, wmask: '1};
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rvfi_csr_o.marchid = '{
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, ARIANE_MARCHID},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, ARIANE_MARCHID},
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rmask: '1,
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wmask: '1
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};
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rvfi_csr_o.mhartid = '{rdata: hart_id_i, wdata: hart_id_i, rmask: '1, wmask: '1};
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rvfi_csr_o.mcountinhibit = '{
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rdata: {'0, csr.mcountinhibit_q},
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wdata: {'0, csr.mcountinhibit_q},
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rdata: {{(CVA6Cfg.XLEN - (MHPMCounterNum + 3)) {1'b0}}, csr.mcountinhibit_q},
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wdata: {{(CVA6Cfg.XLEN - (MHPMCounterNum + 3)) {1'b0}}, csr.mcountinhibit_q},
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rmask: '1,
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wmask: '1
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};
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@ -406,7 +425,12 @@ module cva6_rvfi
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wmask: '1
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};
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rvfi_csr_o.mcycleh = CVA6Cfg.XLEN == 32 ?
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'{rdata: csr.cycle_q[63:32], wdata: csr.cycle_q[63:32], rmask: '1, wmask: '1}
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'{
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.cycle_q[63:32]},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.cycle_q[63:32]},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.minstret = '{
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rdata: csr.instret_q[CVA6Cfg.XLEN-1:0],
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@ -415,7 +439,12 @@ module cva6_rvfi
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wmask: '1
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};
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rvfi_csr_o.minstreth = CVA6Cfg.XLEN == 32 ?
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'{rdata: csr.instret_q[63:32], wdata: csr.instret_q[63:32], rmask: '1, wmask: '1}
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'{
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.instret_q[63:32]},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.instret_q[63:32]},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.cycle = '{
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rdata: csr.cycle_q[CVA6Cfg.XLEN-1:0],
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@ -424,7 +453,12 @@ module cva6_rvfi
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wmask: '1
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};
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rvfi_csr_o.cycleh = CVA6Cfg.XLEN == 32 ?
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'{rdata: csr.cycle_q[63:32], wdata: csr.cycle_q[63:32], rmask: '1, wmask: '1}
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'{
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.cycle_q[63:32]},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.cycle_q[63:32]},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.instret = '{
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rdata: csr.instret_q[CVA6Cfg.XLEN-1:0],
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@ -433,7 +467,12 @@ module cva6_rvfi
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wmask: '1
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};
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rvfi_csr_o.instreth = CVA6Cfg.XLEN == 32 ?
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'{rdata: csr.instret_q[63:32], wdata: csr.instret_q[63:32], rmask: '1, wmask: '1}
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'{
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.instret_q[63:32]},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.instret_q[63:32]},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.dcache = '{rdata: csr.dcache_q, wdata: csr.dcache_q, rmask: '1, wmask: '1};
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rvfi_csr_o.icache = '{rdata: csr.icache_q, wdata: csr.icache_q, rmask: '1, wmask: '1};
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@ -447,7 +486,12 @@ module cva6_rvfi
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wmask: '1
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};
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rvfi_csr_o.pmpcfg1 = CVA6Cfg.XLEN == 32 ?
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'{rdata: csr.pmpcfg_q[7:4], wdata: csr.pmpcfg_q[7:4], rmask: '1, wmask: '1}
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'{
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.pmpcfg_q[7:4]},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.pmpcfg_q[7:4]},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.pmpcfg2 = '{
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rdata: csr.pmpcfg_q[8+:CVA6Cfg.XLEN/8],
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@ -456,7 +500,12 @@ module cva6_rvfi
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wmask: '1
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};
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rvfi_csr_o.pmpcfg3 = CVA6Cfg.XLEN == 32 ?
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'{rdata: csr.pmpcfg_q[15:12], wdata: csr.pmpcfg_q[15:12], rmask: '1, wmask: '1}
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'{
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.pmpcfg_q[15:12]},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.pmpcfg_q[15:12]},
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rmask: '1,
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wmask: '1
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}
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: '0;
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for (int i = 0; i < 16; i++) begin
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@ -464,9 +513,9 @@ module cva6_rvfi
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rdata:
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csr.pmpcfg_q[i].addr_mode[1]
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== 1'b1 ?
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{'0, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]}
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{{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]}
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: {
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'0
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{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}
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,
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csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1]
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,
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@ -475,9 +524,9 @@ module cva6_rvfi
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wdata:
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csr.pmpcfg_q[i].addr_mode[1]
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== 1'b1 ?
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{'0, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]}
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{{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]}
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: {
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'0
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{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}
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,
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csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1]
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,
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@ -106,12 +106,12 @@
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logic [Cfg.XLEN-1:0] rs1_forwarding; \
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logic [Cfg.XLEN-1:0] rs2_forwarding; \
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logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][Cfg.VLEN-1:0] commit_instr_pc; \
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ariane_pkg::fu_op [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][Cfg.TRANS_ID_BITS-1:0] commit_instr_op; \
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ariane_pkg::fu_op [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0] commit_instr_op; \
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logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] commit_instr_rs1; \
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logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] commit_instr_rs2; \
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logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] commit_instr_rd; \
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logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][Cfg.XLEN-1:0] commit_instr_result; \
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logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][Cfg.VLEN-1:0] commit_instr_valid; \
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logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0] commit_instr_valid; \
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logic [Cfg.XLEN-1:0] ex_commit_cause; \
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logic ex_commit_valid; \
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riscv::priv_lvl_t priv_lvl; \
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