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Instr tracer write to file, fix in kill req signal

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This commit is contained in:
Florian Zaruba 2017-06-17 23:23:52 +02:00
parent 8984fafd71
commit 9f603a3f17
4 changed files with 19 additions and 15 deletions
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10
src/load_unit.sv
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@ -186,10 +186,10 @@ module load_unit (
// translation
translation_req_o = 1'b1;
// we are not ready here
ready_o = 1'b0;
ready_o = 1'b0;
// send an abort signal
tag_valid_o = 1'b1;
kill_req_o = 1'b1;
tag_valid_o = 1'b1;
kill_req_o = 1'b1;
// wait for the translation to become valid and redo the request
if (translation_valid_i) begin
// we have a valid translation so tell the cache it should wait for it on the next cycle
@ -317,8 +317,8 @@ module load_unit (
// output the queue data directly, the valid signal is set corresponding to the process above
trans_id_o = out_data.trans_id;
// we got an rvalid and are currently not flushing
if (data_rvalid_i && CS != WAIT_FLUSH) begin
// we got an rvalid and are currently not flushing and not aborting the request
if (data_rvalid_i && CS != WAIT_FLUSH && !kill_req_o) begin
pop = 1'b1;
valid_o = 1'b1;
end

4
src/util/instruction_trace_item.svh
View file

@ -182,7 +182,7 @@ class instruction_trace_item;
endcase
s = $sformatf("%t %15d %h %h %-36s", simtime,
s = $sformatf("%10t %10d %h %h %-36s", simtime,
cycle,
sbe.pc,
instr,
@ -198,7 +198,7 @@ class instruction_trace_item;
if (read_regs[i] != 0)
s = $sformatf("%s %-4s:%16x", s, regAddrToStr(read_regs[i]), reg_file[read_regs[i]]);
end
// if we got a physical address also display address translation
foreach (paddr_queue[i]) begin
s = $sformatf("%s VA: %x PA: %x", s, this.vaddr, paddr_queue[i]);
end

7
src/util/instruction_tracer.svh
View file

@ -33,6 +33,7 @@ class instruction_tracer;
logic [63:0] reg_file [32];
// 64 bit clock tick count
longint unsigned clk_ticks;
int f;
// address mapping
// contains mappings of the form vaddr <-> paddr
struct {
@ -42,6 +43,7 @@ class instruction_tracer;
function new(virtual instruction_tracer_if tracer_if);
this.tracer_if = tracer_if;
f = $fopen("output.txt","w");
endfunction : new
task trace();
@ -161,8 +163,9 @@ class instruction_tracer;
function void printInstr(scoreboard_entry sbe, logic [63:0] instr, logic [63:0] result, logic [63:0] vaddr, logic [63:0] paddr);
instruction_trace_item iti = new ($time, clk_ticks, sbe, instr, this.reg_file, result, vaddr, paddr);
// print instruction to console
$display(iti.printInstr());
string print_instr = iti.printInstr();
$display(print_instr);
$fwrite(this.f, {print_instr, "\n"});
endfunction;
endclass : instruction_tracer

13
tb/common/core_mem.sv
View file

@ -48,11 +48,12 @@ module core_mem (
logic [2:0] instr_address_offset_q;
logic [63:0] instr_data;
// D$ Mock
logic req, we;
logic [7:0] be;
logic [11:0] index;
logic [63:0] wdata;
logic [55:0] data_address;
logic req, we;
logic [7:0] be;
logic [11:0] index;
logic [63:0] wdata;
logic [55:0] data_address;
assign data_address = {data_if_address_tag_i, index[11:3]};
// we always grant the request
@ -76,7 +77,7 @@ module core_mem (
.en_b_i ( req ),
.addr_b_i ( data_address[ADDRESS_WIDTH-1:0] ),
.wdata_b_i ( wdata ),
.rdata_b_o ( data_if_data_rdata_o),
.rdata_b_o ( data_if_data_rdata_o ),
.we_b_i ( we ),
.be_b_i ( be )
);