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Enable assertions in Verilator after migrating to Verilator v5. (#1185)
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6 changed files with 15 additions and 27 deletions
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@ -293,14 +293,12 @@ module axi_shim #(
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// ----------------
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//pragma translate_off
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`ifndef VERILATOR
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initial begin
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assert (AxiNumWords >= 1) else
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$fatal(1, "[axi adapter] AxiNumWords must be >= 1");
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assert (AxiIdWidth >= 2) else
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$fatal(1, "[axi adapter] AXI id width must be at least 2 bit wide");
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end
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`endif
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initial begin
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assert (AxiNumWords >= 1) else
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$fatal(1, "[axi adapter] AxiNumWords must be >= 1");
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assert (AxiIdWidth >= 2) else
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$fatal(1, "[axi adapter] AXI id width must be at least 2 bit wide");
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end
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//pragma translate_on
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endmodule // axi_adapter2
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@ -1275,11 +1275,9 @@ module csr_regfile import ariane_pkg::*; #(
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// Assertions
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//-------------
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//pragma translate_off
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`ifndef VERILATOR
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// check that eret and ex are never valid together
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assert property (
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@(posedge clk_i) disable iff (!rst_ni !== '0) !(eret_o && ex_i.valid))
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// check that eret and ex are never valid together
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assert property (
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@(posedge clk_i) disable iff (!rst_ni !== '0) !(eret_o && ex_i.valid))
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else begin $error("eret and exception should never be valid at the same time"); $stop(); end
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`endif
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//pragma translate_on
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endmodule
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@ -526,17 +526,15 @@ module issue_read_operands import ariane_pkg::*; #(
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end
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//pragma translate_off
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`ifndef VERILATOR
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initial begin
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assert (NR_RGPR_PORTS == 2 || (NR_RGPR_PORTS == 3 && CVXIF_PRESENT))
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else $fatal(1, "If CVXIF is enable, ariane regfile can have either 2 or 3 read ports. Else it has 2 read ports.");
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end
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assert property (
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assert property (
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@(posedge clk_i) (branch_valid_q) |-> (!$isunknown(operand_a_q) && !$isunknown(operand_b_q)))
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else $warning ("Got unknown value in one of the operands");
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`endif
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//pragma translate_on
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endmodule
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@ -381,12 +381,11 @@ module load_unit import ariane_pkg::*; #(
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end
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// end result mux fast
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///////////////////////////////////////////////////////
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// assertions
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///////////////////////////////////////////////////////
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///////////////////////////////////////////////////////
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// assertions
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///////////////////////////////////////////////////////
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//pragma translate_off
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`ifndef VERILATOR
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//pragma translate_off
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// check invalid offsets
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addr_offset0: assert property (@(posedge clk_i) disable iff (~rst_ni)
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valid_o |-> (load_data_q.operation inside {ariane_pkg::LW, ariane_pkg::LWU}) |-> load_data_q.address_offset < 5) else $fatal (1,"invalid address offset used with {LW, LWU}");
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@ -394,7 +393,6 @@ module load_unit import ariane_pkg::*; #(
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valid_o |-> (load_data_q.operation inside {ariane_pkg::LH, ariane_pkg::LHU}) |-> load_data_q.address_offset < 7) else $fatal (1,"invalid address offset used with {LH, LHU}");
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addr_offset2: assert property (@(posedge clk_i) disable iff (~rst_ni)
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valid_o |-> (load_data_q.operation inside {ariane_pkg::LB, ariane_pkg::LBU}) |-> load_data_q.address_offset < 8) else $fatal (1,"invalid address offset used with {LB, LBU}");
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`endif
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//pragma translate_on
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//pragma translate_on
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endmodule
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@ -404,7 +404,6 @@ module scoreboard #(
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end
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//pragma translate_off
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`ifndef VERILATOR
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initial begin
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assert (NR_ENTRIES == 2**BITS_ENTRIES) else $fatal(1, "Scoreboard size needs to be a power of two.");
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end
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@ -436,6 +435,5 @@ module scoreboard #(
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else $fatal (1,"Two or more functional units are retiring instructions with the same transaction id!");
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end
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end
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`endif
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//pragma translate_on
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endmodule
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@ -258,7 +258,6 @@ module store_buffer import ariane_pkg::*; (
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///////////////////////////////////////////////////////
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//pragma translate_off
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`ifndef VERILATOR
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// assert that commit is never set when we are flushing this would be counter intuitive
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// as flush and commit is decided in the same stage
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commit_and_flush: assert property (
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@ -276,7 +275,6 @@ module store_buffer import ariane_pkg::*; (
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commit_buffer_overflow: assert property (
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@(posedge clk_i) rst_ni && (commit_status_cnt_q == DEPTH_COMMIT) |-> !commit_i)
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else $error("[Commit Queue] You are trying to commit a store although the buffer is full");
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`endif
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//pragma translate_on
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endmodule
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