mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-06-27 17:00:57 -04:00
Add Agilex HPS in Altera FPGA design (#2956)
Add Altera HPS to design in order to be able to access the peripherals connected to it.
This commit is contained in:
AngelaGonzalezMarino
GitHub
parent
7555cb7d60
commit
a2c2f60e5b
9 changed files with 3039 additions and 17 deletions
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@ -72,9 +72,13 @@ create_project:
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@touch "$(PROJECT).qsf"
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$(QSYS_PATH)qsys-script --script=ip/interconnect.tcl
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$(QSYS_PATH)qsys-generate interconnect.qsys --quartus_project=ip/interconnect --synthesis
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$(QSYS_PATH)qsys-script --script=ip/hps_cva6_altera.tcl
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$(QSYS_PATH)qsys-generate system.qsys --quartus_project=ip/hps_cva6_altera --synthesis
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rm -f interconnect/*.v
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rm -f interconnect/*.vhd
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rm -f interconnect/synth/*.v
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rm -f system/*.v
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rm -f system/*.vhd
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write_settings:
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@echo "Reading from settings.csv and writing to $(PROJECT).qsf with modifications"
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@ -108,6 +112,7 @@ write_search_paths:
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write_source_files:
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@find ./interconnect -type f -name "*.v" -o -name "*.sv" -o -name "*.svh" >> $(SOURCES_FILE)
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@find ./system -type f -name "*.v" -o -name "*.sv" -o -name "*.svh" >> $(SOURCES_FILE)
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@echo $(var)
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@echo >> $(SOURCES_FILE)
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@echo "Reading from $(SOURCES_FILE) and writing to $(PROJECT).qsf with modifications"
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@ -191,6 +196,7 @@ clean:
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rm -rf interconnect
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rm -rf io_pll
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rm -rf iobuf
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rm -rf system
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$(QUARTUS_PATH)quartus_ipgenerate --clean $(PROJECT)
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@ -5,3 +5,71 @@ IO_STANDARD "1.2 V" -to led[3] -entity cva6_altera
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IO_STANDARD "1.2 V" -to led[2] -entity cva6_altera
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IO_STANDARD "1.2 V" -to led[1] -entity cva6_altera
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IO_STANDARD "1.2 V" -to led[0] -entity cva6_altera
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IO_STANDARD "1.8-V" -to hps_emac0_MDC -entity ghrd
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IO_STANDARD "1.8-V" -to hps_emac0_MDIO -entity ghrd
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IO_STANDARD "1.8-V" -to hps_emac0_RXD0 -entity ghrd
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IO_STANDARD "1.8-V" -to hps_emac0_RXD1 -entity ghrd
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IO_STANDARD "1.8-V" -to hps_emac0_RXD2 -entity ghrd
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IO_STANDARD "1.8-V" -to hps_emac0_RXD3 -entity ghrd
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IO_STANDARD "1.8-V" -to hps_emac0_RX_CLK -entity ghrd
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IO_STANDARD "1.8-V" -to hps_emac0_RX_CTL -entity ghrd
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IO_STANDARD "1.8-V" -to hps_emac0_TXD0 -entity ghrd
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IO_STANDARD "1.8-V" -to hps_emac0_TXD1 -entity ghrd
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IO_STANDARD "1.8-V" -to hps_emac0_TXD2 -entity ghrd
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IO_STANDARD "1.8-V" -to hps_emac0_TXD3 -entity ghrd
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IO_STANDARD "1.8-V" -to hps_emac0_TX_CLK -entity ghrd
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IO_STANDARD "1.8-V" -to hps_emac0_TX_CTL -entity ghrd
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IO_STANDARD "1.8-V" -to hps_i2c1_SCL -entity ghrd
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IO_STANDARD "1.8-V" -to hps_i2c1_SDA -entity ghrd
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IO_STANDARD "1.8-V" -to hps_jtag_tck -entity ghrd
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IO_STANDARD "1.8-V" -to hps_jtag_tdo -entity ghrd
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IO_STANDARD "1.8-V" -to hps_ref_clk -entity ghrd
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IO_STANDARD "1.8 V" -to hps_sdmmc_CMD -entity ghrd
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IO_STANDARD "1.8 V" -to hps_sdmmc_CCLK -entity ghrd
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IO_STANDARD "1.8 V" -to hps_sdmmc_D0 -entity ghrd
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IO_STANDARD "1.8 V" -to hps_sdmmc_D1 -entity ghrd
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IO_STANDARD "1.8 V" -to hps_sdmmc_D2 -entity ghrd
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IO_STANDARD "1.8 V" -to hps_sdmmc_D3 -entity ghrd
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IO_STANDARD "1.8 V" -to hps_uart0_TX -entity ghrd
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IO_STANDARD "1.8 V" -to hps_uart0_RX -entity ghrd
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IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to fpga_clk_100 -entity ghrd
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CURRENT_STRENGTH_NEW 4MA -to hps_emac0_MDC -entity ghrd
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CURRENT_STRENGTH_NEW 4MA -to hps_emac0_MDIO -entity ghrd
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AUTO_OPEN_DRAIN_PINS ON -to hps_emac0_MDIO -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_emac0_MDIO -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_emac0_RXD0 -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_emac0_RXD1 -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_emac0_RXD2 -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_emac0_RXD3 -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_emac0_RX_CLK -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_emac0_RX_CTL -entity ghrd
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CURRENT_STRENGTH_NEW 8MA -to hps_emac0_TXD0 -entity ghrd
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CURRENT_STRENGTH_NEW 8MA -to hps_emac0_TXD1 -entity ghrd
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CURRENT_STRENGTH_NEW 8MA -to hps_emac0_TXD2 -entity ghrd
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CURRENT_STRENGTH_NEW 8MA -to hps_emac0_TXD3 -entity ghrd
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CURRENT_STRENGTH_NEW 8MA -to hps_emac0_TX_CLK -entity ghrd
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CURRENT_STRENGTH_NEW 8MA -to hps_emac0_TX_CTL -entity ghrd
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CURRENT_STRENGTH_NEW 4MA -to hps_i2c1_SCL -entity ghrd
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AUTO_OPEN_DRAIN_PINS ON -to hps_i2c1_SCL -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_i2c1_SCL -entity ghrd
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CURRENT_STRENGTH_NEW 4MA -to hps_i2c1_SDA -entity ghrd
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AUTO_OPEN_DRAIN_PINS ON -to hps_i2c1_SDA -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_i2c1_SDA -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_jtag_tck -entity ghrd
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IO_STANDARD "1.8-V" -to hps_jtag_tdi -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_jtag_tdi -entity ghrd
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CURRENT_STRENGTH_NEW 4MA -to hps_jtag_tdo -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_jtag_tms -entity ghrd
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CURRENT_STRENGTH_NEW 8MA -to hps_sdmmc_CMD -entity ghrd
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CURRENT_STRENGTH_NEW 8MA -to hps_sdmmc_CCLK -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_sdmmc_CMD -entity ghrd
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CURRENT_STRENGTH_NEW 8MA -to hps_sdmmc_D0 -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_sdmmc_D0 -entity ghrd
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CURRENT_STRENGTH_NEW 8MA -to hps_sdmmc_D1 -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_sdmmc_D1 -entity ghrd
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CURRENT_STRENGTH_NEW 8MA -to hps_sdmmc_D2 -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_sdmmc_D2 -entity ghrd
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CURRENT_STRENGTH_NEW 8MA -to hps_sdmmc_D3 -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_sdmmc_D3 -entity ghrd
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CURRENT_STRENGTH_NEW 4MA -to hps_uart0_TX -entity ghrd
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WEAK_PULL_UP_RESISTOR ON -to hps_uart0_RX -entity ghrd
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Can't render this file because it contains an unexpected character in line 1 and column 13.
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@ -24,7 +24,7 @@ proc do_create_emif_cal {} {
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set_instance_parameter_value emif_cal_0 {DIAG_SIM_VERBOSE} {0}
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set_instance_parameter_value emif_cal_0 {DIAG_SYNTH_FOR_SIM} {0}
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set_instance_parameter_value emif_cal_0 {ENABLE_DDRT} {0}
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set_instance_parameter_value emif_cal_0 {NUM_CALBUS_INTERFACE} {1}
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set_instance_parameter_value emif_cal_0 {NUM_CALBUS_INTERFACE} {2}
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set_instance_parameter_value emif_cal_0 {PHY_DDRT_EXPORT_CLK_STP_IF} {0}
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set_instance_parameter_value emif_cal_0 {SHORT_QSYS_INTERFACE_NAMES} {1}
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set_instance_property emif_cal_0 AUTO_EXPORT true
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2534
corev_apu/altera/ip/hps_cva6_altera.tcl
Normal file
2534
corev_apu/altera/ip/hps_cva6_altera.tcl
Normal file
File diff suppressed because it is too large
Load diff
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@ -7,3 +7,7 @@
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./emif_cal.ip
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./vJTAG.ip
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./cva6_intel_jtag_uart_0.ip
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./ip/system/hps.ip
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./ip/system/hps_emif.ip
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./ip/system/init_done.ip
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./ip/system/system_intel_cache_coherency_translator.ip
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@ -137,3 +137,134 @@ PIN_N34 -to ddr4_act_n
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PIN_P33 -to ddr4_reset_n
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PIN_AA6 -to tx
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PIN_F1 -to rx
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PIN_L10 -to emif_hps_pll_ref_clk_p
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PIN_M9 -to emif_hps_oct_oct_rzqin
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PIN_T17 -to emif_hps_mem_mem_a[0]
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PIN_V17 -to emif_hps_mem_mem_a[1]
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PIN_U16 -to emif_hps_mem_mem_a[2]
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PIN_W16 -to emif_hps_mem_mem_a[3]
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PIN_T15 -to emif_hps_mem_mem_a[4]
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PIN_V15 -to emif_hps_mem_mem_a[5]
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PIN_U14 -to emif_hps_mem_mem_a[6]
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PIN_W14 -to emif_hps_mem_mem_a[7]
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PIN_T13 -to emif_hps_mem_mem_a[8]
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PIN_V13 -to emif_hps_mem_mem_a[9]
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PIN_U12 -to emif_hps_mem_mem_a[10]
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PIN_W12 -to emif_hps_mem_mem_a[11]
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PIN_P9 -to emif_hps_mem_mem_a[12]
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PIN_L8 -to emif_hps_mem_mem_a[13]
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PIN_N8 -to emif_hps_mem_mem_a[14]
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PIN_M7 -to emif_hps_mem_mem_a[15]
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PIN_P7 -to emif_hps_mem_mem_a[16]
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PIN_N6 -to emif_hps_mem_mem_ba[0]
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PIN_M5 -to emif_hps_mem_mem_ba[1]
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PIN_P5 -to emif_hps_mem_mem_bg[0]
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PIN_N16 -to emif_hps_mem_mem_act_n
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PIN_L6 -to emif_hps_mem_mem_alert_n
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PIN_M13 -to emif_hps_mem_mem_ck[0]
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PIN_P13 -to emif_hps_mem_mem_ck_n[0]
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PIN_L14 -to emif_hps_mem_mem_cke[0]
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PIN_L16 -to emif_hps_mem_mem_cs_n[0]
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PIN_M15 -to emif_hps_mem_mem_odt[0]
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PIN_N12 -to emif_hps_mem_mem_par
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PIN_P17 -to emif_hps_mem_mem_reset_n
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PIN_A8 -to emif_hps_mem_mem_dqs[0]
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PIN_G8 -to emif_hps_mem_mem_dqs[1]
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PIN_F15 -to emif_hps_mem_mem_dqs[2]
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PIN_B15 -to emif_hps_mem_mem_dqs[3]
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PIN_U22 -to emif_hps_mem_mem_dqs[4]
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PIN_L22 -to emif_hps_mem_mem_dqs[5]
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PIN_M29 -to emif_hps_mem_mem_dqs[6]
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PIN_T29 -to emif_hps_mem_mem_dqs[7]
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PIN_U8 -to emif_hps_mem_mem_dqs[8]
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PIN_C8 -to emif_hps_mem_mem_dqs_n[0]
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PIN_J8 -to emif_hps_mem_mem_dqs_n[1]
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PIN_H15 -to emif_hps_mem_mem_dqs_n[2]
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PIN_D15 -to emif_hps_mem_mem_dqs_n[3]
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PIN_W22 -to emif_hps_mem_mem_dqs_n[4]
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PIN_N22 -to emif_hps_mem_mem_dqs_n[5]
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PIN_P29 -to emif_hps_mem_mem_dqs_n[6]
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PIN_V29 -to emif_hps_mem_mem_dqs_n[7]
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PIN_W8 -to emif_hps_mem_mem_dqs_n[8]
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PIN_B7 -to emif_hps_mem_mem_dbi_n[0]
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PIN_F7 -to emif_hps_mem_mem_dbi_n[1]
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PIN_G14 -to emif_hps_mem_mem_dbi_n[2]
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PIN_A14 -to emif_hps_mem_mem_dbi_n[3]
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PIN_T21 -to emif_hps_mem_mem_dbi_n[4]
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PIN_M21 -to emif_hps_mem_mem_dbi_n[5]
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PIN_L28 -to emif_hps_mem_mem_dbi_n[6]
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PIN_U28 -to emif_hps_mem_mem_dbi_n[7]
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PIN_T7 -to emif_hps_mem_mem_dbi_n[8]
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PIN_A10 -to emif_hps_mem_mem_dq[0]
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PIN_C10 -to emif_hps_mem_mem_dq[1]
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PIN_B9 -to emif_hps_mem_mem_dq[2]
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PIN_D9 -to emif_hps_mem_mem_dq[3]
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PIN_A6 -to emif_hps_mem_mem_dq[4]
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PIN_B5 -to emif_hps_mem_mem_dq[5]
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PIN_C6 -to emif_hps_mem_mem_dq[6]
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PIN_D5 -to emif_hps_mem_mem_dq[7]
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PIN_G10 -to emif_hps_mem_mem_dq[8]
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PIN_J10 -to emif_hps_mem_mem_dq[9]
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PIN_F9 -to emif_hps_mem_mem_dq[10]
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PIN_H9 -to emif_hps_mem_mem_dq[11]
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PIN_G6 -to emif_hps_mem_mem_dq[12]
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PIN_J6 -to emif_hps_mem_mem_dq[13]
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PIN_F5 -to emif_hps_mem_mem_dq[14]
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PIN_H5 -to emif_hps_mem_mem_dq[15]
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PIN_F17 -to emif_hps_mem_mem_dq[16]
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PIN_H17 -to emif_hps_mem_mem_dq[17]
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PIN_G16 -to emif_hps_mem_mem_dq[18]
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PIN_J16 -to emif_hps_mem_mem_dq[19]
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PIN_F13 -to emif_hps_mem_mem_dq[20]
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PIN_J12 -to emif_hps_mem_mem_dq[21]
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PIN_H13 -to emif_hps_mem_mem_dq[22]
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PIN_G12 -to emif_hps_mem_mem_dq[23]
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PIN_B17 -to emif_hps_mem_mem_dq[24]
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PIN_D17 -to emif_hps_mem_mem_dq[25]
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PIN_A16 -to emif_hps_mem_mem_dq[26]
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PIN_C16 -to emif_hps_mem_mem_dq[27]
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PIN_B13 -to emif_hps_mem_mem_dq[28]
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PIN_D13 -to emif_hps_mem_mem_dq[29]
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PIN_A12 -to emif_hps_mem_mem_dq[30]
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PIN_C12 -to emif_hps_mem_mem_dq[31]
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PIN_U24 -to emif_hps_mem_mem_dq[32]
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PIN_W24 -to emif_hps_mem_mem_dq[33]
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PIN_T23 -to emif_hps_mem_mem_dq[34]
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PIN_V23 -to emif_hps_mem_mem_dq[35]
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PIN_U20 -to emif_hps_mem_mem_dq[36]
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PIN_W20 -to emif_hps_mem_mem_dq[37]
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PIN_T19 -to emif_hps_mem_mem_dq[38]
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PIN_V19 -to emif_hps_mem_mem_dq[39]
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PIN_L24 -to emif_hps_mem_mem_dq[40]
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PIN_N24 -to emif_hps_mem_mem_dq[41]
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PIN_M23 -to emif_hps_mem_mem_dq[42]
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PIN_P23 -to emif_hps_mem_mem_dq[43]
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PIN_L20 -to emif_hps_mem_mem_dq[44]
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PIN_P19 -to emif_hps_mem_mem_dq[45]
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PIN_N20 -to emif_hps_mem_mem_dq[46]
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PIN_M19 -to emif_hps_mem_mem_dq[47]
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PIN_M31 -to emif_hps_mem_mem_dq[48]
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PIN_P31 -to emif_hps_mem_mem_dq[49]
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PIN_L30 -to emif_hps_mem_mem_dq[50]
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PIN_N30 -to emif_hps_mem_mem_dq[51]
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PIN_M27 -to emif_hps_mem_mem_dq[52]
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PIN_P27 -to emif_hps_mem_mem_dq[53]
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PIN_L26 -to emif_hps_mem_mem_dq[54]
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PIN_N26 -to emif_hps_mem_mem_dq[55]
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PIN_T31 -to emif_hps_mem_mem_dq[56]
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PIN_V31 -to emif_hps_mem_mem_dq[57]
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PIN_U30 -to emif_hps_mem_mem_dq[58]
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PIN_W30 -to emif_hps_mem_mem_dq[59]
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PIN_T27 -to emif_hps_mem_mem_dq[60]
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PIN_W26 -to emif_hps_mem_mem_dq[61]
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PIN_V27 -to emif_hps_mem_mem_dq[62]
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PIN_U26 -to emif_hps_mem_mem_dq[63]
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PIN_U10 -to emif_hps_mem_mem_dq[64]
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PIN_W10 -to emif_hps_mem_mem_dq[65]
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PIN_T9 -to emif_hps_mem_mem_dq[66]
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PIN_V9 -to emif_hps_mem_mem_dq[67]
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PIN_U6 -to emif_hps_mem_mem_dq[68]
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PIN_W6 -to emif_hps_mem_mem_dq[69]
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PIN_T5 -to emif_hps_mem_mem_dq[70]
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PIN_V5 -to emif_hps_mem_mem_dq[71]
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PIN_M17 -to emif_hps_mem_mem_bg[1] -comment IOBANK_3D
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@ -43,3 +43,24 @@ FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS
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GLOBAL_PLACEMENT_EFFORT "MAXIMUM EFFORT"
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QII_AUTO_PACKED_REGISTERS SPARSE
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OPTIMIZATION_TECHNIQUE SPEED
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AUTO_RESTART_CONFIGURATION OFF
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USE_PWRMGT_SCL SDM_IO14
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USE_PWRMGT_SDA SDM_IO11
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USE_CONF_DONE SDM_IO16
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USE_INIT_DONE SDM_IO0
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USE_CVP_CONFDONE SDM_IO10
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POWER_APPLY_THERMAL_MARGIN ADDITIONAL
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PWRMGT_BUS_SPEED_MODE "100 KHZ"
|
||||
PWRMGT_SLAVE_DEVICE_TYPE ED8401
|
||||
PWRMGT_SLAVE_DEVICE0_ADDRESS 47
|
||||
PWRMGT_SLAVE_DEVICE1_ADDRESS 00
|
||||
PWRMGT_SLAVE_DEVICE2_ADDRESS 00
|
||||
PWRMGT_SLAVE_DEVICE3_ADDRESS 00
|
||||
PWRMGT_SLAVE_DEVICE4_ADDRESS 00
|
||||
PWRMGT_SLAVE_DEVICE5_ADDRESS 00
|
||||
PWRMGT_SLAVE_DEVICE6_ADDRESS 00
|
||||
PWRMGT_SLAVE_DEVICE7_ADDRESS 00
|
||||
PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS
|
||||
PWRMGT_PAGE_COMMAND_ENABLE OFF
|
||||
PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
|
||||
PWRMGT_LINEAR_FORMAT_N "-13"
|
||||
|
Can't render this file because it contains an unexpected character in line 3 and column 28.
|
|
|
@ -44,7 +44,57 @@ module cva6_altera (
|
|||
input logic [ 0:0] ddr4_alert_n,
|
||||
input logic oct_rzqin ,
|
||||
|
||||
output logic [ 3:0] led
|
||||
output logic [ 3:0] led ,
|
||||
//HPS
|
||||
// HPS EMIF
|
||||
output wire [0:0] emif_hps_mem_mem_ck,
|
||||
output wire [0:0] emif_hps_mem_mem_ck_n,
|
||||
output wire [16:0] emif_hps_mem_mem_a,
|
||||
output wire [0:0] emif_hps_mem_mem_act_n,
|
||||
output wire [1:0] emif_hps_mem_mem_ba,
|
||||
output wire [1:0] emif_hps_mem_mem_bg,
|
||||
output wire [0:0] emif_hps_mem_mem_cke,
|
||||
output wire [0:0] emif_hps_mem_mem_cs_n,
|
||||
output wire [0:0] emif_hps_mem_mem_odt,
|
||||
output wire [0:0] emif_hps_mem_mem_reset_n,
|
||||
output wire [0:0] emif_hps_mem_mem_par,
|
||||
input wire [0:0] emif_hps_mem_mem_alert_n,
|
||||
input wire emif_hps_oct_oct_rzqin,
|
||||
input wire emif_hps_pll_ref_clk_p,
|
||||
inout wire [8-1:0] emif_hps_mem_mem_dbi_n,
|
||||
inout wire [64-1:0] emif_hps_mem_mem_dq,
|
||||
inout wire [8-1:0] emif_hps_mem_mem_dqs,
|
||||
inout wire [8-1:0] emif_hps_mem_mem_dqs_n,
|
||||
input wire hps_jtag_tck,
|
||||
input wire hps_jtag_tms,
|
||||
output wire hps_jtag_tdo,
|
||||
input wire hps_jtag_tdi,
|
||||
output wire hps_sdmmc_CCLK,
|
||||
inout wire hps_sdmmc_CMD,
|
||||
inout wire hps_sdmmc_D0,
|
||||
inout wire hps_sdmmc_D1,
|
||||
inout wire hps_sdmmc_D2,
|
||||
inout wire hps_sdmmc_D3,
|
||||
output wire hps_emac0_TX_CLK,
|
||||
input wire hps_emac0_RX_CLK,
|
||||
output wire hps_emac0_TX_CTL,
|
||||
input wire hps_emac0_RX_CTL,
|
||||
output wire hps_emac0_TXD0,
|
||||
output wire hps_emac0_TXD1,
|
||||
input wire hps_emac0_RXD0,
|
||||
input wire hps_emac0_RXD1,
|
||||
output wire hps_emac0_TXD2,
|
||||
output wire hps_emac0_TXD3,
|
||||
input wire hps_emac0_RXD2,
|
||||
input wire hps_emac0_RXD3,
|
||||
inout wire hps_emac0_MDIO,
|
||||
output wire hps_emac0_MDC,
|
||||
input wire hps_uart0_RX,
|
||||
output wire hps_uart0_TX,
|
||||
inout wire hps_i2c1_SDA,
|
||||
inout wire hps_i2c1_SCL,
|
||||
inout wire hps_gpio1_io0,
|
||||
input wire hps_ref_clk
|
||||
);
|
||||
|
||||
// CVA6 Intel configuration
|
||||
|
|
@ -99,7 +149,7 @@ AXI_BUS #(
|
|||
.AXI_DATA_WIDTH ( AxiDataWidth ),
|
||||
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
|
||||
.AXI_USER_WIDTH ( AxiUserWidth )
|
||||
) master[ariane_soc::NB_PERIPHERALS-1:0]();
|
||||
) master[ariane_soc::NB_PERIPHERALS:0]();
|
||||
|
||||
AXI_BUS #(
|
||||
.AXI_ADDR_WIDTH ( CVA6Cfg.XLEN ),
|
||||
|
|
@ -170,7 +220,7 @@ assign rst = ~ddr_sync_reset;
|
|||
// AXI Xbar
|
||||
// ---------------
|
||||
|
||||
axi_pkg::xbar_rule_64_t [ariane_soc::NB_PERIPHERALS-1:0] addr_map;
|
||||
axi_pkg::xbar_rule_64_t [ariane_soc::NB_PERIPHERALS:0] addr_map;
|
||||
|
||||
assign addr_map = '{
|
||||
'{ idx: ariane_soc::Debug, start_addr: ariane_soc::DebugBase, end_addr: ariane_soc::DebugBase + ariane_soc::DebugLength },
|
||||
|
|
@ -182,12 +232,13 @@ assign addr_map = '{
|
|||
'{ idx: ariane_soc::SPI, start_addr: ariane_soc::SPIBase, end_addr: ariane_soc::SPIBase + ariane_soc::SPILength },
|
||||
'{ idx: ariane_soc::Ethernet, start_addr: ariane_soc::EthernetBase, end_addr: ariane_soc::EthernetBase + ariane_soc::EthernetLength },
|
||||
'{ idx: ariane_soc::GPIO, start_addr: ariane_soc::GPIOBase, end_addr: ariane_soc::GPIOBase + ariane_soc::GPIOLength },
|
||||
'{ idx: ariane_soc::DRAM, start_addr: ariane_soc::DRAMBase, end_addr: ariane_soc::DRAMBase + ariane_soc::DRAMLength }
|
||||
'{ idx: ariane_soc::DRAM, start_addr: ariane_soc::DRAMBase, end_addr: ariane_soc::DRAMBase + ariane_soc::DRAMLength },
|
||||
'{ idx: ariane_soc::HPS, start_addr: ariane_soc::HPSBase, end_addr: ariane_soc::HPSBase + ariane_soc::HPSLength }
|
||||
};
|
||||
|
||||
localparam axi_pkg::xbar_cfg_t AXI_XBAR_CFG = '{
|
||||
NoSlvPorts: ariane_soc::NrSlaves,
|
||||
NoMstPorts: ariane_soc::NB_PERIPHERALS,
|
||||
NoMstPorts: ariane_soc::NB_PERIPHERALS+1,
|
||||
MaxMstTrans: 1, // Probably requires update
|
||||
MaxSlvTrans: 1, // Probably requires update
|
||||
FallThrough: 1'b0,
|
||||
|
|
@ -197,7 +248,7 @@ localparam axi_pkg::xbar_cfg_t AXI_XBAR_CFG = '{
|
|||
UniqueIds: 1'b0,
|
||||
AxiAddrWidth: AxiAddrWidth,
|
||||
AxiDataWidth: AxiDataWidth,
|
||||
NoAddrRules: ariane_soc::NB_PERIPHERALS
|
||||
NoAddrRules: ariane_soc::NB_PERIPHERALS+1
|
||||
};
|
||||
|
||||
axi_xbar_intf #(
|
||||
|
|
@ -818,11 +869,11 @@ logic [6:0] ddr_sc_amm_burstcount;
|
|||
logic [63:0] ddr_sc_amm_byteenable;
|
||||
logic ddr_sc_amm_readdatavalid;
|
||||
|
||||
logic calbus_read, calbus_write, calbus_clk, ddr_pll_locked, ddr_rst_req, ddr_rst_done;
|
||||
logic [19:0] calbus_addr;
|
||||
logic [31:0] calbus_wdata;
|
||||
logic [31:0] calbus_rdata;
|
||||
logic [4095:0] calbus_seq_param_tbl;
|
||||
logic calbus_read, calbus_write, calbus_clk, calbus_read1, calbus_write1, calbus_clk1, ddr_pll_locked, ddr_rst_req, ddr_rst_done;
|
||||
logic [19:0] calbus_addr,calbus_addr1;
|
||||
logic [31:0] calbus_wdata, calbus_wdata1;
|
||||
logic [31:0] calbus_rdata, calbus_rdata1;
|
||||
logic [4095:0] calbus_seq_param_tbl, calbus_seq_param_tbl1;
|
||||
logic cal_success;
|
||||
logic ddr_amm_wait_request;
|
||||
|
||||
|
|
@ -1040,9 +1091,214 @@ emif_cal ddr_calibration (
|
|||
.calbus_wdata_0 (calbus_wdata), // output, width = 32, .calbus_wdata
|
||||
.calbus_rdata_0 (calbus_rdata), // input, width = 32, .calbus_rdata
|
||||
.calbus_seq_param_tbl_0 (calbus_seq_param_tbl), // input, width = 4096, .calbus_seq_param_tbl
|
||||
.calbus_clk (calbus_clk) // output, width = 1, emif_calbus_clk.clk
|
||||
);
|
||||
|
||||
.calbus_read_1 (calbus_read1), // output, width = 1, emif_calbus_1.calbus_read
|
||||
.calbus_write_1 (calbus_write1), // output, width = 1, .calbus_write
|
||||
.calbus_address_1 (calbus_addr1), // output, width = 20, .calbus_address
|
||||
.calbus_wdata_1 (calbus_wdata1), // output, width = 32, .calbus_wdata
|
||||
.calbus_rdata_1 (calbus_rdata1), // input, width = 32, .calbus_rdata
|
||||
.calbus_seq_param_tbl_1 (calbus_seq_param_tbl1), // input, width = 4096, .calbus_seq_param_tbl
|
||||
.calbus_clk (calbus_clk) // output, width = 1, emif_calbus_clk.clk
|
||||
);
|
||||
|
||||
wire h2f_reset;
|
||||
wire ninit_done;
|
||||
|
||||
assign system_reset_n = ~h2f_reset & ~ninit_done;
|
||||
|
||||
AXI_BUS #(
|
||||
.AXI_ADDR_WIDTH ( CVA6Cfg.XLEN ),
|
||||
.AXI_DATA_WIDTH ( 128 ),
|
||||
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
|
||||
.AXI_USER_WIDTH ( AxiUserWidth )
|
||||
) master_to_hps[0:0]();
|
||||
|
||||
axi_dw_adapter #(
|
||||
.ADDR_WIDTH (CVA6Cfg.XLEN),
|
||||
.S_DATA_WIDTH (AxiAddrWidth),
|
||||
.M_DATA_WIDTH (128),
|
||||
.ID_WIDTH (AxiIdWidthSlaves)
|
||||
)i_axi_dwidth_converter_hps(
|
||||
.clk(clk),
|
||||
.rst(~ndmreset_n),
|
||||
.s_axi_awid(master[ariane_soc::HPS].aw_id),
|
||||
.s_axi_awaddr(master[ariane_soc::HPS].aw_addr[31:0]),
|
||||
.s_axi_awlen(master[ariane_soc::HPS].aw_len),
|
||||
.s_axi_awsize(master[ariane_soc::HPS].aw_size),
|
||||
.s_axi_awburst(master[ariane_soc::HPS].aw_burst),
|
||||
.s_axi_awlock(master[ariane_soc::HPS].aw_lock),
|
||||
.s_axi_awcache(master[ariane_soc::HPS].aw_cache),
|
||||
.s_axi_awprot(master[ariane_soc::HPS].aw_prot),
|
||||
.s_axi_awregion(master[ariane_soc::HPS].aw_region),
|
||||
.s_axi_awqos(master[ariane_soc::HPS].aw_qos),
|
||||
.s_axi_awvalid(master[ariane_soc::HPS].aw_valid),
|
||||
.s_axi_awready(master[ariane_soc::HPS].aw_ready),
|
||||
.s_axi_wdata(master[ariane_soc::HPS].w_data),
|
||||
.s_axi_wstrb(master[ariane_soc::HPS].w_strb),
|
||||
.s_axi_wlast(master[ariane_soc::HPS].w_last),
|
||||
.s_axi_wvalid(master[ariane_soc::HPS].w_valid),
|
||||
.s_axi_wready(master[ariane_soc::HPS].w_ready),
|
||||
.s_axi_bid(master[ariane_soc::HPS].b_id),
|
||||
.s_axi_bresp(master[ariane_soc::HPS].b_resp),
|
||||
.s_axi_bvalid(master[ariane_soc::HPS].b_valid),
|
||||
.s_axi_bready(master[ariane_soc::HPS].b_ready),
|
||||
.s_axi_arid(master[ariane_soc::HPS].ar_id),
|
||||
.s_axi_araddr(master[ariane_soc::HPS].ar_addr[31:0]),
|
||||
.s_axi_arlen(master[ariane_soc::HPS].ar_len),
|
||||
.s_axi_arsize(master[ariane_soc::HPS].ar_size),
|
||||
.s_axi_arburst(master[ariane_soc::HPS].ar_burst),
|
||||
.s_axi_arlock(master[ariane_soc::HPS].ar_lock),
|
||||
.s_axi_arcache(master[ariane_soc::HPS].ar_cache),
|
||||
.s_axi_arprot(master[ariane_soc::HPS].ar_prot),
|
||||
.s_axi_arregion(master[ariane_soc::HPS].ar_region),
|
||||
.s_axi_arqos(master[ariane_soc::HPS].ar_qos),
|
||||
.s_axi_arvalid(master[ariane_soc::HPS].ar_valid),
|
||||
.s_axi_arready(master[ariane_soc::HPS].ar_ready),
|
||||
.s_axi_rid(master[ariane_soc::HPS].r_id),
|
||||
.s_axi_rdata(master[ariane_soc::HPS].r_data),
|
||||
.s_axi_rresp(master[ariane_soc::HPS].r_resp),
|
||||
.s_axi_rlast(master[ariane_soc::HPS].r_last),
|
||||
.s_axi_rvalid(master[ariane_soc::HPS].r_valid),
|
||||
.s_axi_rready(master[ariane_soc::HPS].r_ready),
|
||||
.m_axi_awaddr(master_to_hps[0].aw_addr),
|
||||
.m_axi_awlen(master_to_hps[0].aw_len),
|
||||
.m_axi_awsize(master_to_hps[0].aw_size),
|
||||
.m_axi_awburst(master_to_hps[0].aw_burst),
|
||||
.m_axi_awlock(master_to_hps[0].aw_lock),
|
||||
.m_axi_awcache(master_to_hps[0].aw_cache),
|
||||
.m_axi_awprot(master_to_hps[0].aw_prot),
|
||||
.m_axi_awregion(master_to_hps[0].aw_region),
|
||||
.m_axi_awqos(master_to_hps[0].aw_qos),
|
||||
.m_axi_awvalid(master_to_hps[0].aw_valid),
|
||||
.m_axi_awready(master_to_hps[0].aw_ready),
|
||||
.m_axi_wdata(master_to_hps[0].w_data ),
|
||||
.m_axi_wstrb(master_to_hps[0].w_strb),
|
||||
.m_axi_wlast(master_to_hps[0].w_last),
|
||||
.m_axi_wvalid(master_to_hps[0].w_valid),
|
||||
.m_axi_wready(master_to_hps[0].w_ready),
|
||||
.m_axi_bresp(master_to_hps[0].b_resp),
|
||||
.m_axi_bvalid(master_to_hps[0].b_valid),
|
||||
.m_axi_bready(master_to_hps[0].b_ready),
|
||||
.m_axi_araddr(master_to_hps[0].ar_addr),
|
||||
.m_axi_arlen(master_to_hps[0].ar_len),
|
||||
.m_axi_arsize(master_to_hps[0].ar_size),
|
||||
.m_axi_arburst(master_to_hps[0].ar_burst),
|
||||
.m_axi_arlock(master_to_hps[0].ar_lock),
|
||||
.m_axi_arcache(master_to_hps[0].ar_cache),
|
||||
.m_axi_arprot(master_to_hps[0].ar_prot),
|
||||
.m_axi_arregion(master_to_hps[0].ar_region),
|
||||
.m_axi_arqos(master_to_hps[0].ar_qos),
|
||||
.m_axi_arvalid(master_to_hps[0].ar_valid),
|
||||
.m_axi_arready(master_to_hps[0].ar_ready),
|
||||
.m_axi_rdata(master_to_hps[0].r_data),
|
||||
.m_axi_rresp(master_to_hps[0].r_resp),
|
||||
.m_axi_rlast(master_to_hps[0].r_last),
|
||||
.m_axi_rvalid(master_to_hps[0].r_valid),
|
||||
.m_axi_rready(master_to_hps[0].r_ready)
|
||||
);
|
||||
|
||||
system hps_minimal (
|
||||
.hps_hps_io_EMAC0_TX_CLK (hps_emac0_TX_CLK), // output, width = 1, hps_hps_io.EMAC0_TX_CLK
|
||||
.hps_hps_io_EMAC0_TXD0 (hps_emac0_TXD0), // output, width = 1, .EMAC0_TXD0
|
||||
.hps_hps_io_EMAC0_TXD1 (hps_emac0_TXD1), // output, width = 1, .EMAC0_TXD1
|
||||
.hps_hps_io_EMAC0_TXD2 (hps_emac0_TXD2), // output, width = 1, .EMAC0_TXD2
|
||||
.hps_hps_io_EMAC0_TXD3 (hps_emac0_TXD3), // output, width = 1, .EMAC0_TXD3
|
||||
.hps_hps_io_EMAC0_RX_CTL (hps_emac0_RX_CTL), // input, width = 1, .EMAC0_RX_CTL
|
||||
.hps_hps_io_EMAC0_TX_CTL (hps_emac0_TX_CTL), // output, width = 1, .EMAC0_TX_CTL
|
||||
.hps_hps_io_EMAC0_RX_CLK (hps_emac0_RX_CLK), // input, width = 1, .EMAC0_RX_CLK
|
||||
.hps_hps_io_EMAC0_RXD0 (hps_emac0_RXD0), // input, width = 1, .EMAC0_RXD0
|
||||
.hps_hps_io_EMAC0_RXD1 (hps_emac0_RXD1), // input, width = 1, .EMAC0_RXD1
|
||||
.hps_hps_io_EMAC0_RXD2 (hps_emac0_RXD2), // input, width = 1, .EMAC0_RXD2
|
||||
.hps_hps_io_EMAC0_RXD3 (hps_emac0_RXD3), // input, width = 1, .EMAC0_RXD3
|
||||
.hps_hps_io_EMAC0_MDIO (hps_emac0_MDIO), // inout, width = 1, .EMAC0_MDIO
|
||||
.hps_hps_io_EMAC0_MDC (hps_emac0_MDC), // output, width = 1, .EMAC0_MDC
|
||||
.hps_hps_io_SDMMC_CMD (hps_sdmmc_CMD), // inout, width = 1, .SDMMC_CMD
|
||||
.hps_hps_io_SDMMC_D0 (hps_sdmmc_D0), // inout, width = 1, .SDMMC_D0
|
||||
.hps_hps_io_SDMMC_D1 (hps_sdmmc_D1), // inout, width = 1, .SDMMC_D1
|
||||
.hps_hps_io_SDMMC_D2 (hps_sdmmc_D2), // inout, width = 1, .SDMMC_D2
|
||||
.hps_hps_io_SDMMC_D3 (hps_sdmmc_D3), // inout, width = 1, .SDMMC_D3
|
||||
.hps_hps_io_SDMMC_CCLK (hps_sdmmc_CCLK), // output, width = 1, .SDMMC_CCLK
|
||||
.hps_hps_io_UART0_RX (hps_uart0_RX), // input, width = 1, .UART0_RX
|
||||
.hps_hps_io_UART0_TX (hps_uart0_TX), // output, width = 1, .UART0_TX
|
||||
.hps_hps_io_I2C1_SDA (hps_i2c1_SDA), // inout, width = 1, .I2C1_SDA
|
||||
.hps_hps_io_I2C1_SCL (hps_i2c1_SCL), // inout, width = 1, .I2C1_SCL
|
||||
.hps_hps_io_gpio1_io0 (hps_gpio1_io0), // inout, width = 1, .gpio1_io0
|
||||
.hps_hps_io_jtag_tck (hps_jtag_tck), // input, width = 1, .jtag_tck
|
||||
.hps_hps_io_jtag_tms (hps_jtag_tms), // input, width = 1, .jtag_tms
|
||||
.hps_hps_io_jtag_tdo (hps_jtag_tdo), // output, width = 1, .jtag_tdo
|
||||
.hps_hps_io_jtag_tdi (hps_jtag_tdi), // input, width = 1, .jtag_tdi
|
||||
.hps_hps_io_hps_osc_clk (hps_ref_clk), // input, width = 1, .hps_osc_clk
|
||||
.h2f_reset_reset (h2f_reset), // output, width = 1, h2f_reset.reset
|
||||
|
||||
.hps_f2h_axi_clock_clk (clk), // input, width = 1, hps_f2h_axi_clock.clk
|
||||
.hps_f2h_axi_reset_reset_n(ndmreset_n), // input, width = 1, hps_f2h_axi_reset.reset_n
|
||||
.hps_emif_pll_ref_clk_clk (emif_hps_pll_ref_clk_p), // input, width = 1, hps_emif_pll_ref_clk.clk
|
||||
.hps_emif_oct_oct_rzqin (emif_hps_oct_oct_rzqin), // input, width = 1, hps_emif_oct.oct_rzqin
|
||||
.hps_emif_mem_mem_ck (emif_hps_mem_mem_ck), // output, width = 1, hps_emif_mem.mem_ck
|
||||
.hps_emif_mem_mem_ck_n (emif_hps_mem_mem_ck_n), // output, width = 1, .mem_ck_n
|
||||
.hps_emif_mem_mem_a (emif_hps_mem_mem_a), // output, width = 17, .mem_a
|
||||
.hps_emif_mem_mem_act_n (emif_hps_mem_mem_act_n), // output, width = 1, .mem_act_n
|
||||
.hps_emif_mem_mem_ba (emif_hps_mem_mem_ba), // output, width = 2, .mem_ba
|
||||
.hps_emif_mem_mem_bg (emif_hps_mem_mem_bg), // output, width = 2, .mem_bg
|
||||
.hps_emif_mem_mem_cke (emif_hps_mem_mem_cke), // output, width = 1, .mem_cke
|
||||
.hps_emif_mem_mem_cs_n (emif_hps_mem_mem_cs_n), // output, width = 1, .mem_cs_n
|
||||
.hps_emif_mem_mem_odt (emif_hps_mem_mem_odt), // output, width = 1, .mem_odt
|
||||
.hps_emif_mem_mem_reset_n (emif_hps_mem_mem_reset_n), // output, width = 1, .mem_reset_n
|
||||
.hps_emif_mem_mem_par (emif_hps_mem_mem_par), // output, width = 1, .mem_par
|
||||
.hps_emif_mem_mem_alert_n (emif_hps_mem_mem_alert_n), // input, width = 1, .mem_alert_n
|
||||
.hps_emif_mem_mem_dqs (emif_hps_mem_mem_dqs), // inout, width = 8, .mem_dqs
|
||||
.hps_emif_mem_mem_dqs_n (emif_hps_mem_mem_dqs_n), // inout, width = 8, .mem_dqs_n
|
||||
.hps_emif_mem_mem_dq (emif_hps_mem_mem_dq), // inout, width = 64, .mem_dq
|
||||
.hps_emif_mem_mem_dbi_n (emif_hps_mem_mem_dbi_n), // inout, width = 8, .mem_dbi_n
|
||||
|
||||
.hps_emif_emif_calbus_calbus_read (calbus_read1), // input, width = 1, hps_emif_emif_calbus.calbus_read
|
||||
.hps_emif_emif_calbus_calbus_write (calbus_write1), // input, width = 1, .calbus_write
|
||||
.hps_emif_emif_calbus_calbus_address (calbus_address1), // input, width = 20, .calbus_address
|
||||
.hps_emif_emif_calbus_calbus_wdata (calbus_wdata1), // input, width = 32, .calbus_wdata
|
||||
.hps_emif_emif_calbus_calbus_rdata (calbus_rdata1), // output, width = 32, .calbus_rdata
|
||||
.hps_emif_emif_calbus_calbus_seq_param_tbl (calbus_seq_param_tbl1), // output, width = 4096, .calbus_seq_param_tbl
|
||||
.hps_emif_emif_calbus_clk_clk (calbus_clk), // input, width = 1, hps_emif_emif_calbus_clk.clk
|
||||
|
||||
.ninit_done_ninit_done (ninit_done), // output, width = 1, ninit_done.ninit_done
|
||||
|
||||
.system_intel_cache_coherency_translator_clock_clk (clk), // input, width = 1, system_intel_cache_coherency_translator_clock.clk
|
||||
.system_intel_cache_coherency_translator_reset_reset (~ndmreset_n), // input, width = 1, system_intel_cache_coherency_translator_reset.reset
|
||||
.system_intel_cache_coherency_translator_s0_araddr (master_to_hps[0].ar_addr), // input, width = 32, system_intel_cache_coherency_translator_s0.araddr
|
||||
.system_intel_cache_coherency_translator_s0_arburst (master_to_hps[0].ar_burst), // input, width = 2, .arburst
|
||||
.system_intel_cache_coherency_translator_s0_arcache (master_to_hps[0].ar_cache), // input, width = 4, .arcache
|
||||
.system_intel_cache_coherency_translator_s0_arid (master_to_hps[0].ar_id), // input, width = 5, .arid
|
||||
.system_intel_cache_coherency_translator_s0_arlen (master_to_hps[0].ar_len), // input, width = 8, .arlen
|
||||
.system_intel_cache_coherency_translator_s0_arlock (master_to_hps[0].ar_lock), // input, width = 1, .arlock
|
||||
.system_intel_cache_coherency_translator_s0_arprot (master_to_hps[0].ar_prot), // input, width = 3, .arprot
|
||||
.system_intel_cache_coherency_translator_s0_arready (master_to_hps[0].ar_ready), // output, width = 1, .arready
|
||||
.system_intel_cache_coherency_translator_s0_arsize (master_to_hps[0].ar_size), // input, width = 3, .arsize
|
||||
.system_intel_cache_coherency_translator_s0_arvalid (master_to_hps[0].ar_valid), // input, width = 1, .arvalid
|
||||
.system_intel_cache_coherency_translator_s0_awaddr (master_to_hps[0].aw_addr), // input, width = 32, .awaddr
|
||||
.system_intel_cache_coherency_translator_s0_awburst (master_to_hps[0].aw_burst), // input, width = 2, .awburst
|
||||
.system_intel_cache_coherency_translator_s0_awcache (master_to_hps[0].aw_cache), // input, width = 4, .awcache
|
||||
.system_intel_cache_coherency_translator_s0_awid (master_to_hps[0].aw_id), // input, width = 5, .awid
|
||||
.system_intel_cache_coherency_translator_s0_awlen (master_to_hps[0].aw_len), // input, width = 8, .awlen
|
||||
.system_intel_cache_coherency_translator_s0_awlock (master_to_hps[0].aw_lock), // input, width = 1, .awlock
|
||||
.system_intel_cache_coherency_translator_s0_awprot (master_to_hps[0].aw_prot), // input, width = 3, .awprot
|
||||
.system_intel_cache_coherency_translator_s0_awready (master_to_hps[0].aw_ready), // output, width = 1, .awready
|
||||
.system_intel_cache_coherency_translator_s0_awsize (master_to_hps[0].aw_size), // input, width = 3, .awsize
|
||||
.system_intel_cache_coherency_translator_s0_awvalid (master_to_hps[0].aw_valid), // input, width = 1, .awvalid
|
||||
.system_intel_cache_coherency_translator_s0_bid (master_to_hps[0].b_id), // output, width = 5, .bid
|
||||
.system_intel_cache_coherency_translator_s0_bready (master_to_hps[0].b_ready), // input, width = 1, .bready
|
||||
.system_intel_cache_coherency_translator_s0_bresp (master_to_hps[0].b_resp), // output, width = 2, .bresp
|
||||
.system_intel_cache_coherency_translator_s0_bvalid (master_to_hps[0].b_valid), // output, width = 1, .bvalid
|
||||
.system_intel_cache_coherency_translator_s0_rdata (master_to_hps[0].r_data), // output, width = 128, .rdata
|
||||
.system_intel_cache_coherency_translator_s0_rid (master_to_hps[0].r_id), // output, width = 5, .rid
|
||||
.system_intel_cache_coherency_translator_s0_rlast (master_to_hps[0].r_last), // output, width = 1, .rlast
|
||||
.system_intel_cache_coherency_translator_s0_rready (master_to_hps[0].r_ready), // input, width = 1, .rready
|
||||
.system_intel_cache_coherency_translator_s0_rresp (master_to_hps[0].r_resp), // output, width = 2, .rresp
|
||||
.system_intel_cache_coherency_translator_s0_rvalid (master_to_hps[0].r_valid), // output, width = 1, .rvalid
|
||||
.system_intel_cache_coherency_translator_s0_wdata (master_to_hps[0].w_data), // input, width = 128, .wdata
|
||||
.system_intel_cache_coherency_translator_s0_wlast (master_to_hps[0].w_last), // input, width = 1, .wlast
|
||||
.system_intel_cache_coherency_translator_s0_wready (master_to_hps[0].w_ready), // output, width = 1, .wready
|
||||
.system_intel_cache_coherency_translator_s0_wstrb (master_to_hps[0].w_strb), // input, width = 16, .wstrb
|
||||
.system_intel_cache_coherency_translator_s0_wvalid (master_to_hps[0].w_valid) // input, width = 1, .wvalid
|
||||
);
|
||||
|
||||
//
|
||||
//clocks
|
||||
|
|
|
|||
|
|
@ -29,12 +29,12 @@ package ariane_soc;
|
|||
PLIC = 6,
|
||||
CLINT = 7,
|
||||
ROM = 8,
|
||||
Debug = 9
|
||||
Debug = 9,
|
||||
HPS = 10
|
||||
} axi_slaves_t;
|
||||
|
||||
localparam NB_PERIPHERALS = Debug + 1;
|
||||
|
||||
|
||||
localparam logic[63:0] DebugLength = 64'h1000;
|
||||
localparam logic[63:0] ROMLength = 64'h10000;
|
||||
localparam logic[63:0] CLINTLength = 64'hC0000;
|
||||
|
|
@ -44,6 +44,7 @@ package ariane_soc;
|
|||
localparam logic[63:0] SPILength = 64'h800000;
|
||||
localparam logic[63:0] EthernetLength = 64'h10000;
|
||||
localparam logic[63:0] GPIOLength = 64'h1000;
|
||||
localparam logic[63:0] HPSLength = 64'h800000;
|
||||
`ifdef NEXYS_VIDEO
|
||||
localparam logic[63:0] DRAMLength = 64'h20000000; // 512MByte of DDR on Nexys video board
|
||||
`else
|
||||
|
|
@ -63,7 +64,8 @@ package ariane_soc;
|
|||
SPIBase = 64'h2000_0000,
|
||||
EthernetBase = 64'h3000_0000,
|
||||
GPIOBase = 64'h4000_0000,
|
||||
DRAMBase = 64'h8000_0000
|
||||
DRAMBase = 64'h8000_0000,
|
||||
HPSBase = 64'hFF80_0000
|
||||
} soc_bus_start_t;
|
||||
|
||||
localparam NrRegion = 1;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue