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[gen_from_riscv_config] improve readme file to support debug spec (#2406)
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1 changed files with 4 additions and 2 deletions
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@ -34,7 +34,7 @@ pip3 install -r requirements.txt
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```bash
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#Generate Restructred-text documentation for Control and Status Registers (CSR)
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python3 <scripts/riscv_config_gen>.py -s <../riscv-config/Config_Name/generated/isa_gen>.yaml -c <../riscv-config/Config_Name/generated/custom_gen>.yaml -m <updaters/Config_Name/csr_updater>.yaml -t < Config_Name>
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python3 <scripts/riscv_config_gen>.py -s <../riscv-config/Config_Name/generated/isa_gen>.yaml -c <../riscv-config/Config_Name/generated/custom_gen>.yaml -d <../riscv-config/Config_Name/generated/debug_gen>.yaml -m <updaters/Config_Name/csr_updater>.yaml -t < Config_Name>
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#Generate Restructred-text documentation for ISA extensions
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python3 <scripts/riscv_config_gen>.py -s <../riscv-config/Config_Name/generated/isa_gen>.yaml -i <templates/isa_template>.yaml -m <updaters/Config_Name/isa_updater>.yaml -t < Config_Name>
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@ -48,7 +48,7 @@ python3 <scripts/riscv_config_gen>.py -s <../riscv-config/Config_Name/generated/
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```bash
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#Generate the Restructred-text documentation for Control and Status Registers (CSR)
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python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_gen.yaml -c ../riscv-config/cv32a65x/generated/custom_gen.yaml -m updaters/cv32a65x/csr_updater.yaml -t cv32a65x
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python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_gen.yaml -c ../riscv-config/cv32a65x/generated/custom_gen.yaml -d ../riscv-config/cv32a65x/generated/debug_gen.yaml -m updaters/cv32a65x/csr_updater.yaml -t cv32a65x
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#Generate the Restructred-text documentation for ISA extensions
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python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_gen.yaml -i templates/isa_template.yaml -m updaters/cv32a65x/isa_updater.yaml -t cv32a65x
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@ -218,6 +218,8 @@ CSR/ISA Updater read RISC-CONFIG.yaml and update the registers so if you want to
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<parameter name> : <parameter value>
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- Exemple :
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Bootroom : true
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- Exemple :
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cores:
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