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[core] Move cache invalidation and fflag signals into acc_dispatcher (#1305)

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Domenic Wüthrich 2023-07-15 02:42:54 +02:00 • committed by GitHub
parent ddafcabb98
commit a49ea21b85
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2 changed files with 33 additions and 27 deletions
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32
core/acc_dispatcher.sv
View file

@ -13,11 +13,16 @@
// Date: 20.11.2020
// Description: Functional unit that dispatches CVA6 instructions to accelerators.
module acc_dispatcher import ariane_pkg::*; import riscv::*; (
module acc_dispatcher import ariane_pkg::*; import riscv::*; #(
parameter type acc_req_t = acc_pkg::accelerator_req_t,
parameter type acc_resp_t = acc_pkg::accelerator_resp_t
) (
input logic clk_i,
input logic rst_ni,
// Interface with the CSR regfile
input logic acc_cons_en_i, // Accelerator memory consistent mode
output logic acc_fflags_valid_o,
output logic [4:0] acc_fflags_o,
// Interface with the CSRs
input logic [2:0] fcsr_frm_i,
output logic dirty_v_state_o,
@ -42,9 +47,13 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; (
output logic ctrl_halt_o,
input logic flush_unissued_instr_i,
input logic flush_ex_i,
// Interface with cache subsystem
input logic inval_ready_i,
output logic inval_valid_o,
output logic [63:0] inval_addr_o,
// Accelerator interface
output acc_pkg::accelerator_req_t acc_req_o,
input acc_pkg::accelerator_resp_t acc_resp_i
output acc_req_t acc_req_o,
input acc_resp_t acc_resp_i
);
`include "common_cells/registers.svh"
@ -197,8 +206,7 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; (
assign acc_req_o.trans_id = acc_req_int.trans_id;
assign acc_req_o.store_pending = !acc_no_st_pending_i && acc_cons_en_i;
assign acc_req_o.acc_cons_en = acc_cons_en_i;
// Will be overwritten by dcache
assign acc_req_o.inval_ready = '0;
assign acc_req_o.inval_ready = inval_ready_i;
always_comb begin: accelerator_req_dispatcher
// Do not fetch from the instruction queue
@ -238,14 +246,16 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; (
logic acc_st_disp;
// Unpack the accelerator response
assign acc_trans_id_o = acc_resp_i.trans_id;
assign acc_result_o = acc_resp_i.result;
assign acc_valid_o = acc_resp_i.resp_valid;
assign acc_exception_o = '{
assign acc_trans_id_o = acc_resp_i.trans_id;
assign acc_result_o = acc_resp_i.result;
assign acc_valid_o = acc_resp_i.resp_valid;
assign acc_exception_o = '{
cause: riscv::ILLEGAL_INSTR,
tval : '0,
valid: acc_resp_i.error
};
assign acc_fflags_valid_o = acc_resp_i.fflags_valid;
assign acc_fflags_o = acc_resp_i.fflags;
// Always ready to receive responses
assign acc_req_o.resp_ready = 1'b1;
@ -253,6 +263,10 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; (
assign acc_ld_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_LOAD);
assign acc_st_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_STORE);
// Cache invalidation
assign inval_valid_o = acc_resp_i.inval_valid;
assign inval_addr_o = acc_resp_i.inval_addr;
/**************************
* Accelerator commit *
**************************/

28
core/cva6.sv
View file

@ -848,14 +848,17 @@ module cva6 import ariane_pkg::*; #(
// ----------------
if (ENABLE_ACCELERATOR) begin: gen_accelerator
acc_pkg::accelerator_req_t acc_req;
acc_dispatcher i_acc_dispatcher (
acc_dispatcher #(
.acc_req_t ( cvxif_req_t ),
.acc_resp_t ( cvxif_resp_t )
) i_acc_dispatcher (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.flush_unissued_instr_i ( flush_unissued_instr_ctrl_id ),
.flush_ex_i ( flush_ctrl_ex ),
.acc_cons_en_i ( acc_cons_en_csr ),
.acc_fflags_valid_o ( acc_resp_fflags_valid ),
.acc_fflags_o ( acc_resp_fflags ),
.fcsr_frm_i ( frm_csr_id_issue_ex ),
.dirty_v_state_o ( dirty_v_state ),
.issue_instr_i ( issue_instr_id_acc ),
@ -872,23 +875,12 @@ module cva6 import ariane_pkg::*; #(
.commit_ack_i ( commit_ack ),
.acc_no_st_pending_i ( no_st_pending_commit ),
.ctrl_halt_o ( halt_acc_ctrl ),
.acc_req_o ( acc_req ),
.inval_ready_i ( inval_ready ),
.inval_valid_o ( inval_valid ),
.inval_addr_o ( inval_addr ),
.acc_req_o ( cvxif_req_o ),
.acc_resp_i ( cvxif_resp_i )
);
assign acc_resp_fflags = cvxif_resp_i.fflags;
assign acc_resp_fflags_valid = cvxif_resp_i.fflags_valid;
// Pack invalidation interface into accelerator interface
always_comb begin : pack_inval
inval_valid = cvxif_resp_i.inval_valid;
inval_addr = cvxif_resp_i.inval_addr;
cvxif_req_o = acc_req;
cvxif_req_o.inval_ready = inval_ready;
end
// Tie off cvxif
assign cvxif_resp = '0;
end : gen_accelerator else begin: gen_no_accelerator
assign acc_trans_id_ex_id = '0;
assign acc_result_ex_id = '0;