🐛 Fix in sret and outdated WB

src/csr_regfile.sv

@@ -412,7 +412,7 @@ module csr_regfile #(
                 // the return should not have any write or read side-effects
                 csr_we   = 1'b0;
                 csr_read = 1'b0;
-                sret     = 1'b0; // signal a return from supervisor mode
+                sret     = 1'b1; // signal a return from supervisor mode
             end
             MRET: begin
                 // the return should not have any write or read side-effects

src/scoreboard.sv

@@ -113,7 +113,9 @@ module scoreboard #(
         // Write Back
         // ------------
         for (int i = 0; i < NR_WB_PORTS; i++) begin
-            if (wb_valid_i[i]) begin
+            // check if this instruction was issued (e.g.: it could happen after a flush that there is still
+            // something in the pipeline e.g. an incomplete memory operation)
+            if (wb_valid_i[i] && mem_n[trans_id_i[i]].issued) begin
                 mem_n[trans_id_i[i]].sbe.valid  = 1'b1;
                 mem_n[trans_id_i[i]].sbe.result = wdata_i[i];
                 // write the exception back if it is valid

tb/common/core_mem.sv

@@ -42,7 +42,7 @@ module core_mem (
     output logic [63:0]              data_if_data_rdata_o
 );
     // we always grant the access
-    localparam ADDRESS_WIDTH = 11;
+    localparam ADDRESS_WIDTH = 16;
 
     logic [ADDRESS_WIDTH-1:0] instr_address;
     logic [2:0]               instr_address_offset_q;