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openocd: Add multi-hart config

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Michael Schaffner 2019-04-17 19:29:07 +02:00 • committed by Florian Zaruba
parent cc7905cf4a
commit a5ee31d2cc
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2 changed files with 43 additions and 3 deletions
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40
fpga/ariane-multi-hart.cfg Normal file
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@ -0,0 +1,40 @@
adapter_khz 1000
interface ftdi
ftdi_vid_pid 0x0403 0x6010
# Channel 1 is taken by Xilinx JTAG
ftdi_channel 0
# links:
# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html
#
# Bit MPSSE FT2232 JTAG Type Description
# Bit0 TCK ADBUS0 TCK Out Clock Signal Output
# Bit1 TDI ADBUS1 TDI Out Serial Data Out
# Bit2 TDO ADBUS2 TDO In Serial Data In
# Bit3 TMS ADBUS3 TMS Out Select Signal Out
# Bit4 GPIOL0 ADBUS4 nTRST In/Out General Purpose I/O
# this corresponds to the following in/out layout, with TMS initially set to 1
ftdi_layout_init 0x0018 0x001b
# we only have to specify nTRST, the others are assigned correctly by default
ftdi_layout_signal nTRST -ndata 0x0010
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
gdb_report_data_abort enable
gdb_report_register_access_error enable
riscv set_reset_timeout_sec 120
riscv set_command_timeout_sec 120
# prefer to use sba for system bus access
riscv set_prefer_sba off
init
halt
echo "Ready for Remote Connections"

6
fpga/ariane.cfg
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@ -8,13 +8,13 @@ ftdi_channel 0
# links:
# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html
#
#
# Bit MPSSE FT2232 JTAG Type Description
# Bit0 TCK ADBUS0 TCK Out Clock Signal Output
# Bit1 TDI ADBUS1 TDI Out Serial Data Out
# Bit2 TDO ADBUS2 TDO In Serial Data In
# Bit3 TMS ADBUS3 TMS Out Select Signal Out
# Bit4 GPIOL0 ADBUS4 nTRST In/Out General Purpose I/O
# Bit4 GPIOL0 ADBUS4 nTRST In/Out General Purpose I/O
# this corresponds to the following in/out layout, with TMS initially set to 1
ftdi_layout_init 0x0018 0x001b
# we only have to specify nTRST, the others are assigned correctly by default
@ -24,7 +24,7 @@ set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
gdb_report_data_abort enable
gdb_report_register_access_error enable