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revert sram wrapper interface and module name

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This commit is contained in:
Michael Schaffner 2018-08-24 19:14:08 +02:00
parent cca0d66fab
commit a6a1af9af8
5 changed files with 21 additions and 19 deletions
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6
Makefile
View file

@ -29,7 +29,8 @@ ariane_pkg := include/riscv_pkg.sv \
util := $(wildcard src/util/*.svh) \
src/util/instruction_tracer_pkg.sv \
src/util/instruction_tracer_if.sv \
src/util/cluster_clock_gating.sv
src/util/cluster_clock_gating.sv \
src/util/sram.sv
# Test packages
test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \
@ -160,7 +161,8 @@ check-benchmarks:
verilate_command := $(verilator) \
$(ariane_pkg) \
$(filter-out tb/ariane_bt.sv,$(src)) \
+incdir+src/axi_node \
src/util/sram.sv \
+incdir+src/axi_node \
--unroll-count 256 \
-Werror-PINMISSING \
-Werror-IMPLICIT \

8
src/icache.sv
View file

@ -77,10 +77,10 @@ module icache #(
// ------------
// Tag RAM
// ------------
sram_wrap #(
sram #(
// tag + valid bit
.DATA_WIDTH ( ICACHE_TAG_WIDTH + 1 ),
.DATA_DEPTH ( ICACHE_NUM_WORD )
.NUM_WORDS ( ICACHE_NUM_WORD )
) tag_sram (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
@ -94,9 +94,9 @@ module icache #(
// ------------
// Data RAM
// ------------
sram_wrap #(
sram #(
.DATA_WIDTH ( ICACHE_LINE_WIDTH ),
.DATA_DEPTH ( ICACHE_NUM_WORD )
.NUM_WORDS ( ICACHE_NUM_WORD )
) data_sram (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),

8
src/nbdcache.sv
View file

@ -159,9 +159,9 @@ module nbdcache #(
// Memory Arrays
// --------------
for (genvar i = 0; i < DCACHE_SET_ASSOC; i++) begin : sram_block
sram_wrap #(
sram #(
.DATA_WIDTH ( DCACHE_LINE_WIDTH ),
.DATA_DEPTH ( DCACHE_NUM_WORDS )
.NUM_WORDS ( DCACHE_NUM_WORDS )
) data_sram (
.req_i ( req_ram [i] ),
.rst_ni ( rst_ni ),
@ -173,9 +173,9 @@ module nbdcache #(
.*
);
sram_wrap #(
sram #(
.DATA_WIDTH ( DCACHE_TAG_WIDTH ),
.DATA_DEPTH ( DCACHE_NUM_WORDS )
.NUM_WORDS ( DCACHE_NUM_WORDS )
) tag_sram (
.req_i ( req_ram [i] ),
.rst_ni ( rst_ni ),

14
src/sram_wrap.sv → src/util/sram.sv
View file

@ -18,16 +18,16 @@
// inferrable RAMS with byte enable. define `FPGA_TARGET_XILINX or
// `FPGA_TARGET_ALTERA in your build environment (default is ALTERA)
module sram_wrap #(
module sram #(
parameter DATA_WIDTH = 64,
parameter DATA_DEPTH = 1024,
parameter OUT_REGS = 0 // enables output registers in FPGA macro (read lat = 2)
parameter NUM_WORDS = 1024,
parameter OUT_REGS = 0 // enables output registers in FPGA macro (read lat = 2)
)(
input logic clk_i,
input logic rst_ni,
input logic req_i,
input logic we_i,
input logic [$clog2(DATA_DEPTH)-1:0] addr_i,
input logic [$clog2(NUM_WORDS)-1:0] addr_i,
input logic [DATA_WIDTH-1:0] wdata_i,
input logic [(DATA_WIDTH+7)/8-1:0] be_i,
output logic [DATA_WIDTH-1:0] rdata_o
@ -55,8 +55,8 @@ generate
for (k = 0; k<(DATA_WIDTH+63)/64; k++) begin
// unused byte-enable segments (8bits) are culled by the tool
SyncSpRamBeNx64 #(
.ADDR_WIDTH($clog2(DATA_DEPTH)),
.DATA_DEPTH(DATA_DEPTH),
.ADDR_WIDTH($clog2(NUM_WORDS)),
.DATA_DEPTH(NUM_WORDS),
.OUT_REGS (0)
) i_ram (
.Clk_CI ( clk_i ),
@ -71,4 +71,4 @@ generate
end
endgenerate
endmodule : sram_wrap
endmodule : sram

4
tb/ariane_testharness.sv
View file

@ -252,9 +252,9 @@ module ariane_testharness #(
.data_i ( rdata )
);
sram_wrap #(
sram #(
.DATA_WIDTH ( AXI_DATA_WIDTH ),
.DATA_DEPTH ( NUM_WORDS )
.NUM_WORDS ( NUM_WORDS )
) i_sram (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),