Remove potential collisions on regfile

Bender.yml

@@ -5,19 +5,19 @@ package:
 dependencies:
   axi: { git: "git@iis-git.ee.ethz.ch:sasa/axi.git", rev: master }
   axi2per: { git: "git@iis-git.ee.ethz.ch:pulp-open/axi2per.git", rev: master }
-  axi_mem_if: { git: "git@iis-git.ee.ethz.ch:pulp-open/axi_mem_if.git", version: 0.1.1 }
+  axi_mem_if: { git: "git@github.com:pulp-platform/axi_mem_if.git", rev: master }
   axi_node: { git: "git@iis-git.ee.ethz.ch:pulp-open/axi_node.git", version: 1.0.3 }
   axi_slice: { git: "git@iis-git.ee.ethz.ch:sasa/axi_slice.git", version: 1.1.2 }
   tech_cells_generic: { git: "git@iis-git.ee.ethz.ch:pulp-open/tech_cells_generic.git", rev: master }
   common_cells: { git: "git@iis-git.ee.ethz.ch:sasa/common_cells.git", version: 1.1.0 }
 
 sources:
+  - include/ariane_pkg.sv
+  - include/nbdcache_pkg.sv
   - target: not(synthesis)
     files:
       - src/util/instruction_tracer_pkg.sv
       - src/util/instruction_tracer_if.sv
-  - include/ariane_pkg.sv
-  - include/nbdcache_pkg.sv
   - src/alu.sv
   - src/ariane.sv
   - src/branch_unit.sv
@@ -32,7 +32,7 @@ sources:
   - src/ex_stage.sv
   - src/fetch_fifo.sv
   - src/ff1.sv
-  - src/fifo.sv
+  # - src/fifo.sv
   - src/frontend.sv
   - src/icache.sv
   - src/id_stage.sv

Makefile

@@ -173,7 +173,7 @@ $(tests): build
 
 # User Verilator
 verilate:
-	$(verilator) $(ariane_pkg) $(filter-out src/regfile.sv, $(wildcard src/*.sv)) $(wildcard src/axi_slice/*.sv) \
+	$(verilator) $(ariane_pkg) $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) $(wildcard src/axi_slice/*.sv) \
 	src/util/cluster_clock_gating.sv src/util/behav_sram.sv src/axi_mem_if/axi2mem.sv tb/agents/axi_if/axi_if.sv \
 	--unroll-count 1024 -Wno-fatal -Wno-UNOPTFLAT -LDFLAGS "-lfesvr" -CFLAGS "-std=c++11" -Wall --cc --trace \
 	$(list_incdir) --top-module ariane_wrapped --exe tb/ariane_tb.cpp tb/simmem.cpp

src/ariane_regfile.sv

@@ -23,11 +23,9 @@
 //                 latches and is thus smaller than the flip-flop based RF.
 //
 
-module regfile
-#(
+module ariane_regfile #(
   parameter DATA_WIDTH    = 32
-)
-(
+)(
   // Clock and Reset
   input  logic                   clk,
   input  logic                   rst_n,

src/ariane_regfile_ff.sv

@@ -22,11 +22,9 @@
 //                 flip flops.
 //
 
-module regfile
-#(
+module ariane_regfile #(
   parameter DATA_WIDTH    = 32
-)
-(
+)(
   // Clock and Reset
   input  logic                   clk,
   input  logic                   rst_n,

src/issue_read_operands.sv

@@ -307,7 +307,7 @@ module issue_read_operands #(
     // ----------------------
     // Integer Register File
     // ----------------------
-    regfile #(
+    ariane_regfile #(
         .DATA_WIDTH     ( 64                     )
     ) regfile_i (
         // Clock and Reset