mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-20 12:17:19 -04:00
Mature peripherals
This commit is contained in:
Florian Zaruba
parent
c1cac77ac4
commit
a8bcb23d51
12 changed files with 387 additions and 434 deletions
11
Makefile
11
Makefile
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@ -53,7 +53,6 @@ test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \
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$(wildcard tb/test/*/*_pkg.sv*)
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# DPI
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dpi := $(patsubst tb/dpi/%.cc,${dpi-library}/%.o,$(wildcard tb/dpi/*.cc))
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dpi := $(addprefix $(root-dir), $(dpi))
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dpi_hdr := $(wildcard tb/dpi/*.h)
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dpi_hdr := $(addprefix $(root-dir), $(dpi_hdr))
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@ -63,6 +62,9 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
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$(wildcard src/cache_subsystem/*.sv) \
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$(wildcard bootrom/*.sv) \
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$(wildcard src/clint/*.sv) \
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$(wildcard fpga/src/apb_uart/src/*.vhd) \
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$(wildcard fpga/src/axi2apb/src/*.sv) \
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$(wildcard fpga/src/axi_slice/src/*.sv) \
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$(wildcard src/plic/*.sv) \
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$(filter-out src/register_interface/src/reg_intf.sv, \
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$(wildcard src/register_interface/src/*.sv)) \
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@ -70,6 +72,7 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
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$(wildcard src/axi_mem_if/src/*.sv) \
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$(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) \
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$(wildcard src/debug/debug_rom/*.sv) \
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fpga/src/ariane_peripherals.sv \
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src/axi/src/axi_multicut.sv \
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src/axi/src/axi_cut.sv \
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src/axi/src/axi_join.sv \
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@ -86,7 +89,7 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
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src/common_cells/src/lfsr_8bit.sv \
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src/common_cells/src/rstgen_bypass.sv \
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tb/ariane_testharness.sv \
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tb/common/mock_uartlite.sv \
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tb/common/uart.sv \
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tb/common/SimDTM.sv \
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tb/common/SimJTAG.sv
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src := $(addprefix $(root-dir), $(src))
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@ -112,6 +115,7 @@ incdir :=
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# Compile and sim flags
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compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+$(defines)
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uvm-flags += +UVM_NO_RELNOTES
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compile_flag_vhd += -64 -nologo -quiet -2008
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# Iterate over all include directories and write them with +incdir+ prefixed
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# +incdir+ works for Verilator and QuestaSim
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list_incdir := $(foreach dir, ${incdir}, +incdir+$(dir))
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@ -128,9 +132,10 @@ build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ari
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# src files
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$(library)/.build-srcs: $(ariane_pkg) $(util) $(src) $(library)
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vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583
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vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(src))
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vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583
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# Suppress message that always_latch may not be checked thoroughly by QuestaSim.
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vlog$(questa_version) $(compile_flag) -work $(library) -pedanticerrors $(src) $(list_incdir) -suppress 2583
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vlog$(questa_version) $(compile_flag) -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(list_incdir) -suppress 2583
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touch $(library)/.build-srcs
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# build TBs
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@ -10,13 +10,14 @@
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#size-cells = <0>;
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timebase-frequency = <25000000>;
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CPU0: cpu@0 {
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clock-frequency = <0>;
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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compatible = "eth, ariane", "riscv";
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riscv,isa = "rv64imac";
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riscv,isa = "rv64imacsu";
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mmu-type = "riscv,sv39";
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clock-frequency = <50000000>;
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timebase-frequency = <25000000>;
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tlb-split;
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// HLIC - hart local interrupt controller
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CPU0_intc: interrupt-controller {
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@ -28,7 +29,7 @@
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x2000000>;
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reg = <0x0 0x80000000 0x0 0x8000000>;
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};
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soc {
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#address-cells = <2>;
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@ -37,8 +38,9 @@
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ranges;
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clint@2000000 {
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compatible = "riscv,clint0";
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interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7 >;
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interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>;
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reg = <0x0 0x2000000 0x0 0xc0000>;
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reg-names = "control";
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};
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PLIC0: interrupt-controller@c000000 {
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#address-cells = <0>;
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@ -57,23 +59,16 @@
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reg-names = "control";
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};
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uart@10000000 {
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compatible = "xlnx,axi-uartlite-1.02.a";
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reg = <0x0 0x10000000 0x0 0x10000>;
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compatible = "ns16750";
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reg = <0x0 0x10000000 0x0 0x1000>;
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clock-frequency = <50000000>;
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interrupt-parent = <&PLIC0>;
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interrupts = <0 1>; // rising edge triggered on port 0
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clock = <50000000>;
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interrupts = <1>;
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reg-shift = <2>; //regs are spaced on 32 bit boundary
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reg-io-width = <4>; // only 32-bit access are supported
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};
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// uart@10000000 {
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// compatible = "ns16550";
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// reg = <0x10000000 0x100>;
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// clock-frequency = <50000000>;
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// interrupt-parent = <&PLIC0>;
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// interrupts = <0 4>;
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// reg-shift = <2>; // regs are spaced on 32 bit boundary
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// reg-io-width = <4>; // only 32-bit access are supported
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// };
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};
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htif {
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compatible = "ucb,htif0";
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chosen {
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stdout-path = "/uart@10000000";
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};
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};
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@ -22,11 +22,11 @@ filename = os.path.splitext(file)[0]
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license = """\
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/* Copyright 2018 ETH Zurich and University of Bologna.
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* Copyright and related rights are licensed under the Solderpad Hardware
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* License, Version 0.51 (the “License”); you may not use this file except in
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* License, Version 0.51 (the "License"); you may not use this file except in
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* compliance with the License. You may obtain a copy of the License at
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* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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* or agreed to in writing, software, hardware and materials distributed under
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* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
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* this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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* CONDITIONS OF ANY KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations under the License.
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*
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@ -59,7 +59,9 @@ module $filename (
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end
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end
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assign rdata_o = mem[addr_q];
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// this prevents spurious Xes from propagating into
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// the speculative fetch stage of the core
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assign rdata_o = (addr_q < RomSize) ? mem[addr_q] : '0;
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endmodule
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"""
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@ -75,11 +77,11 @@ with open(filename + ".img", "rb") as f:
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if i == 4:
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word = "_" + word
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if byte:
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word = byte.hex() + word
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word = ("%02X" % int.from_bytes(byte, "little")) + word
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# fill up with zeros if unaligned
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else:
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pass
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# word += "00";
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word = "00" + word;
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if word != "_":
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word = "64'h" + word
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@ -109,4 +111,4 @@ with open(filename + ".sv", "w") as f:
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s = Template(module)
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f.write(s.substitute(filename=filename, size=i, content=rom_str))
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f.close()
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f.close()
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@ -43,13 +43,13 @@
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BAUDRATE">9600</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BAUDRATE">115200</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_BITS">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ODD_PARITY">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ACLK_FREQ_HZ">50000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PARITY">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BAUDRATE">9600</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BAUDRATE">115200</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DATA_BITS">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ODD_PARITY">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_ACLK_FREQ_HZ">50000000</spirit:configurableElementValue>
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@ -82,6 +82,7 @@
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<spirit:vendorExtensions>
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<xilinx:componentInstanceExtensions>
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<xilinx:configElementInfos>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BAUDRATE" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_S_AXI_ACLK_FREQ_HZ" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_S_AXI_ACLK_FREQ_HZ_d" xilinx:valueSource="user"/>
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</xilinx:configElementInfos>
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@ -9,3 +9,4 @@ set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_ds
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@ -26,15 +26,35 @@ set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports {led[6]}]
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set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports {led[7]}]
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## Switches
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set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS12 } [get_ports { sw[0] }]; #IO_0_17 Sch=sw[0]
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set_property -dict { PACKAGE_PIN G25 IOSTANDARD LVCMOS12 } [get_ports { sw[1] }]; #IO_25_16 Sch=sw[1]
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set_property -dict { PACKAGE_PIN H24 IOSTANDARD LVCMOS12 } [get_ports { sw[2] }]; #IO_L19P_T3_16 Sch=sw[2]
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set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS12 } [get_ports { sw[3] }]; #IO_L6P_T0_17 Sch=sw[3]
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set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS12 } [get_ports { sw[4] }]; #IO_L19P_T3_A22_15 Sch=sw[4]
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set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS12 } [get_ports { sw[5] }]; #IO_25_15 Sch=sw[5]
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set_property -dict { PACKAGE_PIN P26 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L10P_T1_D14_14 Sch=sw[6]
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set_property -dict { PACKAGE_PIN P27 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L8P_T1_D11_14 Sch=sw[7]
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set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS12} [get_ports {sw[0]}]
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set_property -dict {PACKAGE_PIN G25 IOSTANDARD LVCMOS12} [get_ports {sw[1]}]
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set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS12} [get_ports {sw[2]}]
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set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS12} [get_ports {sw[3]}]
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set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS12} [get_ports {sw[4]}]
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set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS12} [get_ports {sw[5]}]
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set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS33} [get_ports {sw[6]}]
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set_property -dict {PACKAGE_PIN P27 IOSTANDARD LVCMOS33} [get_ports {sw[7]}]
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## Fan Control
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set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { fan_pwm }]; #IO_25_14 Sch=fan_pwm
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#set_property -dict { PACKAGE_PIN V21 IOSTANDARD LVCMOS33 } [get_ports { FAN_TACH }]; #IO_L22P_T3_A05_D21_14 Sch=fan_tac
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set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports fan_pwm]
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#set_property -dict { PACKAGE_PIN V21 IOSTANDARD LVCMOS33 } [get_ports { FAN_TACH }]; #IO_L22P_T3_A05_D21_14 Sch=fan_tac
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## Ethernet
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#set_property -dict { PACKAGE_PIN AH24 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_n }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n
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#set_property -dict { PACKAGE_PIN AK14 IOSTANDARD LVCMOS15 } [get_ports { eth_tx_en }]; #IO_L20P_T3_33 Sch=eth_tx_en
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#set_property -dict { PACKAGE_PIN AG10 IOSTANDARD LVCMOS15 } [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
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#set_property -dict { PACKAGE_PIN AJ12 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
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#set_property -dict { PACKAGE_PIN AK11 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
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#set_property -dict { PACKAGE_PIN AJ11 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
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#set_property -dict { PACKAGE_PIN AK10 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
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#set_property -dict { PACKAGE_PIN AJ14 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
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#set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
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#set_property -dict { PACKAGE_PIN AK13 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
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#set_property -dict { PACKAGE_PIN AJ13 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
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#set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS15 } [get_ports { eth_txck }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
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#set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc
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#set_property -dict { PACKAGE_PIN AG12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio
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#set_property -dict { PACKAGE_PIN AK15 IOSTANDARD LVCMOS18 } [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
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#set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS15 } [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
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#set_property -dict { PACKAGE_PIN AK16 IOSTANDARD LVCMOS18 } [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
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@ -75,227 +75,165 @@ module ariane_peripherals #(
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// ---------------
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// UART
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// ---------------
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logic [31:0] s_axi_uart_awaddr;
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logic [7:0] s_axi_uart_awlen;
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logic [2:0] s_axi_uart_awsize;
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logic [1:0] s_axi_uart_awburst;
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logic [0:0] s_axi_uart_awlock;
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logic [3:0] s_axi_uart_awcache;
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logic [2:0] s_axi_uart_awprot;
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logic [3:0] s_axi_uart_awregion;
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logic [3:0] s_axi_uart_awqos;
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logic s_axi_uart_awvalid;
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logic s_axi_uart_awready;
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logic [31:0] s_axi_uart_wdata;
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logic [3:0] s_axi_uart_wstrb;
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logic s_axi_uart_wlast;
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logic s_axi_uart_wvalid;
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logic s_axi_uart_wready;
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logic [1:0] s_axi_uart_bresp;
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logic s_axi_uart_bvalid;
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logic s_axi_uart_bready;
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logic [31:0] s_axi_uart_araddr;
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logic [7:0] s_axi_uart_arlen;
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logic [2:0] s_axi_uart_arsize;
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logic [1:0] s_axi_uart_arburst;
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logic [0:0] s_axi_uart_arlock;
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logic [3:0] s_axi_uart_arcache;
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logic [2:0] s_axi_uart_arprot;
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logic [3:0] s_axi_uart_arregion;
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logic [3:0] s_axi_uart_arqos;
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logic s_axi_uart_arvalid;
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logic s_axi_uart_arready;
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logic [31:0] s_axi_uart_rdata;
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logic [1:0] s_axi_uart_rresp;
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logic s_axi_uart_rlast;
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logic s_axi_uart_rvalid;
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logic s_axi_uart_rready;
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logic uart_penable;
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logic uart_pwrite;
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logic [31:0] uart_paddr;
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logic uart_psel;
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logic [31:0] uart_pwdata;
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logic [31:0] uart_prdata;
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logic uart_pready;
|
||||
logic uart_pslverr;
|
||||
|
||||
logic [31:0] m_axi_uart_awaddr;
|
||||
logic m_axi_uart_awvalid;
|
||||
logic m_axi_uart_awready;
|
||||
logic [31:0] m_axi_uart_wdata;
|
||||
logic [3:0] m_axi_uart_wstrb;
|
||||
logic m_axi_uart_wvalid;
|
||||
logic m_axi_uart_wready;
|
||||
logic [1:0] m_axi_uart_bresp;
|
||||
logic m_axi_uart_bvalid;
|
||||
logic m_axi_uart_bready;
|
||||
logic [31:0] m_axi_uart_araddr;
|
||||
logic m_axi_uart_arvalid;
|
||||
logic m_axi_uart_arready;
|
||||
logic [31:0] m_axi_uart_rdata;
|
||||
logic [1:0] m_axi_uart_rresp;
|
||||
logic m_axi_uart_rvalid;
|
||||
logic m_axi_uart_rready;
|
||||
|
||||
axi_dwidth_converter_0 i_axi_dwidth_converter (
|
||||
.s_axi_aclk ( clk_i ),
|
||||
.s_axi_aresetn ( rst_ni ),
|
||||
|
||||
.s_axi_awid ( uart.aw_id ),
|
||||
.s_axi_awaddr ( uart.aw_addr[31:0] ),
|
||||
.s_axi_awlen ( uart.aw_len ),
|
||||
.s_axi_awsize ( uart.aw_size ),
|
||||
.s_axi_awburst ( uart.aw_burst ),
|
||||
.s_axi_awlock ( uart.aw_lock ),
|
||||
.s_axi_awcache ( uart.aw_cache ),
|
||||
.s_axi_awprot ( uart.aw_prot ),
|
||||
.s_axi_awregion ( uart.aw_region ),
|
||||
.s_axi_awqos ( uart.aw_qos ),
|
||||
.s_axi_awvalid ( uart.aw_valid ),
|
||||
.s_axi_awready ( uart.aw_ready ),
|
||||
.s_axi_wdata ( uart.w_data ),
|
||||
.s_axi_wstrb ( uart.w_strb ),
|
||||
.s_axi_wlast ( uart.w_last ),
|
||||
.s_axi_wvalid ( uart.w_valid ),
|
||||
.s_axi_wready ( uart.w_ready ),
|
||||
.s_axi_bid ( uart.b_id ),
|
||||
.s_axi_bresp ( uart.b_resp ),
|
||||
.s_axi_bvalid ( uart.b_valid ),
|
||||
.s_axi_bready ( uart.b_ready ),
|
||||
.s_axi_arid ( uart.ar_id ),
|
||||
.s_axi_araddr ( uart.ar_addr[31:0] ),
|
||||
.s_axi_arlen ( uart.ar_len ),
|
||||
.s_axi_arsize ( uart.ar_size ),
|
||||
.s_axi_arburst ( uart.ar_burst ),
|
||||
.s_axi_arlock ( uart.ar_lock ),
|
||||
.s_axi_arcache ( uart.ar_cache ),
|
||||
.s_axi_arprot ( uart.ar_prot ),
|
||||
.s_axi_arregion ( uart.ar_region ),
|
||||
.s_axi_arqos ( uart.ar_qos ),
|
||||
.s_axi_arvalid ( uart.ar_valid ),
|
||||
.s_axi_arready ( uart.ar_ready ),
|
||||
.s_axi_rid ( uart.r_id ),
|
||||
.s_axi_rdata ( uart.r_data ),
|
||||
.s_axi_rresp ( uart.r_resp ),
|
||||
.s_axi_rlast ( uart.r_last ),
|
||||
.s_axi_rvalid ( uart.r_valid ),
|
||||
.s_axi_rready ( uart.r_ready ),
|
||||
|
||||
.m_axi_awaddr ( s_axi_uart_awaddr ),
|
||||
.m_axi_awlen ( s_axi_uart_awlen ),
|
||||
.m_axi_awsize ( s_axi_uart_awsize ),
|
||||
.m_axi_awburst ( s_axi_uart_awburst ),
|
||||
.m_axi_awlock ( s_axi_uart_awlock ),
|
||||
.m_axi_awcache ( s_axi_uart_awcache ),
|
||||
.m_axi_awprot ( s_axi_uart_awprot ),
|
||||
.m_axi_awregion ( s_axi_uart_awregion ),
|
||||
.m_axi_awqos ( s_axi_uart_awqos ),
|
||||
.m_axi_awvalid ( s_axi_uart_awvalid ),
|
||||
.m_axi_awready ( s_axi_uart_awready ),
|
||||
.m_axi_wdata ( s_axi_uart_wdata ),
|
||||
.m_axi_wstrb ( s_axi_uart_wstrb ),
|
||||
.m_axi_wlast ( s_axi_uart_wlast ),
|
||||
.m_axi_wvalid ( s_axi_uart_wvalid ),
|
||||
.m_axi_wready ( s_axi_uart_wready ),
|
||||
.m_axi_bresp ( s_axi_uart_bresp ),
|
||||
.m_axi_bvalid ( s_axi_uart_bvalid ),
|
||||
.m_axi_bready ( s_axi_uart_bready ),
|
||||
.m_axi_araddr ( s_axi_uart_araddr ),
|
||||
.m_axi_arlen ( s_axi_uart_arlen ),
|
||||
.m_axi_arsize ( s_axi_uart_arsize ),
|
||||
.m_axi_arburst ( s_axi_uart_arburst ),
|
||||
.m_axi_arlock ( s_axi_uart_arlock ),
|
||||
.m_axi_arcache ( s_axi_uart_arcache ),
|
||||
.m_axi_arprot ( s_axi_uart_arprot ),
|
||||
.m_axi_arregion ( s_axi_uart_arregion ),
|
||||
.m_axi_arqos ( s_axi_uart_arqos ),
|
||||
.m_axi_arvalid ( s_axi_uart_arvalid ),
|
||||
.m_axi_arready ( s_axi_uart_arready ),
|
||||
.m_axi_rdata ( s_axi_uart_rdata ),
|
||||
.m_axi_rresp ( s_axi_uart_rresp ),
|
||||
.m_axi_rlast ( s_axi_uart_rlast ),
|
||||
.m_axi_rvalid ( s_axi_uart_rvalid ),
|
||||
.m_axi_rready ( s_axi_uart_rready )
|
||||
axi2apb_64_32 #(
|
||||
.AXI4_ADDRESS_WIDTH ( AxiAddrWidth ),
|
||||
.AXI4_RDATA_WIDTH ( AxiDataWidth ),
|
||||
.AXI4_WDATA_WIDTH ( AxiDataWidth ),
|
||||
.AXI4_ID_WIDTH ( $bits(uart.aw_id) ),
|
||||
.AXI4_USER_WIDTH ( $bits(uart.aw_user) ),
|
||||
.BUFF_DEPTH_SLAVE ( 2 ),
|
||||
.APB_ADDR_WIDTH ( 32 )
|
||||
) i_axi2apb_64_32 (
|
||||
.ACLK ( clk_i ),
|
||||
.ARESETn ( rst_ni ),
|
||||
.test_en_i ( 1'b0 ),
|
||||
.AWID_i ( uart.aw_id ),
|
||||
.AWADDR_i ( uart.aw_addr ),
|
||||
.AWLEN_i ( uart.aw_len ),
|
||||
.AWSIZE_i ( uart.aw_size ),
|
||||
.AWBURST_i ( uart.aw_burst ),
|
||||
.AWLOCK_i ( uart.aw_lock ),
|
||||
.AWCACHE_i ( uart.aw_cache ),
|
||||
.AWPROT_i ( uart.aw_prot ),
|
||||
.AWREGION_i( uart.aw_region ),
|
||||
.AWUSER_i ( uart.aw_user ),
|
||||
.AWQOS_i ( uart.aw_qos ),
|
||||
.AWVALID_i ( uart.aw_valid ),
|
||||
.AWREADY_o ( uart.aw_ready ),
|
||||
.WDATA_i ( uart.w_data ),
|
||||
.WSTRB_i ( uart.w_strb ),
|
||||
.WLAST_i ( uart.w_last ),
|
||||
.WUSER_i ( uart.w_user ),
|
||||
.WVALID_i ( uart.w_valid ),
|
||||
.WREADY_o ( uart.w_ready ),
|
||||
.BID_o ( uart.b_id ),
|
||||
.BRESP_o ( uart.b_resp ),
|
||||
.BVALID_o ( uart.b_valid ),
|
||||
.BUSER_o ( uart.b_user ),
|
||||
.BREADY_i ( uart.b_ready ),
|
||||
.ARID_i ( uart.ar_id ),
|
||||
.ARADDR_i ( uart.ar_addr ),
|
||||
.ARLEN_i ( uart.ar_len ),
|
||||
.ARSIZE_i ( uart.ar_size ),
|
||||
.ARBURST_i ( uart.ar_burst ),
|
||||
.ARLOCK_i ( uart.ar_lock ),
|
||||
.ARCACHE_i ( uart.ar_cache ),
|
||||
.ARPROT_i ( uart.ar_prot ),
|
||||
.ARREGION_i( uart.ar_region ),
|
||||
.ARUSER_i ( uart.ar_user ),
|
||||
.ARQOS_i ( uart.ar_qos ),
|
||||
.ARVALID_i ( uart.ar_valid ),
|
||||
.ARREADY_o ( uart.ar_ready ),
|
||||
.RID_o ( uart.r_id ),
|
||||
.RDATA_o ( uart.r_data ),
|
||||
.RRESP_o ( uart.r_resp ),
|
||||
.RLAST_o ( uart.r_last ),
|
||||
.RUSER_o ( uart.r_user ),
|
||||
.RVALID_o ( uart.r_valid ),
|
||||
.RREADY_i ( uart.r_ready ),
|
||||
.PENABLE ( uart_penable ),
|
||||
.PWRITE ( uart_pwrite ),
|
||||
.PADDR ( uart_paddr ),
|
||||
.PSEL ( uart_psel ),
|
||||
.PWDATA ( uart_pwdata ),
|
||||
.PRDATA ( uart_prdata ),
|
||||
.PREADY ( uart_pready ),
|
||||
.PSLVERR ( uart_pslverr )
|
||||
);
|
||||
|
||||
axi_protocol_converter_0 i_axi_to_axi_lite (
|
||||
.aclk ( clk_i ),
|
||||
.aresetn ( rst_ni ),
|
||||
|
||||
.s_axi_awaddr ( s_axi_uart_awaddr ),
|
||||
.s_axi_awlen ( s_axi_uart_awlen ),
|
||||
.s_axi_awsize ( s_axi_uart_awsize ),
|
||||
.s_axi_awburst ( s_axi_uart_awburst ),
|
||||
.s_axi_awlock ( s_axi_uart_awlock ),
|
||||
.s_axi_awcache ( s_axi_uart_awcache ),
|
||||
.s_axi_awprot ( s_axi_uart_awprot ),
|
||||
.s_axi_awregion ( s_axi_uart_awregion ),
|
||||
.s_axi_awqos ( s_axi_uart_awqos ),
|
||||
.s_axi_awvalid ( s_axi_uart_awvalid ),
|
||||
.s_axi_awready ( s_axi_uart_awready ),
|
||||
.s_axi_wdata ( s_axi_uart_wdata ),
|
||||
.s_axi_wstrb ( s_axi_uart_wstrb ),
|
||||
.s_axi_wlast ( s_axi_uart_wlast ),
|
||||
.s_axi_wvalid ( s_axi_uart_wvalid ),
|
||||
.s_axi_wready ( s_axi_uart_wready ),
|
||||
.s_axi_bresp ( s_axi_uart_bresp ),
|
||||
.s_axi_bvalid ( s_axi_uart_bvalid ),
|
||||
.s_axi_bready ( s_axi_uart_bready ),
|
||||
.s_axi_araddr ( s_axi_uart_araddr ),
|
||||
.s_axi_arlen ( s_axi_uart_arlen ),
|
||||
.s_axi_arsize ( s_axi_uart_arsize ),
|
||||
.s_axi_arburst ( s_axi_uart_arburst ),
|
||||
.s_axi_arlock ( s_axi_uart_arlock ),
|
||||
.s_axi_arcache ( s_axi_uart_arcache ),
|
||||
.s_axi_arprot ( s_axi_uart_arprot ),
|
||||
.s_axi_arregion ( s_axi_uart_arregion ),
|
||||
.s_axi_arqos ( s_axi_uart_arqos ),
|
||||
.s_axi_arvalid ( s_axi_uart_arvalid ),
|
||||
.s_axi_arready ( s_axi_uart_arready ),
|
||||
.s_axi_rdata ( s_axi_uart_rdata ),
|
||||
.s_axi_rresp ( s_axi_uart_rresp ),
|
||||
.s_axi_rlast ( s_axi_uart_rlast ),
|
||||
.s_axi_rvalid ( s_axi_uart_rvalid ),
|
||||
.s_axi_rready ( s_axi_uart_rready ),
|
||||
|
||||
.m_axi_awaddr ( m_axi_uart_awaddr ),
|
||||
.m_axi_awprot ( ),
|
||||
.m_axi_awvalid ( m_axi_uart_awvalid ),
|
||||
.m_axi_awready ( m_axi_uart_awready ),
|
||||
.m_axi_wdata ( m_axi_uart_wdata ),
|
||||
.m_axi_wstrb ( m_axi_uart_wstrb ),
|
||||
.m_axi_wvalid ( m_axi_uart_wvalid ),
|
||||
.m_axi_wready ( m_axi_uart_wready ),
|
||||
.m_axi_bresp ( m_axi_uart_bresp ),
|
||||
.m_axi_bvalid ( m_axi_uart_bvalid ),
|
||||
.m_axi_bready ( m_axi_uart_bready ),
|
||||
.m_axi_araddr ( m_axi_uart_araddr ),
|
||||
.m_axi_arprot ( ),
|
||||
.m_axi_arvalid ( m_axi_uart_arvalid ),
|
||||
.m_axi_arready ( m_axi_uart_arready ),
|
||||
.m_axi_rdata ( m_axi_uart_rdata ),
|
||||
.m_axi_rresp ( m_axi_uart_rresp ),
|
||||
.m_axi_rvalid ( m_axi_uart_rvalid ),
|
||||
.m_axi_rready ( m_axi_uart_rready )
|
||||
apb_uart i_apb_uart (
|
||||
.CLK ( clk_i ),
|
||||
.RSTN ( rst_ni ),
|
||||
.PSEL ( uart_psel ),
|
||||
.PENABLE ( uart_penable ),
|
||||
.PWRITE ( uart_pwrite ),
|
||||
.PADDR ( uart_paddr[4:2] ),
|
||||
.PWDATA ( uart_pwdata ),
|
||||
.PRDATA ( uart_prdata ),
|
||||
.PREADY ( uart_pready ),
|
||||
.PSLVERR ( uart_pslverr ),
|
||||
.INT ( irq_sources[0] ),
|
||||
.OUT1N ( ), // keep open
|
||||
.OUT2N ( ), // keep open
|
||||
.RTSN ( ), // no flow control
|
||||
.DTRN ( ), // no flow control
|
||||
.CTSN ( 1'b0 ),
|
||||
.DSRN ( 1'b0 ),
|
||||
.DCDN ( 1'b0 ),
|
||||
.RIN ( 1'b0 ),
|
||||
.SIN ( rx_i ),
|
||||
.SOUT ( tx_o )
|
||||
);
|
||||
|
||||
axi_uartlite_1 i_axi_uart (
|
||||
.s_axi_aclk ( clk_i ),
|
||||
.s_axi_aresetn ( rst_ni ),
|
||||
.interrupt ( irq_sources[0] ),
|
||||
.s_axi_awaddr ( m_axi_uart_awaddr[3:0] ),
|
||||
.s_axi_awvalid ( m_axi_uart_awvalid ),
|
||||
.s_axi_awready ( m_axi_uart_awready ),
|
||||
.s_axi_wdata ( m_axi_uart_wdata ),
|
||||
.s_axi_wstrb ( m_axi_uart_wstrb ),
|
||||
.s_axi_wvalid ( m_axi_uart_wvalid ),
|
||||
.s_axi_wready ( m_axi_uart_wready ),
|
||||
.s_axi_bresp ( m_axi_uart_bresp ),
|
||||
.s_axi_bvalid ( m_axi_uart_bvalid ),
|
||||
.s_axi_bready ( m_axi_uart_bready ),
|
||||
.s_axi_araddr ( m_axi_uart_araddr[3:0] ),
|
||||
.s_axi_arvalid ( m_axi_uart_arvalid ),
|
||||
.s_axi_arready ( m_axi_uart_arready ),
|
||||
.s_axi_rdata ( m_axi_uart_rdata ),
|
||||
.s_axi_rresp ( m_axi_uart_rresp ),
|
||||
.s_axi_rvalid ( m_axi_uart_rvalid ),
|
||||
.s_axi_rready ( m_axi_uart_rready ),
|
||||
.rx ( rx_i ),
|
||||
.tx ( tx_o )
|
||||
);
|
||||
// xlnx_axi_ethernetlite i_xlnx_axi_ethernetlite (
|
||||
|
||||
// );
|
||||
|
||||
// output ip2intc_irpt;
|
||||
// input s_axi_aclk;
|
||||
// input s_axi_aresetn;
|
||||
// input [3:0]s_axi_awid;
|
||||
// input [12:0]s_axi_awaddr;
|
||||
// input [7:0]s_axi_awlen;
|
||||
// input [2:0]s_axi_awsize;
|
||||
// input [1:0]s_axi_awburst;
|
||||
// input [3:0]s_axi_awcache;
|
||||
// input s_axi_awvalid;
|
||||
// output s_axi_awready;
|
||||
// input [31:0]s_axi_wdata;
|
||||
// input [3:0]s_axi_wstrb;
|
||||
// input s_axi_wlast;
|
||||
// input s_axi_wvalid;
|
||||
// output s_axi_wready;
|
||||
// output [3:0]s_axi_bid;
|
||||
// output [1:0]s_axi_bresp;
|
||||
// output s_axi_bvalid;
|
||||
// input s_axi_bready;
|
||||
// input [3:0]s_axi_arid;
|
||||
// input [12:0]s_axi_araddr;
|
||||
// input [7:0]s_axi_arlen;
|
||||
// input [2:0]s_axi_arsize;
|
||||
// input [1:0]s_axi_arburst;
|
||||
// input [3:0]s_axi_arcache;
|
||||
// input s_axi_arvalid;
|
||||
// output s_axi_arready;
|
||||
// output [3:0]s_axi_rid;
|
||||
// output [31:0]s_axi_rdata;
|
||||
// output [1:0]s_axi_rresp;
|
||||
// output s_axi_rlast;
|
||||
// output s_axi_rvalid;
|
||||
// input s_axi_rready;
|
||||
|
||||
// input phy_tx_clk ( eth_txck ),
|
||||
// input phy_rx_clk ( eth_rxck ),
|
||||
// input phy_crs ( ),
|
||||
// input phy_dv ( ),
|
||||
// input [3:0] phy_rx_data ( eth_rxd ),
|
||||
// input phy_col ( ),
|
||||
// input phy_rx_er ( ),
|
||||
// output phy_rst_n ( eth_rst_n ),
|
||||
// output phy_tx_en ( eth_tx_en ),
|
||||
// output [3:0] phy_tx_data ( eth_txd ),
|
||||
// input phy_mdio_i ( phy_mdio_i ),
|
||||
// output phy_mdio_o ( phy_mdio_o ),
|
||||
// output phy_mdio_t ( phy_mdio_t ),
|
||||
// output phy_mdc ( eth_mdc )
|
||||
|
||||
// assign eth_mdio = phy_mdio_t ? phy_mdio_i : 1'bz;
|
||||
// assign phy_mdio_i = phy_mdio_t ? 1'b0 : eth_mdio;
|
||||
|
||||
// // active low
|
||||
// assign eth_int_b = 1'b1;
|
||||
// // set floating - power management event
|
||||
// assign eth_pme_b = 1'b1;
|
||||
|
||||
endmodule
|
||||
|
|
@ -62,12 +62,13 @@
|
|||
compatible = "ns16750";
|
||||
reg = <0x0 0x10000000 0x0 0x1000>;
|
||||
clock-frequency = <50000000>;
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&PLIC0>;
|
||||
interrupts = <1>;
|
||||
reg-shift = <2>; //regs are spaced on 32 bit boundary
|
||||
reg-io-width = <4>; // only 32-bit access are supported
|
||||
};
|
||||
// axi_ethernetlite_1: ethernet@20000000 {
|
||||
// xlnx_axi_ethernetlite: ethernet@12000000 {
|
||||
// compatible = "xlnx,axi-ethernetlite-3.0", "xlnx,xps-ethernetlite-1.00.a";
|
||||
// device_type = "network";
|
||||
// interrupt-parent = <&PLIC0>;
|
||||
|
|
@ -81,18 +82,21 @@
|
|||
// xlnx,include-mdio = <0x1>;
|
||||
// xlnx,instance = "axi_ethernetlite_inst";
|
||||
// xlnx,rx-ping-pong = <0x1>;
|
||||
// xlnx,s-axi-id-width = <0x1>;
|
||||
// xlnx,s-axi-id-width = <0x4>;
|
||||
// xlnx,tx-ping-pong = <0x1>;
|
||||
// xlnx,use-internal = <0x0>;
|
||||
// xlnx,has-mdio = <0x1>;
|
||||
// // rgmii-id: combines rgmii-rxid and rgmii-txid and thus configures the
|
||||
// // PHY to enable the RX and TX delays. The MAC should neither add the RX
|
||||
// // nor TX delay in this case.
|
||||
// phy-mode = "rgmii-id";
|
||||
// mdio {
|
||||
// #address-cells = <1>;
|
||||
// #size-cells = <0>;
|
||||
// phy0: phy@0 {
|
||||
// compatible = "marvell,88e1111";
|
||||
// phy0: ethernet-phy@0 {
|
||||
// compatible = "realtek,RTL8211E";
|
||||
// device_type = "ethernet-phy";
|
||||
// reg = <0>;
|
||||
// marvell,reg-init = <2 21 0xffef 0x00 0x0 0 0x7fff 0x8000>;
|
||||
// reg = <0x1>;
|
||||
// };
|
||||
// };
|
||||
// };
|
||||
|
|
@ -109,6 +113,6 @@
|
|||
// }
|
||||
};
|
||||
chosen {
|
||||
stdout-path = "/uart@10000000";
|
||||
stdout-path = "/sco/uart@10000000";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -20,37 +20,43 @@ module bootrom (
|
|||
input logic [63:0] addr_i,
|
||||
output logic [63:0] rdata_o
|
||||
);
|
||||
localparam int RomSize = 211;
|
||||
localparam int RomSize = 233;
|
||||
|
||||
const logic [RomSize-1:0][63:0] mem = {
|
||||
64'h006b,
|
||||
64'h636f6c63_00737470,
|
||||
64'h006874_61702d74,
|
||||
64'h756f6474_73006874,
|
||||
64'h6469772d_6f692d67,
|
||||
64'h65720074_66696873,
|
||||
64'h2d676572_00737470,
|
||||
64'h75727265_746e6900,
|
||||
64'h746e6572_61702d74,
|
||||
64'h70757272_65746e69,
|
||||
64'h00766564_6e2c7663,
|
||||
64'h73697200_79746972,
|
||||
64'h6f697270_2d78616d,
|
||||
64'h2c766373_69720073,
|
||||
64'h656d616e_2d676572,
|
||||
64'h00646564_6e657478,
|
||||
64'h652d7374_70757272,
|
||||
64'h65746e69_00736567,
|
||||
64'h6e617200_656c646e,
|
||||
64'h6168702c_78756e69,
|
||||
64'h6c007265_6c6c6f72,
|
||||
64'h746e6f63_2d747075,
|
||||
64'h72726574_6e690073,
|
||||
64'h6c6c6563_2d747075,
|
||||
64'h72726574_6e692300,
|
||||
64'h79636e65_75716572,
|
||||
64'h662d6b63_6f6c6300,
|
||||
64'h00646565_70732d74,
|
||||
64'h6e657272_75630076,
|
||||
64'h65646e2c_76637369,
|
||||
64'h72007974_69726f69,
|
||||
64'h72702d78_616d2c76,
|
||||
64'h63736972_0073656d,
|
||||
64'h616e2d67_65720064,
|
||||
64'h65646e65_7478652d,
|
||||
64'h73747075_72726574,
|
||||
64'h6e690073_65676e61,
|
||||
64'h7200656c_646e6168,
|
||||
64'h702c7875_6e696c00,
|
||||
64'h72656c6c_6f72746e,
|
||||
64'h6f632d74_70757272,
|
||||
64'h65746e69_00736c6c,
|
||||
64'h65632d74_70757272,
|
||||
64'h65746e69_23007469,
|
||||
64'h6c70732d_626c7400,
|
||||
64'h65707974_2d756d6d,
|
||||
64'h00617369_2c766373,
|
||||
64'h69720073_75746174,
|
||||
64'h73006765_72006570,
|
||||
64'h79745f65_63697665,
|
||||
64'h64007963_6e657571,
|
||||
64'h6572662d_6b636f6c,
|
||||
64'h63007963_6e657571,
|
||||
64'h6572662d_65736162,
|
||||
64'h656d6974_006c6564,
|
||||
64'h6f6d0065_6c626974,
|
||||
|
|
@ -59,135 +65,151 @@ module bootrom (
|
|||
64'h2300736c_6c65632d,
|
||||
64'h73736572_64646123,
|
||||
64'h09000000_02000000,
|
||||
64'h02000000_00003030,
|
||||
64'h30303030_30314074,
|
||||
64'h7261752f_6f63732f,
|
||||
64'h3b010000_13000000,
|
||||
64'h03000000_00006e65,
|
||||
64'h736f6863_01000000,
|
||||
64'h02000000_02000000,
|
||||
64'h80f0fa02_0c010000,
|
||||
64'h04000000_2e010000,
|
||||
64'h04000000_03000000,
|
||||
64'h02000000_01000000,
|
||||
64'h00000000_01010000,
|
||||
64'h0c000000_03000000,
|
||||
64'h02000000_f0000000,
|
||||
64'h02000000_24010000,
|
||||
64'h04000000_03000000,
|
||||
64'h01000000_19010000,
|
||||
64'h04000000_03000000,
|
||||
64'h02000000_08010000,
|
||||
64'h04000000_03000000,
|
||||
64'h00c20100_fa000000,
|
||||
64'h04000000_03000000,
|
||||
64'h80f0fa02_3f000000,
|
||||
64'h04000000_03000000,
|
||||
64'h00000100_00000000,
|
||||
64'h00000010_00000000,
|
||||
64'h4b000000_10000000,
|
||||
64'h03000000_00000000,
|
||||
64'h612e3230_2e312d65,
|
||||
64'h74696c74_7261752d,
|
||||
64'h6978612c_786e6c78,
|
||||
64'h1b000000_19000000,
|
||||
64'h03000000_00000030,
|
||||
64'h30303030_30303140,
|
||||
64'h74726175_01000000,
|
||||
64'h02000000_006c6f72,
|
||||
64'h746e6f63_c8000000,
|
||||
64'h08000000_03000000,
|
||||
64'h00100000_00000000,
|
||||
64'h00000000_00000000,
|
||||
64'h4b000000_10000000,
|
||||
64'h03000000_ffff0000,
|
||||
64'h01000000_b4000000,
|
||||
64'h00000010_00000000,
|
||||
64'h5b000000_10000000,
|
||||
64'h03000000_00303537,
|
||||
64'h3631736e_1b000000,
|
||||
64'h08000000_03000000,
|
||||
64'h00333130_2d677562,
|
||||
64'h65642c76_63736972,
|
||||
64'h1b000000_10000000,
|
||||
64'h03000000_00003040,
|
||||
64'h72656c6c_6f72746e,
|
||||
64'h6f632d67_75626564,
|
||||
64'h00000030_30303030,
|
||||
64'h30303140_74726175,
|
||||
64'h01000000_02000000,
|
||||
64'h02000000_a5000000,
|
||||
64'h04000000_03000000,
|
||||
64'h02000000_9f000000,
|
||||
64'h04000000_03000000,
|
||||
64'h35000000_e5000000,
|
||||
64'h04000000_03000000,
|
||||
64'h07000000_d2000000,
|
||||
64'h04000000_03000000,
|
||||
64'h006c6f72_746e6f63,
|
||||
64'hc8000000_08000000,
|
||||
64'hd2000000_08000000,
|
||||
64'h03000000_00100000,
|
||||
64'h00000000_00000000,
|
||||
64'h00000000_5b000000,
|
||||
64'h10000000_03000000,
|
||||
64'hffff0000_01000000,
|
||||
64'hbe000000_08000000,
|
||||
64'h03000000_00333130,
|
||||
64'h2d677562_65642c76,
|
||||
64'h63736972_1b000000,
|
||||
64'h10000000_03000000,
|
||||
64'h00003040_72656c6c,
|
||||
64'h6f72746e_6f632d67,
|
||||
64'h75626564_01000000,
|
||||
64'h02000000_02000000,
|
||||
64'haf000000_04000000,
|
||||
64'h03000000_02000000,
|
||||
64'ha9000000_04000000,
|
||||
64'h03000000_02000000,
|
||||
64'hef000000_04000000,
|
||||
64'h03000000_07000000,
|
||||
64'hdc000000_04000000,
|
||||
64'h03000000_00000004,
|
||||
64'h00000000_0000000c,
|
||||
64'h00000000_4b000000,
|
||||
64'h00000000_5b000000,
|
||||
64'h10000000_03000000,
|
||||
64'h09000000_01000000,
|
||||
64'h0b000000_01000000,
|
||||
64'hb4000000_10000000,
|
||||
64'h03000000_8a000000,
|
||||
64'hbe000000_10000000,
|
||||
64'h03000000_94000000,
|
||||
64'h00000000_03000000,
|
||||
64'h00306369_6c702c76,
|
||||
64'h63736972_1b000000,
|
||||
64'h0c000000_03000000,
|
||||
64'h01000000_79000000,
|
||||
64'h01000000_83000000,
|
||||
64'h04000000_03000000,
|
||||
64'h00000000_00000000,
|
||||
64'h04000000_03000000,
|
||||
64'h00000000_30303030,
|
||||
64'h30306340_72656c6c,
|
||||
64'h6f72746e_6f632d74,
|
||||
64'h70757272_65746e69,
|
||||
64'h01000000_02000000,
|
||||
64'h00000c00_00000000,
|
||||
64'h00000002_00000000,
|
||||
64'h4b000000_10000000,
|
||||
64'h03000000_07000000,
|
||||
64'h01000000_03000000,
|
||||
64'h01000000_b4000000,
|
||||
64'h006c6f72_746e6f63,
|
||||
64'hd2000000_08000000,
|
||||
64'h03000000_00000c00,
|
||||
64'h00000000_00000002,
|
||||
64'h00000000_5b000000,
|
||||
64'h10000000_03000000,
|
||||
64'h00000000_30746e69,
|
||||
64'h6c632c76_63736972,
|
||||
64'h1b000000_0d000000,
|
||||
64'h03000000_00000030,
|
||||
64'h30303030_30324074,
|
||||
64'h6e696c63_01000000,
|
||||
64'had000000_00000000,
|
||||
64'h03000000_00007375,
|
||||
64'h622d656c_706d6973,
|
||||
64'h00636f73_2d657261,
|
||||
64'h622d656e_61697261,
|
||||
64'h2c687465_1b000000,
|
||||
64'h1f000000_03000000,
|
||||
64'h02000000_0f000000,
|
||||
64'h04000000_03000000,
|
||||
64'h02000000_00000000,
|
||||
64'h04000000_03000000,
|
||||
64'h00636f73_01000000,
|
||||
64'h02000000_00000002,
|
||||
64'h00000000_00000080,
|
||||
64'h00000000_4b000000,
|
||||
64'h10000000_03000000,
|
||||
64'h00007972_6f6d656d,
|
||||
64'h3f000000_07000000,
|
||||
64'h03000000_00303030,
|
||||
64'h30303030_38407972,
|
||||
64'h6f6d656d_01000000,
|
||||
64'h02000000_02000000,
|
||||
64'h02000000_01000000,
|
||||
64'ha5000000_04000000,
|
||||
64'h07000000_01000000,
|
||||
64'h03000000_01000000,
|
||||
64'h9f000000_04000000,
|
||||
64'h03000000_00006374,
|
||||
64'h6e692d75_70632c76,
|
||||
64'h63736972_1b000000,
|
||||
64'h0f000000_03000000,
|
||||
64'h8a000000_00000000,
|
||||
64'h03000000_01000000,
|
||||
64'h79000000_04000000,
|
||||
64'hbe000000_10000000,
|
||||
64'h03000000_00000000,
|
||||
64'h72656c6c_6f72746e,
|
||||
64'h6f632d74_70757272,
|
||||
64'h65746e69_01000000,
|
||||
64'h80f0fa02_69000000,
|
||||
64'h30746e69_6c632c76,
|
||||
64'h63736972_1b000000,
|
||||
64'h0d000000_03000000,
|
||||
64'h00000030_30303030,
|
||||
64'h30324074_6e696c63,
|
||||
64'h01000000_b7000000,
|
||||
64'h00000000_03000000,
|
||||
64'h00007375_622d656c,
|
||||
64'h706d6973_00636f73,
|
||||
64'h2d657261_622d656e,
|
||||
64'h61697261_2c687465,
|
||||
64'h1b000000_1f000000,
|
||||
64'h03000000_02000000,
|
||||
64'h0f000000_04000000,
|
||||
64'h03000000_02000000,
|
||||
64'h00000000_04000000,
|
||||
64'h03000000_00636f73,
|
||||
64'h01000000_02000000,
|
||||
64'h00000008_00000000,
|
||||
64'h00000080_00000000,
|
||||
64'h5b000000_10000000,
|
||||
64'h03000000_00007972,
|
||||
64'h6f6d656d_4f000000,
|
||||
64'h07000000_03000000,
|
||||
64'h00303030_30303030,
|
||||
64'h38407972_6f6d656d,
|
||||
64'h01000000_02000000,
|
||||
64'h02000000_02000000,
|
||||
64'h01000000_af000000,
|
||||
64'h04000000_03000000,
|
||||
64'h01000000_a9000000,
|
||||
64'h04000000_03000000,
|
||||
64'h00006374_6e692d75,
|
||||
64'h70632c76_63736972,
|
||||
64'h1b000000_0f000000,
|
||||
64'h03000000_94000000,
|
||||
64'h00000000_03000000,
|
||||
64'h01000000_83000000,
|
||||
64'h04000000_03000000,
|
||||
64'h00000000_72656c6c,
|
||||
64'h6f72746e_6f632d74,
|
||||
64'h70757272_65746e69,
|
||||
64'h01000000_79000000,
|
||||
64'h00000000_03000000,
|
||||
64'h40787d01_2c000000,
|
||||
64'h04000000_03000000,
|
||||
64'h00003933_76732c76,
|
||||
64'h63736972_60000000,
|
||||
64'h63736972_70000000,
|
||||
64'h0b000000_03000000,
|
||||
64'h00636d69_34367672,
|
||||
64'h56000000_08000000,
|
||||
64'h03000000_00000076,
|
||||
64'h63736972_1b000000,
|
||||
64'h06000000_03000000,
|
||||
64'h00007573_63616d69,
|
||||
64'h34367672_66000000,
|
||||
64'h0b000000_03000000,
|
||||
64'h00000076_63736972,
|
||||
64'h00656e61_69726120,
|
||||
64'h2c687465_1b000000,
|
||||
64'h12000000_03000000,
|
||||
64'h00000000_79616b6f,
|
||||
64'h4f000000_05000000,
|
||||
64'h5f000000_05000000,
|
||||
64'h03000000_00000000,
|
||||
64'h4b000000_04000000,
|
||||
64'h5b000000_04000000,
|
||||
64'h03000000_00757063,
|
||||
64'h4f000000_04000000,
|
||||
64'h03000000_00000000,
|
||||
64'h3f000000_04000000,
|
||||
64'h03000000_00000030,
|
||||
64'h40757063_01000000,
|
||||
|
|
@ -213,11 +235,11 @@ module bootrom (
|
|||
64'h00000000_01000000,
|
||||
64'h00000000_00000000,
|
||||
64'h00000000_00000000,
|
||||
64'hc8040000_12010000,
|
||||
64'h48050000_47010000,
|
||||
64'h00000000_10000000,
|
||||
64'h11000000_28000000,
|
||||
64'h00050000_38000000,
|
||||
64'h12060000_edfe0dd0,
|
||||
64'h80050000_38000000,
|
||||
64'hc7060000_edfe0dd0,
|
||||
64'h00000000_00000000,
|
||||
64'h00000000_00000000,
|
||||
64'h00000000_00000000,
|
||||
|
|
|
|||
|
|
@ -39,5 +39,5 @@ package ariane_soc;
|
|||
localparam logic[63:0] CLINTLength = 64'hC0000;
|
||||
localparam logic[63:0] PLICLength = 64'h3FF_FFFF;
|
||||
localparam logic[63:0] UARTLength = 64'h10000;
|
||||
localparam logic[63:0] DRAMLength = 64'h4000000;
|
||||
localparam logic[63:0] DRAMLength = 64'h8000000;
|
||||
endpackage
|
||||
|
|
@ -322,60 +322,25 @@ module ariane_testharness #(
|
|||
);
|
||||
|
||||
// ---------------
|
||||
// PLIC
|
||||
// Peripherals
|
||||
// ---------------
|
||||
logic [ariane_soc::NumTargets-1:0] irqs;
|
||||
logic [ariane_soc::NumSources-1:0] irq_sources;
|
||||
logic tx, rx;
|
||||
logic [1:0] irqs;
|
||||
|
||||
AXI_LITE #(
|
||||
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
|
||||
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH )
|
||||
) axi_lite_plic ();
|
||||
|
||||
REG_BUS #(
|
||||
.ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
|
||||
.DATA_WIDTH ( AXI_DATA_WIDTH )
|
||||
) reg_bus (clk_i);
|
||||
|
||||
axi_to_axi_lite i_axi_to_axi_lite_eth (
|
||||
.clk_i,
|
||||
.rst_ni,
|
||||
.testmode_i ( 1'b0 ),
|
||||
.in ( master[ariane_soc::PLIC] ),
|
||||
.out ( axi_lite_plic )
|
||||
ariane_peripherals #(
|
||||
.AxiAddrWidth ( AXI_ADDRESS_WIDTH ),
|
||||
.AxiDataWidth ( AXI_DATA_WIDTH )
|
||||
) i_ariane_peripherals (
|
||||
.clk_i ( clk_i ),
|
||||
.rst_ni ( ndmreset_n ),
|
||||
.plic ( master[ariane_soc::PLIC] ),
|
||||
.uart ( master[ariane_soc::UART] ),
|
||||
.irq_o ( irqs ),
|
||||
.rx_i ( rx ),
|
||||
.tx_o ( tx )
|
||||
);
|
||||
|
||||
axi_lite_to_reg #(
|
||||
.ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
|
||||
.DATA_WIDTH ( AXI_DATA_WIDTH )
|
||||
) i_axi_lite_to_reg (
|
||||
.clk_i,
|
||||
.rst_ni,
|
||||
.axi_i ( axi_lite_plic ), // AXI Lite
|
||||
.reg_o ( reg_bus )
|
||||
);
|
||||
|
||||
plic #(
|
||||
.ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
|
||||
.DATA_WIDTH ( AXI_DATA_WIDTH ),
|
||||
.ID_BITWIDTH ( 2 ), // TODO (zarubaf): Find propper width
|
||||
.PARAMETER_BITWIDTH ( 2 ), // TODO (zarubaf): Find propper width
|
||||
.NUM_TARGETS ( ariane_soc::NumTargets ),
|
||||
.NUM_SOURCES ( ariane_soc::NumSources )
|
||||
) i_plic (
|
||||
.clk_i,
|
||||
.rst_ni ( ndmreset_n ),
|
||||
.irq_sources_i ( irq_sources ),
|
||||
.eip_targets_o ( irqs ),
|
||||
.external_bus_io ( reg_bus )
|
||||
);
|
||||
|
||||
// ---------------
|
||||
// Peripheral
|
||||
// ---------------
|
||||
mock_uartlite i_mock_uartlite (.clk_i(clk_i), .rst_ni(rst_ni), .slave(master[ariane_soc::UART]));
|
||||
// tie-off uart here
|
||||
assign irq_sources = '0;
|
||||
uart_bus #(.BAUD_RATE(115200), .PARITY_EN(0)) i_uart_bus (.rx(tx), .tx(rx), .rx_en(1'b1));
|
||||
|
||||
// ---------------
|
||||
// Core
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue