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Adapt parameterization assertions l15 adapter to allow for different associativity in I and D cache.

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Michael Schaffner 2018-11-14 08:56:39 +01:00
parent 34de5d2739
commit a99a176add
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GPG key ID: 7AA09AE049819C2C
3 changed files with 7 additions and 13 deletions
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2
include/serpent_cache_pkg.sv
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@ -33,7 +33,7 @@ package serpent_cache_pkg;
localparam L15_TID_WIDTH = `L15_THREADID_WIDTH;
localparam L15_TLB_CSM_WIDTH = `TLB_CSM_WIDTH;
`else
localparam L15_SET_ASSOC = 4;
localparam L15_SET_ASSOC = ariane_pkg::DCACHE_SET_ASSOC;// align with dcache for compatibility with the standard Ariane setup
localparam L15_TID_WIDTH = 2;
localparam L15_TLB_CSM_WIDTH = 33;
`endif

5
src/cache_subsystem/serpent_cache_subsystem.sv
View file

@ -169,9 +169,8 @@ serpent_l15_adapter #(
// and serpent cache system with the standard AXI-based testharness
`ifdef AXI64_CACHE_PORTS
// this is static at the moment due to the openpiton config.
// TODO: make this parameterizable in the future
localparam AXI_NUM_WORDS = 4;
// support up to 512bit cache lines
localparam AXI_NUM_WORDS = 8;
logic axi_rd_req, axi_rd_gnt;
logic [63:0] axi_rd_addr, axi_wr_addr;

13
src/cache_subsystem/serpent_l15_adapter.sv
View file

@ -383,19 +383,14 @@ fifo_v2 #(
initial begin
// assert wrong parameterizations
assert (L15_SET_ASSOC == ICACHE_SET_ASSOC)
else $fatal(1,"[l15_adapter] number of icache ways not aligned with L15");
assert (L15_SET_ASSOC >= ICACHE_SET_ASSOC)
else $fatal(1,"[l15_adapter] number of icache ways must be smaller or equal the number of L15 ways");
// assert wrong parameterizations
assert (L15_SET_ASSOC == DCACHE_SET_ASSOC)
else $fatal(1,"[l15_adapter] number of dcache ways not aligned with L15");
assert (L15_SET_ASSOC >= DCACHE_SET_ASSOC)
else $fatal(1,"[l15_adapter] number of dcache ways must be smaller or equal the number of L15 ways");
// invalidation address returned by L1.5 is 16 bit
assert (16 >= DCACHE_INDEX_WIDTH && 16 >= ICACHE_INDEX_WIDTH)
else $fatal(1,"[l15_adapter] maximum number of index bits supported by L1.5 is 16");
// assert mismatch of cache line width
assert (ICACHE_LINE_WIDTH==256)
else $fatal(1,"[l15_adapter] ichache lines are currently restricted to 256 bits");
assert (DCACHE_LINE_WIDTH==128)
else $fatal(1,"[l15_adapter] dchache lines are currently restricted to 128 bits");
end
`endif
//pragma translate_on